JPS6439653U - - Google Patents
Info
- Publication number
- JPS6439653U JPS6439653U JP13352387U JP13352387U JPS6439653U JP S6439653 U JPS6439653 U JP S6439653U JP 13352387 U JP13352387 U JP 13352387U JP 13352387 U JP13352387 U JP 13352387U JP S6439653 U JPS6439653 U JP S6439653U
- Authority
- JP
- Japan
- Prior art keywords
- groups
- integrated circuit
- studs
- correspondence
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の集積回路素子の一実施例を示
す実装状態の一部断面側面図、第２図はその要部
の分解斜視図、第３図はその縦断面図、第４図は
従来の集積回路素子の実装例を示す分解斜視図、
第５図はその一部断面側面図である。
１……プリント基板、５……ソケツト接触子、
１０……集積回路素子、１４……スタツド。
FIG. 1 is a partially sectional side view showing an embodiment of the integrated circuit device of the present invention in a mounted state, FIG. 2 is an exploded perspective view of its main parts, FIG. 3 is a vertical sectional view, and FIG. An exploded perspective view showing an example of mounting a conventional integrated circuit element,
FIG. 5 is a partially sectional side view thereof. 1... Printed circuit board, 5... Socket contact,
10... integrated circuit element, 14... stud.
Claims (1)
あるスタツド１４群に、挿着可能に対応配置され
たソケツト接触子５群を、本体内部に一体構造で
設置して成ることを特徴とする集積回路素子。 An integrated circuit characterized in that 5 groups of socket contacts are arranged in correspondence with 14 groups of studs, which are pin contacts vertically arranged on a printed circuit board 1, so that they can be inserted into the main body. circuit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13352387U JPS6439653U (en) | 1987-09-01 | 1987-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13352387U JPS6439653U (en) | 1987-09-01 | 1987-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6439653U true JPS6439653U (en) | 1989-03-09 |
Family
ID=31391461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13352387U Pending JPS6439653U (en) | 1987-09-01 | 1987-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6439653U (en) |
-
1987
- 1987-09-01 JP JP13352387U patent/JPS6439653U/ja active Pending