JPH0281596A - Video signal processor - Google Patents

Abstract

PURPOSE:To simplify a system by using a memory means for both noise reduction means, which eliminates noise with the use of the correlation of the field of a video signal, and flicker reduction means, which doubles field frequencies and decreases a surface flicker. CONSTITUTION:A noise reduction circuit 22 is made into a circulative type filter constitution, and it is repeatedly added with the use of a single filter memory 26. In the field memory 26, the signal is written by a write control signal VCLRO from a flicker reduction circuit 29, digital luminance data read and added by a read control signal VCLR2 are generally outputted through a digital/analog converting circuit 30 after noise reduction. The field memory 26 used for the noise reduction circuit 22 is shared with the field memory of the flicker reduction circuit 29. Thus, the whole system can be simplified, and costs can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital video signal processing device suitable for use in a digital television receiver or a digital video tape recorder.

[Summary of the invention]

The present invention relates to a digital video signal processing device suitable for use in a digital television receiver or a digital videotape recorder, and more specifically to a video signal processing device having a storage means for converting an analog video signal into a digital video signal and performing video signal processing. a noise reduction means for removing noise from the storage means using field correlation of the video signal;
The system is simplified by doubling the field frequency and also serving as flicker reduction means to reduce surface flicker, thereby reducing the cost of the digital video signal processing circuit.

[Conventional technology]

Recent IQTV (improved Definito
In the video signal system (N Te1evision), the video signal system is digitized, and high-definition, high-quality reproduced images are obtained using large-capacity storage means such as frame memory or field memory. FIG. 7 is a system diagram showing the configuration of such 10TV.

In the same figure, the RF multiplied signal received by the antenna is separated into a baseband video signal and an audio signal by the tuner, and the NTSC video signal is supplied to the input terminal (1) and converted from analog to digital in order to digitally process this analog signal. circuit(
2) is converted into a digital signal and supplied to the motion adaptive Y/C separation circuit (3) to extract the movement of the subject from the digital signal.The video part is processed by the line type Y/C separation circuit, and the still image part is In this case, processing is switched to a frame type Y/C separation circuit to compensate for deterioration in separation characteristics. (4) is a frame memory used to perform motion adaptive Y/C separation processing. The luminance signal data Y separated by the Y/C separation circuit (3) is supplied to the digital-to-analog conversion circuit (6) and converted into an analog luminance signal. The color signal data C is also demodulated in the color demodulation circuit (5), and the color difference signal data R-Y and B-Y are converted into analog color difference signal data in the digital-to-analog conversion circuits (7) and (8), respectively. Ru. The luminance signal and color difference signal converted into analog signals in this way are sent back to the analog-to-digital conversion circuit (9).
It is converted into digital data in steps (10) and (11).

It is helpful to perform digitization again in this way, and although it is not shown in the adaptive Y/C separation circuit (3), it is necessary to use a longer tarokku for chroma, but the next stage motion adaptive progressive scan conversion circuit (12) This is because cladding that is locked to the line must be used.

The motion-adaptive progressive scan conversion circuit (12) doubles the number of scanning lines compared to the conventional NTSC system, and the line-type scanning line interpolation processing and field-type scanning line interpolation processing depend on the presence or absence of subject movement. Therefore, motion-adaptive scan line interpolation is performed in which the interpolation mode is switched depending on the presence or absence of this motion. Frame memo! I (1
3) is a storage means for performing such operations. The output of the motion adaptive progressive scan conversion circuit (12) is converted into R (red), G (green), and B (blue) by the matrix circuit (14), and the number of scanning lines is doubled in the digital-to-analog conversion circuit (15). and is supplied to a cathode ray tube (CRT) (16). Of course, this CRT (16) is a high-definition cathode ray tube that scans at double speed, and the deflection coil (
17) has fv and 2fh from the synchronous deflection system circuit (19).
horizontal and vertical deflection signals are provided. Moreover, the analog-digital conversion circuits (2) and (15) are 4fs. (fs.

=Subkit rear) and 8fsc signals are supplied.

[Problem to be solved by the invention]

When digitally processing a video signal like in a conventional 10TV, a motion adaptive Y/C separation circuit (3) and a motion adaptive progressive scan conversion circuit (12) with different clocks etc. are used to process the Y/C signal digitally.
/C separation processing and sequential scan conversion processing are performed, but digital-analog conversion circuits (6), (7) (8), analog-digital conversion circuits (9), (10), (11
) and two frame memories (4), (13)
However, in order to digitize the video signal processing circuit, not only the circuit becomes complicated, but also an extra circuit must be added.

The present invention has been made in view of the above points, and its purpose is to standardize digital components such as frame memories, simplify digital video processing circuits, and construct them at low cost.

[Means to solve the problem]

An example of the video signal processing device of the present invention is as shown in FIG. The storage means (26) is equipped with a noise reduction means (22) that removes noise by utilizing the field correlation of the video signal, and a field frequency that is 2 times the field frequency.
It doubles as a flicker reduction means (27) for eliminating surface flicker.

[Effect]

According to the video signal processing device of the present invention, a noise reduction means for removing noise using field correlation;
The storage means (26) is also used as a flicker reduction means to reduce surface flicker by doubling the field frequency, which simplifies the circuit configuration by reducing the number of digital parts when digitizing the video signal processing circuit. You can.

〔Example〕

An embodiment of the video signal processing device of the present invention will be described below with reference to the drawings.

Figure 1 shows the luminance signal system when digitally processing the video signal processing circuit of a digital television receiver or digital video tape recorder.The frame memory of the noise reduction circuit is also used as the frame memory of the flicker reduction circuit. This figure shows the configuration.

In Figure 1, P A L (Phase Alternative)
on by line) method, or entrusted CAM (Se'q
uent+cel Couleur ame' moi
A video signal of a 50-field system with a vertical frequency of 50 Hz like the re) system passes through an analog Y/C separation circuit, and its luminance signal Y is supplied to the input terminal (20). This analog luminance signal is supplied to an analog-to-digital conversion circuit (21) and converted into digital luminance data. This digitally converted digital luminance data YO is supplied to a noise reduction circuit (22). The noise reduction circuit (22) has a recursive filter configuration, and is configured to perform repeated addition using one filter memo 'J (26). That is, the digital luminance data Y, is multiplied by 1- (where K is the attenuation amount Q<K<1>) and is supplied to the frame memory (26) through the adder circuit (24).

Next, it is multiplied by the circuit (25) and added by the addition circuit (24), and the field memo! Travel through the loop containing J (26).

In this process, noise components in the luminance signal are suppressed.

This suppression principle has different properties during addition between video signals and noise, and when adding signals Si with the same amplitude and frequency phase, if the adding circuit is M, the addition output So is So=M-3i
......[1] t'l, but to add the noise of the same effective value voltage Ni, if the adding circuit is M and the addition output is No, then No = N - N1... River (2) Therefore, the addition of the video signal is proportional to the adder circuit M, but the noise is proportional to the square root of the adder circuit, so the difference between the video signal and the noise becomes larger, and the S/N ratio improves.

In this kind of addition, noise can be suppressed by increasing K added with the same still image between fields, but in the case of a moving image, the picture is different for each field, so if different moving images are added in fields, it will look blurred. A motion detection circuit (28) is provided so that the noise is set to 0 without noise reduction, and 1 is set only for still images, and the L- circuit (23) and K circuit (25) are It's in control. The method for detecting motion is to calculate the difference between fields and supply it to the control terminal (27). The field memory (26) has a flicker reduction circuit (29) which will be described later.
) with the write control signal VCLRG from the write and read control signal V. The digital luminance data read out and added by LR2 is generally output with noise reduced through a digital-to-analog conversion circuit (30). In this example, this noise reduction circuit (22
) is shared with the field memory of the flicker reduction circuit (29). This flicker reduction circuit (29) is shown in Figure 2A.
This will be explained using a three-dimensional model of images and scanning lines shown in FIGS. In the PAL or SECAM system, the vertical frequency is 1 field (31) and 1 field (31) as shown in Figure 2 A and B.
The field (32) is increment scanned, and the interval between the l field (31), the i+l+2 field 2), the l+2 field (33), and so on is 507 and 20 μs. Since there is a problem in which flickering is noticeable in large screen areas, the field frequency is doubled to 100Hz, 1 as shown in Figure 3A and B.
This is to reduce flicker in the large screen portion by setting the time to 0 μs.

In addition, the vertical synchronization signal interval (1v) of 1 field (31) in Fig. 3A and B is 313.0H11 field (31a).
1v is 312.5H, (i +1) 7 yield (
32) is 312, OH, (i+l)' field (3
2a) is 312.58 (i + 2) 7 eel)' (33H! 313.0 heart.

In Figure 1, field memo from the flicker reduction circuit (29)! VCLII supplied to J (26)
Q is a write control signal, VCLII is a read control signal, and since the read speed is twice the write speed, field memo! Output terminal (26b) of the two ports of J (26)
) outputs digital luminance data 2Y that is twice as much as the output terminal (26a). This luminance data is converted into an analog signal by a digital-to-analog conversion circuit (30) and supplied to an RGB conversion circuit and the like.

Although digital luminance data processing has been explained in FIG. 1, FIG. 4 shows the configuration of a PAL digital television receiver. Note that parts corresponding to those in FIG. 1 are designated by the same reference numerals and redundant explanation will be omitted.

A PAL/SECAM composite video signal is input to the input terminal (35) and supplied to the analog Y/C separation circuit (36) and the sync separation circuit (41).

The analog Y/C separation circuit (36) separates the luminance signal Y and color difference signals R-Y and B-Y, and the luminance signal Y is supplied to the analog-digital conversion circuit (21) and converted into a digital signal. The signal is outputted to the digital-to-analog conversion circuit (30) through a system similar to that shown in FIG. 1, and a 2Y analog luminance signal is supplied to the RGB conversion circuit (40). This digital luminance data processing path has exactly the same configuration as in FIG. 1, except for the 4-bit memo IJ (26Y) and (26Y').

The color difference signals R-Y and B-Y separated by the analog Y/C separation circuit (36) are sent to R via the analog switch (37).
-Y, B-Y, R-Y, B-Y, which are converted into serial color difference data, are digitized by an analog-to-digital conversion circuit (38), and are digitized by a color difference noise reduction circuit (38).
9) to the memories (26c) and (26c'). The memories (26c) and (26c') have a 4-bit configuration and store 8-bit serial data in parallel in 4-bit units. Memo! J (26c), (26c
') The output is inputted to the flicker reduction circuit (29) in 8 bits and outputted as double color difference signals 2R-Y and 2B-Y. For this purpose, the read control signal V
CLII+ is a write control signal V. L. 2
It is read out twice.

In the synchronization separation circuit (41), the vertical synchronization signal V sy n
and horizontal synchronization signal Hs y n , and Hs y
n is supplied to the horizontal AFC circuit (42) and the reference
For example, a 28 MHz clock CLK is generated and supplied to the flicker reduction circuit (29), and the memory (29) is also supplied to the flicker reduction circuit (29).
6Y), (26Y').

(26c), (26c'), the flicker reduction circuit (29) is supplied to the analog Y/C separation circuit (36), the analog switch (37), and the analog-to-digital conversion circuit (30). 3
8), (21) Noise reduction circuit (22), (
39) It controls the deflection circuit (43).

If the memory is operated at the same timing as when the flicker reduction circuit (29) is used alone in the configuration shown in FIGS. 1 and 4 above, the write data will be delayed by the amount that it passes through the noise reduction circuit. There is a noise reduction circuit (22) at the left end of the screen displayed on the CRT.
(39) Generate blanking for the amount of delay.

In order to solve this problem, the write control signal can be delayed by the amount of delay of the noise reduction circuit compared to when a flicker reduction circuit is used alone.

This configuration is shown in FIG.

In FIG. 5, for the sake of simplicity, a case will be described in which digital luminance data similar to that in FIG. 1 is obtained. Note that the motion detection circuit (28) is not provided for simplicity. In FIG. 5, the write control signal VCLI is output from the power reduction circuit (29). A delay circuit (44) that delays the noise reduction circuit (22) by the delay amount of the noise reduction circuit (22) is incorporated into the noise reduction circuit of the IC configuration, and through this delay circuit (44), noise is sent to the field memory (26) by the write control signal of VCLIL, O. Reduction Ifil-
f'' - This field memory (26) into which data for evening and full reduction is written is a FIFO
The read control signal VeL12 of the field memo IJ (26) used for performing addition in the noise reduction circuit (22) is the write control signal V. The same reading speed as LIIG is sufficient, and the first output terminal (26a) of the field memo IJ (26)
The addition operation is performed through.

On the other hand, when used as the frame memory (26) of the flicker reduction circuit (29), the write control signal VCLI is used. A read control signal VCL□ is output from the flicker reduction circuit (29) so as to read at twice the read speed of the field memory (
A 2Y luminance signal is obtained at the second output terminal (26b) of 26).

In this way, the delay circuit (44) is replaced by the noise reduction circuit (
22), and the write control signal is delayed by the amount of delay by the noise reduction circuit (22).
By using IO, it is possible to prevent a blanking section from occurring at the left end of the screen.

Furthermore, in the case of a PAL system using field memory in the noise reduction circuit (22), the vertical synchronization signal interval is 313H → 312H → 313H →
312H... is configured to repeat alternately, which causes a problem that the addition positions are sequentially shifted. Therefore, in this example, the write control signal VCLII is changed as shown in FIG.
O or V. By configuring the vertical clear pulse (31) of Lllll)' as 313H→312H→313H-312H, etc., the deviation of the comparison position signal can be automatically corrected. According to the recording device for video signal processing of the present invention, not only can expensive digital field memory be used in common, but there is no need to perform A/D and D/A conversion many times within the digital video signal processing circuit. , the circuit can be simplified and costs can be significantly reduced.

It goes without saying that the present invention is not limited to the embodiments described above, and that various changes can be made without departing from the gist of the present invention.

〔Effect of the invention〕

According to the video signal processing device of the present invention, the storage means can be used in common, the entire system can be simplified, and costs can be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing the basic configuration of the video signal processing device of the present invention, Fig. 2 is a three-dimensional model diagram of a PAL image and scanning line, and Fig. 3 is a diagram of a flicker reduction circuit image and scanning line. A three-dimensional model diagram, FIG. 4 is a system diagram showing an embodiment of the video signal processing device of the present invention, FIG. 5 is a system diagram showing a field memory writing method, FIG. 6 is a waveform diagram of a write control signal, and FIG. Figure 7 is a system diagram of a conventional 10TV. (21), (3g) are A/D converters, (22),
(39) is a noise reduction circuit, (26>,
(26Y), (26Y'), (26c). (26c') is a field memory, and (29) is a flicker reduction circuit. Procedural amendment Written by the Commissioner of the Japan Patent Office Yoshi 1) Moon Kokudo 1, Indication of the case 1988 Patent Application No. 233255 2, Name of the invention Video signal processing device 3, Person making the amendment Relationship to the case Patent applicant address No. 6-7-35, Kitashinyo, Tokyo Parts Ward Name (2
18) Sony Corporation Representative Director Norio Ohga 4, Representative 6 Number of inventions increased by amendment (]) Specification, middle, page 3, line 5, “processed by” is corrected to “processed by” do. (2) Same, page 4, line 1, ``Clad'' is corrected to ``Clock.'' (3) Same, page 7, lines 4 and 5, page 8, line 1, ``frame memory'' is corrected to ``field memory.'' (4) Same, page 10, line 4 says ``10μs''' 10
Correct to n+s J. (5) Same, page 12, lines 9-10, "It is read out at twice the speed." replaces "it must be supplied at twice the speed."
Correct. (6) Same, page 14, line 2, "flicker reduction" is corrected to "flicker reduction". (7) On the same page, in lines 11 and 12, "frame memory" is corrected to "field memory." (8) Same, page 15, lines 5-7 “The vertical synchronization signal interval is...
...is configured," should be corrected to "Since the vertical synchronization signal interval is 312.58, the write or read control signal VCLRO or ■.If Lllll is constant 312H or constant 313H." Figure 3 is corrected as shown in the attached sheet. Above correction diagram

Claims (1)

[Claims] In a video signal processing device having a storage means for converting an analog video signal into a digital video signal and performing video signal processing, a noise reduction means for removing noise from the storage means using the correlation of fields of the video signal. A video signal processing device characterized in that it also serves as flicker reduction means for doubling the field frequency and reducing surface flicker.