JPS6019366A - Horizontal profile circuit - Google Patents

Abstract

PURPOSE:To reduce the number of memories used and dot disturbance by separating a horizontal profile component through a band pass filter after a chrominance signal component is eliminated from a digital video signal converted into the sequential scanning system by means of a comb line filter. CONSTITUTION:A horizontal profile signal 509 is formed by four THS delay circuits 126 and a horizontal profile 502. This circuit is considered to be a cascade connection of a vertical LPF701 of comb line filter constitution and a BPF709. Although it is considered that a Y signal itself is passed through a BPF having a pass band of nearly 4MHz in order to obtain a horizontal profile signal normally, dot disturbance is caused at a signal having a large color change by applying a horizontal profile correction. Thus, the horizontal/vertical profile signal is separated by combining the BPF709 to extract the horizontal profile signal and the vertical LPF701 to suppress the leak in the C signal. The horizontal profile signal 717 is multiplied with a horizontal profile control signal 505 at a multiplier 712, and after the gain is adjusted, the signal is outputted newly as a horizontal profile signal 509.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention converts a baseband analog video signal into a digital signal, converts it from a 2:1 interlaced scanning system to an 1114th scanning system, and displays it as a progressive scanning system signal. The present invention relates to a signal processing circuit for a scanning digital television receiver, and particularly to a horizontal contour circuit. [Technical background of the invention and its problems] The standard television system uses the ID, 2:1 interlaced scanning system, but due to defects such as interline flicker, the displayed images are extremely difficult to view. Ta. In order to improve these shortcomings, a method has been considered in which the video signal is temporarily stored in memory and then converted from interlaced scanning to progressive scanning; A progressive scanning signal was obtained. Therefore, there are disadvantages in that the circuit scale becomes too large and the cost increases accordingly. Particularly in the case of home-use television receivers, high cost is the biggest obstacle to practical application, and a low-cost progressive scanning digital television receiver has been desired. On the other hand, when considering a digital horizontal contour circuit applied to such a digital television receiver, it is necessary to separate the horizontal contour signal component from the luminance signal of the next standard video that has been converted to the single-track scanning method as in the past. However, if a new method of adding to the luminance signal is adopted, the horizontal contour signal separated from the #Ling number often contains chromaticity signal components, so horizontal contour correction is performed using such a contour signal. When doing this, there was a problem in that the dot interference that occurred in the 19 guns with large color electrification was emphasized. [Object of the Invention] The object of the present invention is to improve the drawback of the conventional method that the number of memories used is large, to perform signal conversion to a sequential scanning method using a composite color video signal as an input signal, and to An object of the present invention is to provide a horizontal contour circuit with reduced dot interference, which is applied to a digital television receiver. [Summary of the Invention] The present invention removes the chromaticity signal component from a digital video signal converted to a progressive scanning method using a comb filter, and then separates the horizontal contour component through a bandpass filter. It was designed to obtain Here, the frequency of the comb filter is f = nfHs
(f tls is the horizontal frequency converted to I: iti order 7 scan method, n is an integer), the gain is 1, f-(n±2-
) f■ (has a frequency characteristic such that the gain is 0 at B. [Embodiment of the invention] Figure 1 shows how a baseband analog video signal is converted into a digital signal and sequentially scanned using memory. This shows an overall block diagram of an image processing circuit 100 that converts the digital No. 18 processing to 1'j fz and demodulates the RGB signal.In the following figure, the signal line indicated by the f+++ arrow is the analog No. 18 or A line of a 1-bit digital signal is indicated by a thick arrow (line No. 2 represents a line of a digital signal axed by multiple bits. Below, using FIG. 1, the image processing circuit 100
The outline will be explained, and then the main parts will be explained in more detail. Analog video signal 1 input to image processing circuit 100
01 is a low-pass filter (
(hereinafter referred to as LPF) 103. LPF103 is
Al1) During sampling performed by the converter (hereinafter referred to as ADC) 109, it serves to remove high-frequency noise that causes aliasing distortion. The output of the LPF 013 is input to the adder 105 via the buffer 104 and added to the Clam Buoy No. 4 1 () 6, and then input to the ADC 109 via the amplifier 108. The AI) C 109 samples and digitizes the input signal. In addition, the amplifier 108
In order to effectively utilize the dynamic range of the ADC 109, the output signal 107 of the adder 105 is amplitude-adjusted and output to AI)C1j)9. Here 1. AI) C109 → Clamp circuit 112 → B
/A converter (hereinafter referred to as 1) AC) 114 → adder 105 → amplifier 108 → AT) A control loop is formed by C109, which controls the pedestal level of the digital video signal 110 output from the ADC 109 to a predetermined target value. Control is in place to ensure this. In this control loop, the output of the ADC 109 (i4 110) and the burst J+q repulse 111 from the lυ1 minute-t timing generation circuit 122, which will be described later, are input to the clamp circuit 112. First, the average value (pedestal level) of the burst portion of the digital video signal 110 is computed.Next, the difference between the computed pedestal level and the target A10 is computed and output as an error signal 113. Error No. 41 113 fl;, t, I) AC11
After being exchanged for analog 227146 No. 106 in 4,
As described in mfJ, the adder 105 adds 5° to the output signal of the buffer 104. As a result, the video signal 107 output from the adder 105 is converted into a DC signal, and the pedestal level of this signal 107 is controlled to approach the target value. It is done. And this signal

07 is an amplifier 108 for amplitude adjustment
, ADC 109 is converted into digital video signal 110 by
After being converted into , it enters the crank circuit 112 again and an error signal 113 is calculated. Pedestal clamping is performed by the above operation. On the other hand, sampling in the ADC 109 is performed using a voltage controlled crystal oscillator (hereinafter referred to as vcxo) and a counter.
This is performed at the timing of the sampling pulse 116 (φS) output from the clock generation circuit 115 that is generated. In this example, the vCXO has an oscillation frequency of 8
jsc = 3.58M1 (z
). Therefore, the sampling pulse 116 (φ
8) frequency fs is the output signal (φck) of vcxo9
The frequency divided by 2 output of 0 is used, and fs is set to 4fsc. In the NTSC signal, the hue component of the color signal is phase-modulated by the color subcarrier, so the relative phase between the sampling pulse 116 (φS) and the color burst is the color 451.
Determine the demodulation axis when the signal is modulated, and determine the hue. This point, sampling pulse, <1.16 (φS
) must be locked to the phase of the color burst. This control is performed by the ADC1091 phase detection circuit 118-+I]AC12(1-+crop.The control procedure is as follows.First, the digital video signal 110 and bar, ()t&
A scraped pulse 111 is input to a phase detection circuit 118 . This phase detection circuit 118 detects the burst extraction pulse 1.
11, a color burst portion of the digital video (17110) is extracted, and the actual sample phase (θ) in this color burst portion and the phase target value 117I0
0) is calculated, and the phase error signal 11
Output as 9. However, in reality, the phase difference signal 11
9 is proportional to IIIn(θ-00). The phase error signal 119 is converted into an analog signal by I) AC 120, and as the vcxo control voltage 121, the vcxo
is applied to As a result, the phase of the sampling pulse 116 (φ3) which is the output of the vcxo is changed to the phase target value 1
17 (θ0). Note that hue control is performed by changing the phase target value 117 (θ0). Sampling pulse 116 (
φS) is supplied to each block together with the vcxo output signal 90 (φck) as an operating reference for the digital circuit section in the image processing circuit 100. The synchronization separation/timing generation circuit 122 receives the tagged video signal 110 as input and outputs a burst extraction pulse and an NTSC horizontal/vertical synchronization signal 123 through a predetermined operation.ノ(-Streak extraction pulse 111
The above-mentioned clamp circuit 112 and phase detection circuit 11
8, and NTSC horizontal and vertical synchronization signals 12
3 is input to the countdown circuit 124. In the countdown circuit 124, the sampling pulse 116 (φ
8), a horizontal/vertical synchronizing pulse 125 converted to a progressive scanning method is generated. The horizontal/vertical synchronization clock 125 operates the CRT via a synchronization drive circuit (not shown). Digital video signal 110 has its sample phase, pedestal level, and amplitude adjusted as described above and is input to progressive scan conversion circuit 99. The progressive scan conversion circuit 99 converts the interlaced scanning digital video signal 110 into the llffft sequential scanning digital video signal 98. The progressive scan conversion circuit 99 receives horizontal timing signals 95 to 97 for interlaced scanning and progressive scanning output from the countdown circuit 124 and color demodulation control pulses 140 for interlaced scanning from the phase detection circuit 118 for memory control. It is input via circuit 92. The memory control circuit 92 uses these numbers 16 to create the necessary timing for the progressive scanning method, and also generates a pulse 94 for extracting the burst portion from the digital video signal 98 converted to the progressive scanning method. (Details of the 11nth scan conversion [['' path 99 will be described later.) Digital video signal 98 expressed in a progressive scanning system.
is input to the RGB tone/image quality control system described below. The digital video signal 98 is 4T, (8 delay circuits 12
6, OT[s, ITHs + 2THs,
3THs, 4TIIs (THs is one horizontal time converted to progressive scanning) delayed signal 127
is output. This delayed signal 127 is required for each calculation using the diine correlation that will be described below. In addition, here, IT
The number of bits in Hs is calculated to be 910 bits taking into consideration the NTSC system, and the clock frequency at this time is 8fsc. The delayed signal 127 is input to a luminance signal/chromaticity signal separation circuit (hereinafter abbreviated as Y/Cfk t'i[f1 circuit) 128 and a Y signal processing circuit 129. Y/C separation circuit 128 has 0TIIs, 1'i"H
s, 2THs, 3THs. Using a @-type filter realized by calculation using a delayed signal 127 of 4THs, and a band-pass filter (hereinafter abbreviated as BPF) whose gain is 1 at f=2fs,
Chromaticity signal (hereinafter abbreviated as C signal) 1 from delayed signal 127
30, and further subtracts the C signal 130 from the 2THs delayed signal of the delayed signal 127 to obtain a luminance signal (hereinafter referred to as
Y signal) 131 is separated. The Y signal processing circuit 129 processes the delayed signal 127 and the Y signal 1.
31 and an external image quality control signal 132 are input, and after each correction of horizontal contour, vertical contour, contrast, and brightness is applied to the Y signal 131, a new Y signal 133 is input.
As U'' Ka (swallow for details). The C signal 130 is input to a color control/color killer circuit 135. The color control/color killer circuit 135 detects the burst amplitude of the C signal 130, and performs color control and color killer operations based on this. Color signal 2 obtained with this color control meeting color killer circuit 135 - Hakugo 137
is input to the Y/c division circuit 128, and when the Cassie Killer 'jI111 is activated, it also controls the video No. 18 to be output as the itY signal 131 in order to widen the band of the Y signal 131. In the color control color killer circuit 135, the amplitude (color saturation) of the C signal 130 is also adjusted by a color control signal 136 from the outside. Six outputs 138 of the color control/color killer circuit 135 enter a color demodulation circuit 139 and are synchronously demodulated. Demodulated C signal 141 obtained by color demodulation circuit 139
become I and Q signals. The Y-signal 133 and the demodulated C signal 141 are input to a matrix circuit 142, multiplied by a predetermined demodulation coefficient, and then added and converted into an RGB signal 143. This RGB signal 143 is converted into an analog signal by a DAC 144, and this signal 145 is input to the CRT via an RGB output circuit (not shown). Next, details of the progressive scan conversion circuit 99 will be explained. The progressive scan conversion circuit 99 shown in FIG. 1 receives H8ynKI from the φ countdown circuit 124, a signal HI96 with an fh period obtained by one period, a 1/2 fh signal He 95 obtained by dividing the frequency of the above 96 by 2, and an H11 signal 96. From 1/2 TJ-
According to the control signal of the memory control circuit to which the delayed signal f (s 97 is input) and the signals 116 (φ8) and 90 (φck) from the clock generation circuit 115, the interlaced scanning digital video that is the output of the ADC 109 is generated. The signal 110i is converted into a progressive scanning digital video signal 98. In this embodiment, 2
An example using two line memories and one field memory will be described. (Field memory is 26311
t also has a storage capacity). First, the timing signal HI*HcrHs96,'
95. 97, the time relationship is shown in FIG. In Figure 3, (a) is the input video signal 1.10 s (b) is I
b signal 96, (c) shows Hc signal 95, and (d) shows H33 signal 97. A method of converting to the IIN scan method using the above timing will be described with reference to FIG. The digital video signal 110 being led to the first and second line memories undergoes time-base compression in these two memories. The first and second line memories each have memory control circuits 1j5 and 16-R/W.
A control signal 19 and Atto 1/Sume 2o are supplied. The memory control circuit 15°16 receives the φB information signal 16.
, or using the φck signal 9o as a clock signal, the HI
A line memory address is generated by using the signal 96 or H, (S signal 97) as an address load signal.
5 and is controlled and selected. The Ftr signal 96 and the φ88 motor 116 are applied to the first line memory control circuit 15.
When in the write state, the second line memory control circuit 16 is supplied with H88, 97 and φ. k
A signal 90 is supplied and the read state is established. In the next T period, control is provided by the Hc- signal 95 so that both signals alternate. Further, the R/W control of the line memories 1.0 and 110 is such that the R/W is switched every T old in synchronization with the address controlled according to the Hc signal 95. The digital video signals 31 and 32 thus time-base compressed are led to the field memory 13 and the signal switch 4 through a signal switch controlled by the Ic signal 95. The R/W control and address signals from the field memory control circuit 17 are input to the field memory 13 . The field memory control circuit 17 has φ
. According to the Hr signal 96 and Hs signal 97 from the KA number 90 and the countdown circuit 124 (see FIG. 1), an address signal and an R/W control signal are generated and supplied to the field memory 13.Field memory 13 H.
The r signal 96 reads the signal, and the HI signal 97 writes the output 33 from the signal switch 12 to the same address that was read 1/2 THI ago. Further, the field memory 13 performs address clearing every 263'1''. The signal 34 read out in this way is % (
It is led to the i4 switch 14. 1 for the signal switch 14
．． 1lr (C No. (j and I (8@ No. 97)
In the first half period of υth 11, field memory 13
In the 1/2 period, the signal 33 from the line memory is passed through 3 m. In this way, the digital signal 11 according to the interlaced scanning method is
0 is sequentially converted into a dark blue digital signal 98. The above time relationship is schematically shown in FIG. In FIG. 4, (a) is a signal based on the interlaced scanning method (corresponding to the video signal 110), (b) is writing in the pll line memory 10-1, and (e) is writing in the second line memory 1.
(d) corresponds to the video signal 31 read out from the first line memory 10), (e) corresponds to the video signal 32 read out from the second line memory 11. ), (f) corresponds to the video signal 34 read out from the field memory 18)% (g) 1 input to the field memory 13, (h) corresponds to the output signal 98 of the signal switcher [4, respectively. It shows the time relationship of B. It's a size (i)
) indicates an address block in TH8 units in the field memory 13. Next, details of the Y signal processing circuit 129 will be explained. Y signal processing circuit 129 i, horizontal contour, vertical contour, contrast,
Each brightness correction is performed and output to the matrix circuit 142. FIG. 5 shows a specific configuration example of the Y signal processing circuit 129. The Y signal processing circuit 129 includes a vertical contour circuit 501, a horizontal contour circuit 502, a contrast circuit 503, and an L circuit 5.
11, a pedestal clamp circuit 513. ``The image quality control signal 132 still includes a vertical contour control signal 504, a horizontal contour control signal 505,
It includes a contrast control signal 506 and a brightness control signal 507. 4 Tkl, delay signal 1 output from delay circuit 126
27 is each vertical 1K, horizontal contour and contrast circuit 5
01.502, 503, vertical and horizontal contour signals and contrast 1. :V No. 508, 509,
510 is output. The gains of these signals are adjusted by respective control signals 504, 505, 506. In the filter 511, vertical/horizontal contour and contrast signals 508, 509, 510 and Y signal 13 are processed.
1 and the bright control signal 507 from the addition section are added. The bright control converts the DC component of the Y signal 131 into ijl by the bright control signal 507.
,',j, and this fz is performed by an adder 511 and a pedestal clamp circuit 513. Y signal 13
1&, Vertical 11, horizontal contour, contrast mentioned above,
After each brightness correction is applied, the signal is output as a new Y signal 133 and enters the matrix circuit 142. below,
The horizontal contour circuit within the YIFi processing circuit 129 will be explained in detail. The creation of the horizontal contour circuit 502 is not shown in FIG. The horizontal contour signal 509 is generated by the 4TI (8 delay circuit 126) and the horizontal contour circuit 502. This circuit i-, i:, <t,
Type filter configuration vertical 1,000 F701 and In), [” 7
09 can be considered to be connected in cascade. Vertical], the PF 701 is connected to the 4TH8 delay circuit 126! It is composed of eaves 702 to 706 and an adder 707. The vertical frequency characteristic HvLpF surface of vertical LPF 701 is
HvLpNP'l=a (i + 2CD8 < 2π
fvF/fHs) +(O8(4πfvF/fH
B)・・・・・・・・・・・・ It is given by (1). The characteristic given by equation (1) is constant in the horizontal frequency direction and changes only in the vertical frequency direction, and this change is such that when F = 0, the gain = 1, and then the gain decreases and F
= 0.25 x fHs / fv and the gain = 0. The output cuff 08 of the vertical LPF 701 is input to the BPF 709 . BPF 709 is 4Tck delay circuit 710
．． 711 and coefficient multipliers 713 to 715, and has characteristics of a center frequency fs/4 (3.6 MHz) and a normal band ±fs/s (1.8 MHz). This extracts the horizontal contour signal of a picture around 4 MHz. Normally, when obtaining a horizontal contour signal, the Y signal itself is
It is conceivable to pass the signal through a BPF with a passband around 4F4Hz, but the vertical frequency band of the Y signal is also relatively wide, and the C signal often leaks into the horizontal contour signal. Therefore, by applying horizontal contour correction, dot interference occurs in areas where the color change is large. Therefore, in this embodiment, BPF 7 (+9) and C (
, No. ii leakage suppressed, vertical LPF 70
1 are combined and the water drop contour signals are separated. This horizontal contour signal 717 is multiplied by the horizontal contour control signal 505 in a multiplier 712, gain adjusted, and then output as a new horizontal contour circuit 509. In the above embodiment, a vertical LPF with a comb-shaped configuration using 4TI (8 delay circuits) was used, but a vertical LPF' with a comb-shaped configuration using 2TH8 delay circuits may also be used. In this case, If the signal output from the delay circuit is set as shi0.shi1.shi2 in descending order of delay amount, then it is sufficient to perform the calculation +Σshio+0.shi1+Σν1 on each of them and output them. The characteristics of the comb filter are HvLpF (Fl=-(2πf, F'/fH9)
It is expressed as −・−・−・−・・−・+21. [Effects of the Invention] According to the present invention, instead of using demodulated RlG and B signals as in the past, a baseband composite video signal is used as an input signal, converted to a digital signal, and then converted to a progressive scanning method. It has become possible to perform processing, and the size of the circuit has been reduced to one-third of that of conventional circuits, making it possible to miniaturize the circuit. However, as a result, costs have been reduced, and the cost problem, which is a major hindrance to home-use television receivers, has been solved. Further, according to the present invention, it is possible to obtain a horizontal contour signal without leakage of the chromaticity No. 8 component. Therefore, when horizontal contour correction is applied, dot interference is not emphasized in areas where color changes are large, and image quality is improved. Furthermore, the present invention has a circuit configuration that directly separates and extracts the horizontal contour signal from the video signal, rather than from the luminance signal as in the prior art. Further, this circuit configuration can be used in common with the delay amount and path used in the comb filter for removing the chromaticity signal in the Y/C separation circuit 128. Therefore, a horizontal contour signal can be obtained without increasing the circuit scale or increasing the cost.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of the entire image processing circuit of a digital television receiver, Figure 2 is a configuration diagram of the progressive scan conversion circuit, and Figure 3 is a waveform diagram showing a timing chart used to control the progressive scan conversion circuit. , FIG. 4 is a schematic diagram showing an explanatory timing chart of the sequential scanning method, 5v1 is a <rlt diagram of the Y signal processing circuit, and FIG. 6 is a diagram of the horizontal contour circuit. 101...Analog video signal, 108...A/D
Converter, 110...Digital video signal, 98
...11th order scanning digital video signal, 99...
・Progressive scan conversion circuit, 126...Delay circuit, 128・
...Brightness signal/chromaticity signal separation circuit, 130...Chromaticity signal, 131...Brightness signal, 701...Comb filter (
Vertical LPF) 702.703,704,705,706,713,7
14,715...Coefficient 11-unit, 707.716
...Adder, 708...LPF output signal, 709.
... Bandpass filter (BPF) 712 ... Multiplier, 710.711 ... Delay circuit, 717 ... Horizontal contour signal, 505 ... Horizontal contour control signal, 5
09...Final horizontal contour signal. Figure 2 Figure 3 Figure 4 (1) Possible ■■■mouth Field H26161626 Figure 6 Figure 6

Claims (1)

[Claims] Applicable to progressive scan television receivers that digitize a standard composite video signal, then temporarily store it in memory, convert it from a 2:1 interlaced scan format to a progressive scan format, and display it as a progressive scan format signal. In the horizontal contour circuit, there is a delay circuit that takes progressive scanning digital video (i) as input and outputs a signal delayed by one horizontal period converted to the progressive scanning format, and an output from this delay circuit. When the frequency is f =
nfHs (fHs is the horizontal frequency converted to the progressive scanning method, n is an integer), the gain is l, f = (n ± L) fHs
A horizontal filter comprising: a comb-shaped filter having a frequency characteristic with a gain of 0; and a band-pass filter that separates a horizontal contour component from the output signal of the comb-shaped filter and outputs a horizontal contour signal. contour circuit.