JPH0281242A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the processing time by bringing a data storage means to access by a first access means and a second access means, when an addressing mode coincides with an addressing mode determined in advance, and when the former does not coincide with the latter, respectively. CONSTITUTION:At the time of an addressing mode determined in advance, a data storage means 1 is brought to access by using a first access means 2 without calculating an effective address. Also, when other addressing mode than that which is determined in advance is used against data of the same address, a second access means 3 is used. Accordingly, data of a specific memory area such as a stack area, etc., can be referred to by the time being equal to a register, and the consistency to a memory can also be maintained. In such a way, the processing can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device having a mechanism for speeding up data references in a stack area.

In order to speed up the processing of a data processing device operated by a conventional technology program, it is necessary to speed up references to data used by subroutines. One way to achieve this using software is to hold data used by subroutines in registers that can be referenced as quickly as possible. However, there is usually a limit to the number of usable registers, and there is a problem in that registers holding data to be used later must be saved when a subroutine is called. Therefore, one method to implement this using hardware is to store data in the stack area, provide a cache memory that can be accessed at high speed, and hold data used by subroutines in the stack.

An example of a data processing device that has a mechanism for speeding up data references in the conventional stack area is the ``Armpit High Performance 032 Bit'' by T. Nishimkai et al.
"Microprocessor" PRC, iTripleE International/L/@Conference on Computer Science, 336-339
Page, October 1986 (T, NiShiN15h
i and 3 others, ``'A ) (igh Performa
nce 32-bitMicroproctssor
”, Proc, IEEE Izsternati
onalConference on Compute
r Design, pp336-339.0cto
ber 1986).

FIG. 5 is a block diagram of this conventional data processing device.

1 is a data storage means, 4 is an instruction register that stores an instruction word, and 5 is an addressing mode determination unit that decodes the addressing part of the instruction word and generates a control signal 62 necessary for address calculation. 31 is an effective address calculation means, 32 is a second storage position determining means, 33 is a general-purpose register group, e is a replacement control means for controlling data transfer with the main storage device in the event of a cache miss, and 7 is an arithmetic means. be.

In the conventional data processing device configured as described above, the addressing mode determining means 31 decodes the addressing part 44 in the instruction word stored in the instruction register 4, and the control necessary for calculating the effective address is performed. A signal 62 is output. Effective address calculation means 31 calculates an effective address according to control signal 62. For example, if the addressing mode is a so-called register indirect addressing mode with displacement that indicates a relative position from the contents of a specific general-purpose register, the contents of the specified register from the general-purpose register group 33 are read, and the displacement in the instruction word is read. 43 (4 pits.

8 bits, 16 bits or 32 bits). The second storage position determination means 32 determines in which position of the data storage means 1 the data corresponding to the effective address 311 is stored, and if it is stored, reads or writes the data.

When corresponding data is not stored, the replacement control means 6 reads that data from the main memory.

There are various methods of mapping between the effective address 311 and the storage location in the data storage means 1, such as a direct mapping method, a set associative method, and a full associative method, and there are also various ways to implement the mapping method.

Problems to be Solved by the Invention However, in the above configuration, even if a data storage means that can be accessed in the same time as a register is provided, it requires time to calculate the effective address, so it is not possible to have a pipeline processing structure. In a data processing device that does not have a stack area, the processing time for an instruction that directly uses data in the stack area increases, and in a data processing device that has a pipeline processing structure, the number of pipeline stages increases and the processing time for an f branch instruction increases. It had

In view of this, an object of the present invention is to provide a data processing device that can refer to data stored in a specific memory area such as a stack area in the same amount of time as data stored in a register.

Means for Solving the Problems The present invention provides a data storage means, a first access means for directly determining a storage position of the data storage means from a part of the memory address specification part in a command word, and the memory address specification part. and second access means that calculates an effective address based on the addressing mode specified by and determines a storage location of the data storage means based on the effective address.

According to the above-described structure, the present invention uses the first access means to access the data storage means without calculating an effective address when in a predetermined addressing mode, thereby accessing the data storage means in the same time as registers. Data can be referenced. Also, when using an addressing mode other than the predetermined one for data at the same address, the second
Memory integrity can be maintained by using access means.

Embodiment FIG. 1 shows a block diagram of a data processing apparatus in an embodiment of the present invention. In FIG. 1, 1 is a data storage means, 2 is a first access means, 3 is a second access means, 4 is an instruction register, 5 is an addressing mode discrimination means, 6 is a replacement control means, and 7 is an arithmetic means. be.

FIG. 2 is a block diagram showing the configuration of the first access means 2. In FIG. A pointer 22 is a second pointer indicating where in the data storage means 1 the effective address indicated by the frame pointer is mapped; 23 is a first pointer 21 and a second pointer 22;
Short displacement in instruction word (4 bits,
The bit 42 (1 bit) that distinguishes between stack pointer and frame pointer in the instruction word (multiplyed by 4 when calculating the effective address) is used as input to determine the storage location in the data storage device 1 of the data to be referenced. 1 is a storage position determining means.

Further, the second access means 2 has the same structure as the conventional data processing apparatus shown in FIG.

FIG. 3 is a block diagram showing the configuration of the first storage position determining means 23, in which 231 is a selector and 232 is an adder.

In this embodiment, the data memory hand B1. has a capacity of 256 bytes and stores data in 4-byte units using the direct map method, so
The second pointer 22 holds the values of the lower three to eight bits of the stack pointer and frame pointer, respectively.

The operation of the data processing apparatus of this embodiment configured as described above will be described below.

When storing the data used in the subroutine in the stack area, for example, as shown in Iwao Morishita's microcomputer hardware Jpp61-71, the stack pointer and frame pointer are used as pace registers to store the data in the stack area. to access. In this embodiment, the addressing mode most often used when accessing the stack area is frame pointer relative indirect addressing mode with displacement (displacement is from (-8X4) to (+7X4)).
, stack pointer with displacement addressing mode (displacement is from 0 to (
+7X4 )), stack bush, and pop modes, and these addressing modes can cover most of the accesses to the stack area.

Furthermore, when an instruction word using the frame pointer with displacement relative indirect addressing mode is set in the instruction register 4, the first storage position determining means stores the short displacement 41 in the contents of the second pointer 22. Add content. At the same time, the addressing mode determining means 6 determines whether the addressing mode is any of the above-mentioned addressing modes, outputs the first access means valid signal 61, and outputs the first storage position determining means 23. The data storage means 1 is accessed according to the storage location 2o1 to output the data to the calculation means 7. The above operation in this embodiment having a pipeline structure is shown in FIG. 4(a). The stack pointer with displacement relative indirect addressing mode is exactly the same; in the case of a stacked bush, the first pointer 21 is decremented before accessing the data storage means 1, and in the case of a stack pop, it is decremented to the data storage means 1. The first pointer is incremented after the access.

Next, when an instruction word that uses an addressing mode other than the addressing mode mentioned above is set in the instruction register 4, the addressing mode determination means 6 does not output the first access means valid signal 51, as in the conventional data processing device. The second access means 3 outputs a control signal 52 necessary for calculating an effective address, and if the data to be referenced is stored in the data storage means 1, the second access means 3 outputs the control signal 52 necessary for calculating the effective address. is accessed and the data is output to the calculation means 7. The above operation in this example is $4.
Figure 1).

Furthermore, when the stack pointer or frame pointer is changed, the replacement control means 6 determines whether the area to be accessed in the above-mentioned addressing mode is stored in the data storage means 1, and if it is not stored, it is possible to Data transfer with the main memory is performed so that the data in the area accessed in the addressing mode is stored as much as possible. This processing is controlled by a microprogram, and if the stack area used by the subroutine is too large to store all of it, access to the unstored area is performed in the same way as in the past.

As described above, according to this embodiment, in addition to the conventional means of accessing the cache memory, a part of the instruction word that specifies a specific addressing mode is directly used, and the cache memory is accessed without calculating the effective address. By providing means for accessing the memory area, data in a specific memory area such as a stack area can be referenced in the same time as the register, and consistency with the memory can also be maintained.

In the first embodiment, the first access means 2 uses a pointer and an adder, but it can also be implemented using an associative memory. Furthermore, regarding the pipeline structure, it is conceivable that the structure requires two stages for decoding.

As described in detail, according to the present invention, processing can be sped up by holding data used by subroutines in the stack area, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a first access means of the embodiment, and FIG. 3 is a first storage position determining means of the embodiment. FIG. 4 is a pipeline operation diagram of the same embodiment, and FIG. 6 is a block diagram of a conventional data processing device. 1...Data storage means, 2...First access means, 3...Second access means, 4.
...Instruction register, 6...Addressing control means, e...Replacement control means, 7.
...Calculation means. Name of agent Patent attorney Shigetaka Awano and 1 other person 1 Figure 2 Figure 3 Figure Figure Figure (2) F<U seconds (b) Cffi page→

Claims (1)

[Claims] data storage means; first access means for directly determining the storage location of the data storage means from a part of the memory address designation part in the instruction word; and an effective address based on the addressing mode specified by the memory address designation part. and a second access means for calculating the storage location of the data storage means based on the effective address, and when the addressing mode matches a predetermined addressing mode, the first access means A data processing apparatus, characterized in that the data storage means is accessed, and when the data do not match, the data storage means is accessed by the second access means.