JPH0278248A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the operations by a method wherein signal lines are periodically coupled with dummy wirings arranged making right angles with the extensions of the signal lines, etc., at the specified intervals. CONSTITUTION:A non-inversion clock-signal line CP 1 and an inversion clock signal line -CP 1 are parallel arranged at the intervals in unit length of (l). The signal lines CP 1 and -CP 1 are respectively coupled with dummy wirings d1-d3 and d4-d6 by a high-speed computer. The dummy wirings in length of 2l are arranged making right angles with the prolonged lines of the clock lines. The values of L and 2l are specified so that any crosstalk noise may be abated even if the general signal wirings are parallel arranged with the clock signal lines. The general signal lines Sa, Sb are arranged close to the complementary clock signal lines. Respective signal lines shall be connected linearly without traversing any other lines at the minimum distance between two connecting points. Through these procedures, the crosstalk noise can be abated while the operations of the high speed computer, etc., can be stabilized, thereby enabling the cycle time to be accelerated equivalently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, for example, DA (Design Autosat) for layout design regarding signal wiring of high-speed logic integrated circuits such as high-speed computers.
ion: Design automation).

[Conventional technology]

There are high-speed computers constructed from high-speed logic integrated circuits. Furthermore, there is a DA technology used for layout design of signal wiring, etc. of such high-speed computers.

High-speed computers are described, for example, in Nikkei Electronics J, June 2, 1986, pages 179 to 209, published by Nikkei McGraw-Hill.

[Problem to be solved by the invention]

FIG. 3 shows an example of a partial layout of a high speed computer as described above.

In FIG. 3, a high-speed computer has complementary clock signal lines CPI and CP arranged linearly over a relatively long distance.
1, and general signal lines Se and sr placed close to this complementary clock signal line. In this high-speed computer, the layout design for the complementary clock signal lines CPI, CPl, etc. is done manually in order to minimize the delay time and skew of the clock signal, but the signal lines Se and Layout design regarding general signal wiring such as Sf is automatically performed by DA technology using a grid method. As a result, waste of time and space in layout design is eliminated, and design costs for high-speed computers and the like are reduced.

However, the inventors of the present application have discovered that the above technique A has the following problems.

That is, in the above DA technology, the signal lines Se and sr
General signal wiring, such as, is arranged so as to provide the shortest distance between two points to be connected. Therefore, as shown in FIG. 3, when these signal wirings are placed in parallel to the complementary clock signal line CPI-CP1 etc. placed in advance to the extent that it causes a problem and over a relatively long distance. occurs. As is well known, parasitic capacitances such as csl and cs2 exist between these clock signal lines and signal wirings, and their capacitance values change as high-speed computers become more highly integrated and the width and spacing of signal lines become finer. increases according to

As a result, crosstalk noise between the complementary clock signal line and each signal line increases, which may lead to malfunction of the circuit. This equivalently limits the cycle time of high-speed computers and contributes to lowering their processing power.

An object of the present invention is to provide a DA technology that reduces crosstalk noise. Another object of the present invention is to stabilize the operation of a high-speed computer using DA technology and to speed up its cycle time.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in high-speed computers, etc., where the layout design is automatically performed using DA technology, crosstalk noise becomes a problem, so the lock signal line, etc., is arranged substantially perpendicular to its extension direction. Dummy wiring of a predetermined length is periodically coupled at predetermined intervals.

[For production]

According to the above-mentioned means, the distance between the clock signal line, etc. and other general signal wiring, which is long enough to cause problems, and arranged parallel to each other, is maintained at the predetermined length or more, and the clock signal line, etc. It is possible to limit the section in which the wiring is arranged so close to and parallel to other general signal wiring that it becomes a problem to be within the predetermined interval. This reduces parasitic capacitance between clock signal lines or between clock signal lines and general signal wiring, and reduces crosstalk noise, thereby stabilizing the operation of high-speed computers and equivalently The cycle time can be increased.

(Embodiment 1) Fig. 1 shows a partial layout diagram of an embodiment of a high-speed computer to which the present invention is applied.
(Embitter Coupled Log-i
c) It is constituted by a plurality of high-speed logic integrated circuits whose basic configuration is a circuit, and is operated synchronously in accordance with complementary clock signals of a plurality of phases. FIG. 1 exemplarily shows the layout of complementary clock signal lines CPI-CPI and their peripheral parts among the plurality of phases of complementary clock signals.

The high-speed computer of this embodiment has a general layout design for signal wiring that uses a grid method.
This is done automatically using A technology.

In other words, the general signal wiring of this high-speed computer is arranged along countless grids on a semiconductor substrate with a predetermined unit length l, as shown in the upper right corner of Fig. 1. be done. In this embodiment, the semiconductor substrate on which the high-speed computer is formed has two wiring layers consisting of a first and second aluminum layer, and the grid is assumed to be in each of the first and second aluminum layers. be done. The arrangement interval of these grids, that is, the unit length l, is determined based on the miniaturization technology, and is, for example, 5μ.
(microns). For each signal wiring, the positional coordinates of the two grids to be connected are given, so that its placement route, wiring layer, etc. are automatically determined. On the other hand, in this embodiment, the layout design regarding complementary clock signal lines, etc. is not particularly limited, but is performed manually due to the need to minimize the delay time and skew, and is a general layout design for signal wiring. The layout is fixed prior to.

Note that, in the following figures, signal wiring arranged in the first aluminum layer is shown by a solid line, and signal wiring arranged in the second aluminum layer is shown by a dotted line. Also,@
A contact for bonding the first and second aluminum layers is indicated by an X mark, and a grid located at the tip of a dummy interconnect, which will be described later, is indicated by a 0 mark.

In FIG. 1, the first phase non-inverted clock signal line CPI
Although not particularly limited, the inverted clock signal line CPI and the inverted clock signal line CPI are arranged in parallel with an interval of the above unit length i. As described above, the layout design for these clock signal lines is performed manually, and the layout is fixed prior to the general signal wiring layout design.

In the high-speed computer of this embodiment, the non-inverted clock signal line cpi and the inverted clock signal line CPl include, but are not limited to, dummy wiring lines d1 to d3 and d4 to d4, which are periodically arranged at predetermined intervals. d6 are respectively combined. These dummy wirings are arranged perpendicularly to the extending direction of the corresponding clock signal line, and their length is not particularly limited, but is twice the unit length β, that is, 21. Here, the interval at which the dummy wiring is coupled to the corresponding clock signal line and its length 21
is set to a predetermined value such that crosstalk noise will not be a problem even if a general signal wiring is arranged parallel to a clock signal line.

The high-speed computer further includes general signal lines Sa and sb arranged relatively close to the complementary clock signal lines CPI and CPI, of which the signal line Sa is connected to the complementary clock signal lines CPI and CPI. The signal line sb is arranged from one coupling point located at the top toward the other coupling point located below, and the signal line sb is arranged in parallel with the complementary clock signal line CPI-CPI in the section shown. As described above, the layout design for these general signal wirings is automatically performed by the DA technology using the grid method. At this time, each signal line is
They are arranged so as to connect two points to be connected in the shortest possible distance and in a straight line without crossing other signal lines as much as possible.

As a result, the signal line Sa, for example, connects the section sandwiched by the dummy wirings di and d2 to the non-inverted clock signal line C.
After being placed in parallel with PI, it intersects with the complementary clock signal lines CPI and CPI through the second aluminum layer, and is further placed to the lower coupling point through the first aluminum layer. - On the other hand, the signal line sb is the dummy wiring d1 to d3.
Along the upper grid of the grid located at the tip of
In other words, it is arranged parallel to the non-inverted clock signal line CP1 at a distance of three times the unit length l, that is, 31. Therefore, the section in which the signal line Sa and the complementary clock signal lines CP1 and CPI are arranged close enough to each other and in parallel to cause a problem is limited to within the predetermined interval, and the signal line sb and the complementary clock signal lines CP1 and CPI are arranged in parallel. The distance between parallel sections that are long enough to cause problems with CPI is:
The unit length is limited to three times the unit length 2, that is, 31 or more.

For these reasons, in the high-speed combinator of this embodiment, the parasitic capacitance between the complementary clock signal line and the general signal wiring is reduced, and the crosstalk noise between these signal wirings is reduced. Therefore, the operation of the high-speed combinator is stabilized, and its cycle time is equivalently increased.

As described above, in the high-speed computer of this embodiment, layout design regarding general signal wiring is automatically performed by DA technology using the grid method. Two aluminum wiring layers are provided on the semiconductor substrate, and the grid is assumed to be in the form of a lattice, with each of these aluminum layers having a unit length l. In this embodiment, the layout design regarding the clock signal lines is performed manually to minimize the delay time and skew of the clock signal, and the layout is fixed prior to general signal wiring. D1-wirings having a length of 2i and arranged perpendicularly to the direction in which the clock signal line extends are periodically coupled to the clock signal line at predetermined intervals. Therefore, in general signal wiring placed close to these clock signal lines, the section that is placed close enough to the clock signal line and parallel to the clock signal line is limited to within the above-mentioned predetermined interval, and The distance at which a problematically long section is arranged in parallel with the clock signal line is limited to three times the unit length E, that is, 3 g or more. Therefore, in the KM computer of this embodiment, the parasitic capacitance between the clock signal line and the general signal wiring is reduced, and crosstalk noise between these signal wirings is reduced. As a result, the operation of the high-speed computer is stabilized, and its cycle time is equivalently speeded up.

[Embodiment 2] FIG. 2 shows a partial layout diagram of another embodiment of a high-speed computer to which the present invention is applied. This embodiment basically follows the first embodiment described above. Therefore, in the following explanation regarding this embodiment, only the parts that are different from the first embodiment will be added.

In the high-speed computer of this embodiment, the layout design of each signal wiring including the clock signal line is automatically performed by the DA technology using the grid method described above. In this embodiment, the semiconductor substrate is provided with two aluminum wiring layers, and each grid is assumed to have a lattice shape with each aluminum layer having the unit length β as in the first embodiment. .

In FIG. 2, a high-speed computer is equipped with complementary clock signals cp1-CPI and CF2, which should be arranged linearly over a relatively long period in the horizontal direction of the figure, although this is not particularly limited.
-Includes CF2. These clock signal lines are designed in a layout that takes precedence over other general signal wiring.
Four pairs of connection points are specified to be arranged at a distance of unit length l. In this embodiment, connection points are added to the non-inverted clock signal line CPI to which dummy wirings d7 to d12 arranged perpendicularly to the direction of extension thereof are connected, although this is not particularly limited, and the inverted clock signal line CPI
A connection point is added to I so that dummy wirings d13 to di5 arranged at positions point-symmetrical with respect to the dummy wirings d8, dlO and d12 are connected. Similarly, connection points are added to the inverted clock signal line CP2 to which dummy wirings d19 to d24 arranged perpendicularly to the extension direction thereof are connected, although this is not particularly limited.
The dummy wiring d1 is connected to the non-inverted clock signal line CP2.
9. A connection point is added to connect the dummy wirings d16 to dlB, which are arranged at positions symmetrical with respect to d21 and d23, respectively. Here, dummy wiring d
7. d9 and dll and d20. d22 and d24
is set to have a length twice the unit length l, that is, 2β, and all other dummy wires have a unit length i.

Furthermore, the average spacing of the dummy wires provided corresponding to each clock (g9 line) is approximately the predetermined spacing described above. A connection point is added so that it can be provided in

As a result, the non-inverted clock signal line CPI and the inverted clock signal line 7 are connected to the dummy wirings d13 to d15 or d8, dlO and The extending direction is blocked by d12, and the aluminum layers are alternately arranged on the first and second aluminum layers at the predetermined intervals.

Similarly, the non-inverted clock signal line CP2 and the inverted clock signal line CP2 and
The signal 1JlcP2 is connected to the corresponding inverted clock signal line C.
P2 or the dummy wiring d19 provided on the non-inverted clock signal line CP2. d21 and d23 or d16 to d1
The direction of extension thereof is interrupted by 8, which are alternately arranged on the first and second aluminum layers at a predetermined interval.

The high-speed computer of this embodiment further includes general signal lines Sc and Sd arranged relatively close to the complementary clock signal lines CPI·τT1 and CF2·CP2. Of these, the signal line Sc is arranged from one coupling point located above the complementary clock signal line toward the other coupling point located below it, and the signal line Sd is connected to the complementary clock signal line for a while. After being arranged in parallel, they are arranged towards the connection point located below. As mentioned above, the complementary clock signal lines CPI-CPI and CF2.
Layout design regarding CF2 is performed with priority over the general signal lines Sc and Sd. Therefore, the signal line Sc is parallel to the grid located at the top of the grid at the tips of the dummy wirings d9 and dll, in other words, from the non-inverted clock signal line CPI at a distance of three times the unit length β, that is, 31. After avoiding the connection point of the complementary clock signal line, it is placed toward the connection point below. Further, the signal line Sd is arranged along the lower grid of the grid at the tip of the dummy wiring d20.
In other words, they are arranged in parallel to the right at a distance of three times the unit length l, that is, 32, from the inverted clock signal line CP2, and then are arranged toward the lower connection point. Therefore, signal line Sc and complementary clock signal line CPI・C
PI or signal line Sd and complementary clock signal line CP2.
The distance at which a section long enough to cause a problem with CF2 is arranged in parallel is three times the unit length β, that is, 3j! limited to the above. For these reasons, in the high-speed computer of this embodiment, the parasitic capacitance between clock signal lines or between complementary clock signal lines and general signal wiring is reduced, and crosstalk noise between these signal wirings is reduced. Ru. As a result, the operation of the high-speed computer is stabilized, and its cycle time is equivalently speeded up.

As described above, in the high-speed computer of this embodiment, the layout design of each signal wiring including the clock signal line is automatically performed by the DA technology using the grid method. Two aluminum wiring layers are provided on the semiconductor substrate, and the grid is assumed to be in the form of a lattice, with each of these aluminum layers having a unit length E. In this embodiment, dummy wiring having a length of 21 or 1 and arranged perpendicularly to the direction in which the clock signal line extends are periodically coupled to each clock signal line at predetermined intervals.

Also, among these dummy wirings, dummy wirings d8 and d
lO and d12, dummy wirings d13 to d15, dummy wirings d16 to d18, and dummy wirings d19. d21 and d23 are arranged point-symmetrically so as to block the extension direction of the pair of clock signal lines. Therefore, these clock signal lines are alternately arranged at the predetermined intervals through the first and second aluminum layers. In addition, general signal wiring placed close to these clock signal lines has a distance that is parallel to the clock signal line over a problematically long section, or 3 times the above unit length l, that is, 32 or more. limited. Therefore, in the high-speed computer of this embodiment, parasitic capacitance between clock signal lines or between a clock signal line and general signal wiring is reduced, and crosstalk noise is reduced. As a result, the operation of the high-speed computer is stabilized, and its cycle time is equivalently speeded up.

As shown in the above two embodiments, by applying the present invention to semiconductor integrated circuit devices such as high-speed computers, the following effects can be obtained. In other words, (1) Crosstalk noise becomes a problem in high-speed computers, etc. where the layout design is automatically done by DA technology. By periodically connecting dummy wiring of a predetermined length to be placed at a predetermined interval, the distance between the general signal line and the clock signal line, etc. that is long enough to cause a problem and arranged in parallel can be reduced. It is possible to obtain the effect that the interval can be kept at a predetermined length or more, or the section in which the general signal line and the clock signal line are disposed so close to each other and in parallel that it becomes a problem can be suppressed to within the predetermined interval.

(2) In the above (paragraph 11), the aluminum wiring layer of the semiconductor substrate is made into two layers, and dummy wiring is placed in point-symmetrical positions to block the extension direction of each clock signal line, etc., which are placed in parallel. are provided periodically at predetermined intervals, so that these clock signal lines are arranged alternately at the predetermined intervals via two aluminum layers,
An effect can be obtained in that the distance over which these clock signal lines are arranged in parallel can be substantially shortened.

(3) The effect of items (1) and (2) above is that the parasitic capacitance between clock signal lines or between a clock signal line and a general fS line can be reduced, and crosstalk twist can be reduced. or can be obtained.

(4) The above items (11 to (3)) provide the effect of stabilizing the operation of a high-speed computer and equivalently speeding up its cycle time.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIGS. 1 and 2, each dummy wiring only requires that the tip and middle grids be designated as connection points, and there is no need for physical wiring. Further, the length of these dummy wirings and the number of phases of complementary clock signals are arbitrary. The semiconductor substrate may have three or more aluminum wiring layers, and the signal wiring to which the dummy wiring is coupled need not be limited to three wires.

Further, the specific arrangement method of each No. 14 wiring shown in FIGS. 1 and 2 and the relationship with the dummy wiring can be implemented in various embodiments.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to high-speed computers, which is the application field that became the R scene, but it is not limited to this, and for example, digital communication devices and digital control It can also be used in various digital processing devices such as devices.

The present invention is widely applicable at least to semiconductor integrated circuit devices whose layout design is automatically performed by DA technology.

〔Effect of the invention〕

A brief explanation of the effects obtained by the typical inventions disclosed in this patent is as follows. In other words, in high-speed computers and the like where the layout design is automatically performed using DA technology, crosstalk noise becomes a problem, and lock signal lines, etc.
By periodically coupling dummy wiring of a predetermined length arranged substantially at right angles to the direction of extension of the dummy wiring at a predetermined interval, it is possible to connect between clock signal lines or between a clock signal line and a general signal wiring. can reduce parasitic capacitance and crosstalk noise. This stabilizes the operation of a high-speed computer and equivalently speeds up its cycle time.

[Brief explanation of the drawing]

FIG. 1 is a partial layout diagram showing one embodiment of a high-speed computer to which this invention is applied, and FIG. 2 is a partial layout diagram showing another embodiment of a high-speed computer to which this invention is applied. 3 are partial layout diagrams showing an example of a conventional high-speed computer. CPI-τT to CP2/τ7...Complementary black, signal line, 5a-3f...General signal wiring, d l-d
24...Dummy wiring. Representative Patent Attorney Katsuma Ogawa, ＼ ; ) □, To/ Figure 1 Figure 2 9 `` Figure 3 8ρ

Claims (1)

Claims: 1. A semiconductor integrated circuit device comprising a signal wiring to which dummy wiring of a predetermined length arranged substantially perpendicular to the direction of extension of the signal wiring is periodically coupled. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a high-speed logic integrated circuit, and the signal wiring is a clock signal line. 3. The high-speed logic integrated circuit according to claim 1 or 2, wherein the layout design regarding general signal wiring is automatically performed by DA technology using a grid method. Semiconductor integrated circuit device.