JPH0277131A - Resin seal type semiconductor device - Google Patents

Abstract

PURPOSE:To improve characteristics and humidity resistance of a resin seal type semiconductor device by arranging a row of holes along the spreading direction of a conductor film, at the bending part of a conductor film in the corner part of a substrate. CONSTITUTION:Concerning to the change of a slit system, a row of small holes is arranged instead of a neatly L-shaped slit, for a means to limit the width of a corner part. According to a desirable practice mode, a plurality of small holes of 10mum square are arranged. By the effect of arrangement of these small holes, the resistance increase of aluminum film wiring can be reduced to a minimum. In the case where a slit 11 is formed at the corner part of a guard ring, the width of the guard ring is reduced by the width of the slit, and it is recognized that the cause of crack generation is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that is resin-sealed and has a wide conductor film on the periphery of a semiconductor substrate.

In an LSI or the like including a logic circuit, as shown in FIGS. 1 and 1A, a semiconductor element region 2 constituting an active region is formed on the entire surface of a semiconductor substrate (chip) 1, and an insulating film on the surface of the peripheral portion of the substrate is formed. Wiring 4 made of aluminum film on 3
．． A guard ring 6 is provided outside of the pump ring 5 to prevent the inversion layer, and this is connected to the ground line GN.
A structure is known in which the chip surface is covered with a pad page such as phosphosilicate glass (PSG) or silicon nitride film so that the pad portion 5 is exposed. When a semiconductor element with such a structure is sealed with resin, the mold resin is subjected to strong (strong) stress, especially at the four corners around the chip, causing cracks in the passivation film on and around the guard ring 6. It was found that this occurs.

In addition, when a semiconductor element with such a structure is subjected to a humidity test in a high temperature and high humidity atmosphere, PSG (
This causes phosphorus elution from the IJ (oxide-containing silicate glass) film, peeling of the passivation film, and corrosion of the aluminum wiring reaches the active area of the chip.
It was also found that this causes property deterioration.

The inventors of the present application focused on the fact that the defects on the passivation film crank and the like on and around the guard ring at a part of the chip corner are related to the width of the guard ring made of aluminum, and made improvements to the above-mentioned defects. Therefore, the object of the present invention is to improve the characteristic defects and improve the moisture resistance in resin-sealed semiconductor devices.

The present invention will be specifically described below with reference to Examples. First, the slit method, which was considered at the stage of studying the present invention and became the basis of the configuration of the present invention, will be explained with reference to FIGS. 2 and 2A.

In the figure, reference numeral 1 denotes a silicon semiconductor substrate, and reference numeral 2 denotes a semiconductor element region formed on the entire surface of the substrate, which is formed by introducing impurities of a conductivity type different from that of the substrate, for example, by means of diffusion or the like. A field insulating film 3 is made of, for example, a thick semiconductor oxide film (SiOx film). Reference numeral 8 denotes a first surface insulating film made of, for example, a thin Sin film. A second surface insulating film 9 is formed of, for example, a PSG (IJ oxide-containing silicate glass) film, and serves as a getter for impurities such as sodium into which phosphorus enters from the outside. 10 is an aluminum (i) wiring with a PSG film 9 and S io.

Ohmic contact is made to the semiconductor region 2 through a through hole in the film 8 . 5 is a bonding bath formed as an external terminal of the aluminum wiring, and 6 is a guard ring formed along the periphery of the substrate, which is made of an aluminum film. A guard ring 10 along the corner is provided on the guard ring on the corner of the substrate.

7 is an insulating film as a passivation film, for example PSG.
.

CVD (vapor phase chemical reaction generation) Sin! It is made of plasma-generated silicon nitride or 5OG (spin-on glass).

In such a structure, by providing a slit in the guard ring, defects such as badge-on film cracks can be prevented for the following reasons.

As shown in Figure 3, the cause of film cracks, etc. on the periphery of a resin-sealed semiconductor chip is that it should be
It has been experimentally confirmed that the corner) K stress tends to concentrate, and that the width of the aluminum film of the guard ring is significantly large. Further, various experiments have confirmed that if a slit is formed at a part of the corner of the guard ring, the width of the guard ring is reduced by the width of the slit, and the cause of crack generation is eliminated. In order to prevent an increase in the resistance of the aluminum film wiring of the guard ring, the width of the slit must be made small to some extent. For this reason, it is appropriate that the slit has a width of about 10 μm outward from the center of the aluminum ring and a length that covers the inner corner.

The present invention relates to a modification of the so-called slit method as a means for limiting the width of a part of a corner.

It is characterized by forming an array of small holes instead of the abbreviated slits. According to a preferred embodiment of the present invention,
A plurality of small holes of 10 μm square are formed. According to the arrangement of the small holes of the present invention, it is possible to minimize the increase in resistance of the aluminum film as a wiring.

The relationship between the shape of a part of the corner of a guard ring and the incidence of defects in part of the corner will be shown by the following experimental examples.

Figure 4 shows the AI of cracks in the passivation film on the guard ring without machining the corners! (Aluminum) Shows width dependence. In this case, the chip size is 4.7X4.7in
”, the temperature cycle is 20 times from -55℃ to 150℃.The passivation film is PEG/P-8iN/PSG.
=0.85/1.110.2 (μm) 3-layer structure and P-
A two-layer structure of 8iN/PSG=1.1 μm and 10.2 μm is used. Figure 5 shows the shape of the corner of the guard ring and i
Indicates the width of the membrane. As shown in FIG. 4, in the relationship of corner partial defect rate - 1 width, it is clear that L is small (.) The corner defect rate is small.

FIG. 6 shows the dependence of baccypasing film cracks on the guard ring portion on the slit width value in the AI film when a ]-shaped slit is formed in a part of the corner of the guard ring as shown in FIG. In this case, the padgepage thin film has a 〇-〇 curve of P=SiN/PSG=1.1μm/0.2μm2
Layer film, Δ...6 curve is PSG/P-8iN/PSG=
It is a three-layer film of 0.85 μm/1.1-μm and 10.2 μm. According to FIG. 6, it is clear that the partial corner defect rate is significantly reduced when the slit width is 20 μm to 40 μm.

Figure 8 shows the guard ring corner in Figure 9 (A)■)...
・Guard for cases where slits and hole rows of various shapes shown in (E) are formed (including cases where they are not formed) +) 7
7m passivation film crack A! The morphology dependence of peritoneal slits and hole rows is shown. In this case, the semiconductor pellet is 4.7 x 4.7 ram square, and the temperature cycle is -55°C to 150°C 20 times. The padgepage thin film is the same as in the example of FIG.

In Fig. 9, (A) is when no slit etc. is processed at all, a3) is when there is one long slit α1), (0 is short slit (lla, llb, 1lc), and when there are three slits, ■) is When the hole row 12 is one row, ■ is the hole row (12a
, 12b, 12c) shows the shape of a part of each guard ring corner when there are three rows. As can be seen from FIG. 8, it is clear that when a row of holes is formed in the same manner as in the case of forming slits, the defect rate at a part of the corner is reduced.

The present invention is not limited to the above embodiments. For example, the configuration and shape of the padgepage thin film formed on the Al guard ring can be modified as appropriate. The shape of the guard ring itself may change depending on the internal circuitry and placement of the bonding pads. Regarding the sealing resin body, the guard ring part may be anisotropic (it may also include an undercoating resin that is directly applied).

The present invention is applicable to all semiconductor devices having a guard ring and using a high phosphorus concentration film such as Glass Flow between layers, especially plastic sealants, LSIs, etc., and is effective for improving moisture resistance.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a part of the chip surface of a conventional semiconductor device, and FIG. 1A is a cross-sectional view taken along the line AA in FIG. FIG. 2 is a plan view showing a part of a semiconductor device invented at the study stage of the present invention, and FIG. 2A is a cross-sectional view taken along the line AA in FIG. Figure 3 is a curve diagram showing the distribution state of resin mold stress, Figure 4 is a curve diagram showing the AI width dependence of cracks in the bancivation film, and Figure 5 is a curve diagram showing the corner shape used for Figure 4. FIG. 3 is a partial plan view of the ring. FIGS. 6 to 15 show embodiments of the present invention. Among these, Fig. 6 is a curve diagram showing the dependence of cracks on the slit width in the Al film of the Badge Page M7 film in the guard ring part, Fig. 7 is a plan view showing the corner shape used for Fig. 6, and Fig. 8 The figures are plan views showing the corner shape used for the slit in the AI model of the guard ring part pudgebage carbon membrane and crank and FIG. 8. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate (chip), 2... Semiconductor element area, 3... Insulating film, 4... Wiring, 5... Bonding pad, 6... Guard ring, 7... Padgepage thin film, 8... first surface insulating film, 9... second
surface insulating film, 10...AI wiring, 11...slit, 12...hole. Figure 1 Figure 1A Figure 2 Figure 2A Figure 3 Figure 4 o-op -5tN//'' Figure 5 Figure 6 /

Claims (1)

[Claims] 1. An element region formed on one main surface of a rectangular semiconductor substrate, and a bent portion formed on an insulating film in a peripheral area of the substrate including a corner of the substrate, and a bent portion at a corner of the substrate. a conductive film extending from one side of the substrate along the other adjacent side;
a protective film formed on the conductor film, and in which the substrate is sealed with a resin body, the semiconductor device has a protective film formed on the conductor film, and the semiconductor device has a protective film formed on the conductor film; A resin-sealed semiconductor device characterized by having a row of holes along its length. 2. The semiconductor device according to claim 1, wherein the conductor film is formed to have a wider width than a wiring conductor film formed on the insulating film at the center of the substrate. 3. The conductor film formed on the periphery and the center of the substrate is made of aluminum, and the protective insulating film made of phosphosilicate glass is formed on the conductor film. A semiconductor device according to scope 2. 4. The semiconductor device according to claim 1, wherein a plurality of rows of the holes are provided in parallel.