JPH0652735B2 - Resin-sealed semiconductor device - Google Patents

Description

The present invention relates to a resin-encapsulated semiconductor device having a wide conductor film on the periphery of a semiconductor substrate.

In an LSI or the like including a logic circuit, a semiconductor element region 2 forming an active region is formed on one main surface of a semiconductor substrate (chip) 1 as shown in FIGS. 1 and 1A, and an insulating film on the peripheral surface of the substrate is formed. A wiring 4 made of an aluminum film, a bonding pad 5 and a guard ring 6 for preventing the inversion layer are provided on the outer side of the wiring 3, and the wiring 4 is connected to the ground line GN.
There is known a structure in which the chip surface is covered with passivation such as phosphosilicate glass (PSG) or a silicon nitride film so as to expose the pad portion 5 by being connected to D. When the semiconductor device having such a structure is sealed with a resin, a strong stress due to the mold resin is applied to the guard ring 6 especially at the four corners of the chip because a large (strong) stress is applied to the four corners.
It was found that cracks in the passivation film occur on and around the top.

In addition, when a semiconductor device having such a structure is subjected to a humidity resistance test in a high temperature and high humidity atmosphere, PSG which is an interlayer insulating film is used.
It was also found that phosphorus was eluted from the (phosphate compound-containing silicate glass) film, the coating passivation film was peeled off, and the corrosion of the aluminum wiring reached the active area of the chip, causing deterioration of the characteristics.

The inventor of the present invention has improved the above-mentioned defects by paying attention to the fact that the defects such as cracks on the passivation film on and around the guard ring at the chip corner portion are related to the width of the guard ring made of aluminum. Therefore, it is an object of the present invention to improve characteristic defects and moisture resistance in a resin-sealed semiconductor device.

Hereinafter, the present invention will be specifically described with reference to Examples. First, the slit system which was considered in the examination stage of the present invention and was the basis of the constitution of the present invention will be described with reference to FIGS. 2 and 2A.

In the figure, 1 is a silicon semiconductor substrate, 2 is a semiconductor element region formed on one main surface of the substrate, for example, an impurity of a conductivity type different from that of the substrate is introduced by means of diffusion or the like. 3 is a field insulating film, which is made of, for example, a thick semiconductor oxide film (SiO ₂ film). Reference numeral 8 is a first surface insulating film made of, for example, a thin SiO ₂ film. Reference numeral 9 denotes a second surface insulating film, which is formed of, for example, a PSG (phosphorus oxide-containing silicate glass) film and has a role of a getter for impurities such as sodium into which phosphorus invades from the outside. An aluminum (Al) wiring 10 makes ohmic contact with the semiconductor region 2 through the through holes of the PSG film 9 and the SiO ₂ film 8. Reference numeral 5 is a bonding pad formed as an outer terminal of the aluminum wiring, and 6 is a guard ring formed along the peripheral portion of the substrate, which is made of an aluminum film. The guard ring on the corner of the substrate is provided with a slit 10 along the corner. An insulating film 7 as a passivation film is made of, for example, PSG, CVD (gas phase chemical reaction generation) SiO ₂ plasma generation silicon nitride or SOG (spin on glass).

In such a structure, by providing a slit in the guard ring, defects such as cracks in the passivation film can be prevented for the following reasons.

As shown in FIG. 3, stress is concentrated on the edges of the chip, especially on the corners, as shown in FIG. Tend, and also
It was experimentally confirmed that the larger the width of the aluminum film of the guard ring, the more remarkable. It was also confirmed by various experiments that when the slits are formed at the corners of the guard ring, the width of the guard ring is reduced by the width of the slit, and the cause of cracking is eliminated. However, in order to prevent an increase in the resistance of the aluminum film of the guard ring as a wiring, the width of the slit must be made a small area to some extent. Therefore, it is appropriate that the slit has a width of about 10 μm outside the center of the aluminum ring and a length that covers the inside corner.

The present invention relates to such a so-called slit type deformation, and is characterized by forming an array of small holes instead of the substantially L-shaped slits as a means for limiting the width of the corner portion. According to the preferred embodiment of the present invention, a plurality of 10 μm square small holes are arranged. According to the arrangement of the small holes of the present invention, the increase in resistance of the aluminum film as the wiring can be minimized.

The relationship between the shape of the corner portion of the guard ring and the incidence rate of the defect in the corner portion will be shown by the following examples.

FIG. 4 shows the Al (aluminum) width dependence of the cracks of the passivation film on the guard ring where the corners are not processed. In this case, the chip size is 4.7 × 4.7 mm ² , and the temperature cycle is −55 ° C. to 150 ° C. and 20 times. PSG / P-SiN / PSG = 0.85 / 1.1 for the passivation film
/0.2(μm)3 layer structure and P-SiN / PSG = 1.1μ
A two-layer structure of m / 0.2 μm is used. FIG. 5 shows the shape of the corner of the guard ring and the width L of the Al film. As shown in FIG. 4, in the relationship between the defect rate of the corner and the Al width,
It is clear that the smaller L is, the smaller the defect rate is.

FIG. 6 shows the dependence of the slit width W in the Al film of the cracks in the passivation film of the guard ring when the slits are formed at the corners of the guard ring as shown in FIG. In this case, the passivation film is a two-layer film in which the ○-○ curve is P = SiN / PSG = 1.1 μm / 0.2 μm, Δ
... △ curve is PSG / P-SiN / PSG = 0.85 μm / 1.
It is a 3-layer film of 1 μm / 0.2 μm. According to FIG. 6, it is apparent that the defect rate of the corner portion is significantly reduced when the slit width is 20 μm to 40 μm.

Fig. 8 shows the cracks on the passivation film of the guard ring when the slits and holes of various shapes shown in Fig. 9 (A) (B) ... (E) are formed at the guard ring corner (including the case not formed). 3 shows the morphological dependence of slits and hole arrays in the Al film of FIG. The semiconductor pellet in this case is 4.7 x 4.7
The mm square and the temperature cycle are −55 ° C. to 150 ° C. 20 times.
The passivation film is the same as in the example of FIG.
In FIG. 9, (A) is a case where no slits are processed, (B) is a long slit (11), (C) is a short slit (11a, 11b, 11c), and 3 cases are, (D) when the row 12 of holes is one row, (E) is the row of holes (12a, 12)
The shape of each guard ring corner part when b, 12c) is three rows is shown. As can be seen from FIG. 8, it is apparent that the defect rate of the corner portion decreases when the hole array is formed similarly to the formation of the slit.

The present invention is not limited to the above embodiments. For example, the structure and shape of the passivation film formed on the Al guard ring can be appropriately modified. The shape of the guard ring itself may be changed depending on the arrangement of the internal circuit and the bonding pad. The encapsulating resin body may include an undercoating resin applied directly to the surface of the guard ring portion.

INDUSTRIAL APPLICABILITY The present invention is effective for improving the moisture resistance by being applied to all semiconductor devices having a guard ring and using a phosphorus high concentration film such as glass flow between layers, in particular, plastic sealing type, LSI and the like.

[Brief description of drawings]

FIG. 1 is a plan view showing a part of a chip surface of a conventional semiconductor device, and FIG. 1A is a sectional view taken along line AA in FIG. FIG. 2 is a plan view showing a part of a semiconductor device invented in the examination stage of the present invention, and FIG. 2A is a line AA in FIG.
FIG. FIG. 3 is a curve diagram showing the distribution of resin mold stress, FIG. 4 is a curve diagram showing the Al width dependence of the passivation film crack, and FIG. 5 is a guard ring showing the corner shape used for FIG. FIG. 6 to 9 show each embodiment for the present invention. Of these, FIG. 6 is a curve diagram showing the slit width dependence of the guard ring passivation film / cracks in the Al film, FIG. 7 is a plan view showing the corner shape used for FIG. 6, and FIG. Is a curve diagram showing the morphological dependence of the slits and hole rows in the Al film of the guard ring passivation film / cracks, FIGS. 9 (A) to (E)
FIG. 9 is a plan view showing a corner shape used for FIG. 8. 1 ... Semiconductor substrate (chip), 2 ... Semiconductor element region,
3 ... Insulating film, 4 ... Wiring, 5 ... Bonding pad, 6 ... Guard ring, 7 ... Passivation film,
8: first surface insulating film, 9: second surface insulating film, 1
0 ... Al wiring, 11 ... slit, 12 ... hole.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tatsuro Totani 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Micro Computer Engineering Stock Association (56) Reference JP-A-53-89688 (JP, A) JP-A-SHO 54-133090 (JP, A)

Claims (2)

[Claims] 1. A device region formed on one main surface of a quadrilateral semiconductor substrate and an insulating film in a peripheral portion of the substrate including a corner portion of the substrate, and having a bent portion at the corner portion of the substrate. And a conductor film extending from one side of the substrate along another side adjacent thereto, and a protective film formed so as to cover the upper surface and the side surface of the conductor film, and the substrate is sealed with a resin body. In the semiconductor device described above, along the extending direction of the conductor film,
Further, in the bent portion, a plurality of rows of holes that are substantially equivalent to slits are provided close to each other, and the protective film is extended so as to be in contact with the side surface of the conductor film and the insulating film in the holes. A resin-sealed semiconductor device characterized by the above. 2. The resin-encapsulated semiconductor device according to claim 1, wherein a plurality of rows of the holes are provided in parallel.