JPH0276254A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain high integration of a semiconductor integrated circuit device by providing a resistance element in a part different from a bipolar transistor on the main surface of a semiconductor substrate and by constructing this resistance element of a semiconductor region of the same conductivity type with that of a collector region of the bipolar transistor which is provided on the main surface of the substrate. CONSTITUTION:A transistor Bip1, MOSFETs Qpl and Qn1 and resistance elements R1 to R3 are constructed on a semiconductor substrate 1 formed of p<-> type single crystal silicon. The transistor Bip1 is constructed of an n<+> type buried layer, an n<-> type collector region 5, a p-type base region 14, an n<+> emitter region 15, a p<+> type base lead out region 16 and an n<+> type collector lead out region 17. The resistance elements are constructed of semiconductor regions of the same conductivity type with that of the collector region of the transistor. Accordingly, these resistance elements can be provided in the semiconductor regions of the opposite conductivity type to that of the collector region. According to this constitution, a semiconductor region for element isolation is dispensed with and high integration of a semiconductor integrated circuit device can be attained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device equipped with a circuit composed of a bipolar transistor and a resistive element. It is about effective techniques.

[Conventional technology]

There is an ECL (Emitter Couu) on the semiconductor substrate.
NPN bipolar transistors (
(hereinafter simply referred to as a transistor) and a resistance element.

Regarding ECL circuits, for example, rNEC technical report Vol. 1.3
6 No. 8/1983, pages 85 to 91. The resistor element is formed using the process of forming the base region of the transistor in order to shorten the manufacturing process, and is therefore formed of a p-type semiconductor region. Here, since the semiconductor substrate for forming the transistor is of P- type, it is not possible to directly form a resistance element made of the p-type semiconductor region on this main surface. Therefore, the resistive element is formed as follows. First, similarly to the n-type buried layer for leading out the collector region of the transistor, an n-type buried layer is formed in a portion of the semiconductor substrate where the resistor element is to be provided. Then, an n-type well region is further formed on this n-type semiconductor region using the process of forming an n-type collector region of a transistor, and a resistor made of the p-type semiconductor region is formed in the n-type well region. Form an element.

By the way, in order to stabilize the electrical characteristics of the resistance element, this n-type well region is always kept at a power supply potential Vcc, for example, 5
V is supplied to make it a constant potential. This power supply potential vcc is n
An n° type semiconductor region is provided near the resistive element in the − type well region, and a power supply potential vcc is connected to this n° type semiconductor region to supply power. Since the n-type well region is set to the power supply potential Vcc, the n-type buried layer below it is also set to the power supply potential Vcc.
becomes. On the other hand, in the transistor, the n-type collector region is directly connected to the power supply potential Vcc.

Some are connected to the power supply potential vcc via resistive elements, MISFETs, etc. This resistance element and M
In a device connected to the power supply potential Vcc via an ISFET or the like, the potential of its n-type collector region is equal to the power supply potential Vcc.
It is not. n- which is not fixed to this power supply potential vcc
The n-type collector region is provided with the resistive element.
Must be electrically isolated from the mold well region. Element isolation between the n-type collector region and the n-type well region is achieved by providing a p-type semiconductor region (well region) between them. Furthermore, the n-type buried layer under the n-type collector region and the n-type buried layer under the n-type well region must be separated, and this element isolation is performed between them. This is done by providing a p° type semiconductor region.

[Problem 11I to be Solved by the Invention] As a result of studying the resistance element made of the p-type semiconductor region, the inventors found the following problems.

That is, the resistance element made of the p-type semiconductor region must be formed in the n-type well region as described above, and the n° for supplying the power supply potential vcc to this well region is
Since the type semiconductor region must be provided, the area required for providing the resistor element becomes very large. In particular, E
In an integrated circuit such as a CL circuit that uses a large number of resistive elements, the ratio of the area in which the resistive elements are formed becomes large, leading to a decrease in the degree of integration. Furthermore, between the n-type well region and the n-type collector region of the transistor, and between the n-type well region and the n-type collector region of the transistor,
A p-type semiconductor region (well region) or a p-type semiconductor region for element isolation is provided between the n-type buried layer under the n-type well region and the n-type buried layer under the n-type collector region, respectively. (buried layer) must be provided. Therefore, there has been a problem in that it is difficult to improve the degree of integration of semiconductor integrated circuit devices. Further, a predetermined voltage is applied to the resistance element when operating the electronic circuit,
Since the potential of the n-type well region, that is, the potential difference with the power supply potential Vcc is small, the extension of the depletion layer between the resistance element and the n-type well region is small. Therefore, there is a problem in that the parasitic capacitance of the resistance element is large, and the circuit operation of the electronic circuit becomes slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can increase the degree of integration of semiconductor integrated circuit devices.

Another object of the present invention is to provide a technique that can improve the operating speed of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device in which a predetermined circuit is configured by providing a bipolar transistor on the main surface of a semiconductor substrate and providing a resistance element in a portion of the main surface of the semiconductor substrate that is different from the bipolar transistor, the resistance element is composed of a semiconductor region of the same conductivity type as the collector region of the bipolar transistor provided on the main surface.

[Effect]

According to the above-described means, since the resistor element is formed of a semiconductor region of the same conductivity type as the collector region of the transistor, the resistor element can be provided in a semiconductor region of the opposite conductivity type to the collector region. Therefore, there is no need for a semiconductor region for element isolation between the semiconductor region where the resistive element is provided and the collector region of the transistor, and the semiconductor integrated circuit device can be highly integrated.

Furthermore, since the circuit ground potential Vss or a potential lower than that can be applied to the semiconductor region of the opposite conductivity type in which the resistor element is provided, there is no depletion between the resistor element and the semiconductor region of the opposite conductivity type. The elongation of the layer becomes large, and the parasitic capacitance of the resistance element can be reduced. Thereby, speeding up can be achieved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

1 is a plan view of the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the cutting line ■-■ in FIG. 1, and FIG. It is an equivalent circuit of the ECL circuit configured in the semiconductor integrated circuit device of the embodiment.

Note that, in order to make the structure of the element easier to understand, FIG. 1 does not illustrate the interlayer insulating film on the semiconductor substrate.

In FIG. 3, Tl, T2. T3 is an input terminal into which a signal is input, and 0UTI and 0UT2 are output terminals from which output signals are taken out. Bipl.

Bip2. Bip3+ Bip4. Bip5. Bip6
．． Bip7. Bip8 is an NPN type bipolar transistor (hereinafter simply referred to as a transistor), Di, D2 . D
3. D4. D5 is a diode, Qpl is P channel type M
ISFET, Qnl, Qn2, Qn3, Q
n4, Qn5 are N-channel MISFETs,
R1, R2, R3, R4, R5, and R6 are resistance elements. These transistors Bipl to Bip8, diodes D1 to D5, MISFETQ p 1 + Q n 1
~Q n 5, each of the resistance elements R1 to R6 is the third
The circuit configuration is as shown in the figure. Transistor B
A reference voltage VP is input to the base of ip6. The transistors Bipi, MISFETs Qpl, Qnl, and resistance elements R1, R2, R3 in the portion surrounded by dotted lines in the equivalent circuit in FIG. 3 are configured as shown in FIGS. 1 and 2. These transistors Bip1, MI
SFETs Qpl, Qnl, and resistive elements R1°R2, R3 are constructed on a semiconductor substrate 1 made of p-type single crystal silicon, as shown in FIGS. 1 and 2. The transistor Bipl includes an n0-type buried layer 3, an n-type collector region 5, a p-type base region 14, an n°-type emitter region 15, a p-type base lead-out region 16, and a square-shaped collector lead-out region 17. It is made up of. Said n
The °-type buried layer 3 is formed on the p-type semiconductor substrate 1, and the n-type collector region 5 is provided thereon. p-type base region 14. The n'' type collector lead-out regions 17 are provided in the n- type collector regions 5. Furthermore, the n+ type emitter regions 15+p'
The type base extraction region 16 is provided within the p-type base region 14 . This transistor Bipl has an n-type collector lead-out region 17 at a power supply potential VCC, for example, 5
Since they are not connected to the V wiring, the potentials of the square-shaped collector lead-out region 17, the n-type buried layer 3, and the n-type collector region 5 vary in accordance with the operation of the circuit. However, the potential is higher than the ground potential Vss (OV). For example, in the transistor Bip2 shown in FIG. 3, the n-type collector lead-out region 17 is connected to the power supply potential vCC, for example, 5V, so in this case, n9
type collector extraction region 17 and n-type buried layer 3. n
- type collector region 5 is electrically fixed to power supply potential CC.

The P-channel MISFET Qpl is provided on the main surface of the n-type well region 5 above the square-shaped buried layer 3, and has a gate insulating film 7 made of a silicon oxide film and a tungsten silicide film (for example, on a polycrystalline silicon film). WSi2)I
A gate electrode 8 consisting of a two-layer film made of laminated high melting point metal silicide films such as II, etc., and p which form part of the source and drain.
− type semiconductor region 11, and p゛ type semiconductor region 12 forming the source and drain portions other than the P− type semiconductor region 11.
It is made up of. A side wall 24 made of a silicon oxide crotch is provided on the side surface of the gate electrode 8.

The n-type buried layer 3 is the n-type buried layer 3 of the transistor Bipl.
The n-type well region 5 is formed in the same process as the type buried layer 3, and the n-type well region 5 is formed in the n-type well region 5 of the transistor Bip1.
This is formed in the same process as the - type collector region 5. In the n-type well region 5, a wiring I made of an aluminum film is formed.
A voltage WX potential Vcc of, for example, 5V is applied via Q20, thereby constantly maintaining a constant potential. Since the n-type well region 5 is set to the power supply potential VCa, the square-shaped buried layer 3 therebelow is also fixed to the power supply potential ■cc. Reference numeral 19 denotes a connection hole, which is formed by removing the first layer of a passivation film made of, for example, a silicon oxide film.

N channel M I S F E T Q n 1 is p
A p-type buried layer 2 is provided on a −-type semiconductor substrate 1, a p-type well region 4 is further provided on this, and the p-type well region 4 is configured within the p-type well region 4. The N-channel MISFET Qnl includes a gate insulating film 7, a gate electrode 8, an n-type semiconductor region 9 forming part of the source and drain, and a portion other than the n-type semiconductor region 9 of the source and drain. It is composed of an n-type semiconductor region 10. Here, the p-type semiconductor substrate 1 is applied with a so-called back bias -van, that is, a potential lower than the ground potential Vss (OV), for example, -3V. The potential of the well region 4 is also the back bias −v@ll potential.

Each of the resistive elements R1, R2, and R3 (hereinafter simply referred to as resistive element R) has a p-type buried layer 2 provided on a p-type semiconductor substrate 1, and a p-type unino region 4 on top of the p-type buried layer 2.
is provided in this p° type well region 4.

The resistance value of the resistance element R is set to about 4 to 10 Ω. The resistance element R is composed of an n-type semiconductor region 13A on the main surface of the p-type well region 4, and n-type semiconductor regions 13B at both ends thereof. This n-type semiconductor region 13B connects the resistance element R to the wiring 2 made of aluminum film.
This is a terminal for connecting to 0 or wiring 23. The n-type semiconductor region 13A is the source of the N-channel MISFETQnl.

This is a part of the drain and is formed in the same process as a certain n-type semiconductor region 9. Therefore, n' type semiconductor region 13
A and N channel M I S F E T Q n 1
The impurity concentration and junction depth are the same as that of the n-type semiconductor region 9, which is a part of the source and drain.

Further, the n-type semiconductor region 13B at the end of the resistance element R is
It is formed in the same process as the n'-type semiconductor region 10 which is part of the source and drain of the N-channel MISFETQnl. Therefore, the n3 type semiconductor region 13B and the n3 type semiconductor region 13B
The impurity concentration and junction depth are the same as that of the ゛-type semiconductor region 10. The p-type well region 4 in which the resistance element R is provided is in contact with the n-type collector region 5 of the transistor Bipl, and the P゛-type buried layer 2 under the p°-type well region 4 is in contact with the n-type collector region 5 of the transistor Bipl. Although it is in contact with the buried layer 3, it is in contact with the p-type well region 4 and the p-type well region 4 as described above.
The potential of the °-type buried layer 2 is the back bias potential -■. On the other hand, in the transistor Bipl, the potential of the n-type collector region 5 and the n-type buried layer 3 is the ground potential Vs.
s(OV) or more, those p-type well regions 4
A reverse bias is applied between the toothed collector region 5 and between the P-type buried layer 2 and the 1-type buried layer 3, and element isolation is achieved. Due to these factors, element isolation is achieved between the resistance element R (the n-type semiconductor region 13A and the n-type semiconductor regions 13B at both ends thereof) configured in the p-type well region 4 and the transistor Bipl. . That is, p-
Device isolation is achieved without providing any semiconductor region for device isolation between the p-type buried layer 2 and the n-type buried layer 3 and between the n-type collector region 5 and the p-type well region 4. on the other hand,
The n-type well region 5 and the n-type buried layer 3 in which the P-channel MISFET Qpl is provided are electrically fixed to the power supply potential Vcc. For this reason, the p- type well region 4 and the p◆ type buried layer 2 where the resistance element R is provided, the n° type well region 5 where the P channel MISFET Qpl is provided, and the n0 type buried layer 3 thereunder.
During this period, a reverse bias is always applied to isolate the elements.

The resistance element R, the transistor Bipl, the P-channel MISFETQpl, and the N-channel MISFETQn
A field insulating film 6 made of a silicon oxide film is provided between each of the field insulating films 6 and 1. 20 is a wiring made of a first layer of aluminum film, and 21 is a second layer of passivation film, which is made of, for example, a silicon oxide film or a phosphosilicate glass (PSA) film.

22 is a connection hole formed by selectively removing the second layer passivation film 21. 23 is a wiring made of a second layer of aluminum film. P-channel MISFET
A wiring 20 is connected between each gate electrode 8 of Qpl and N-channel MISFET Qnl. p°, which forms part of the drain region of P-channel MISFET Qpl
The type semiconductor region 12 and the n' type semiconductor region 13B at one end of the resistance element R1 are connected by a wiring 23. An n-type semiconductor region 10 forming a part of the drain of the N-channel MISFET Qnl, an n-type semiconductor region 13B at a different end of the resistance element R1, and an n-type semiconductor region 13B at one end of the resistance element R2. , a wiring 20 connects the n-type collector lead-out regions 17 of the transistors Bipl through a connection hole 19. The n-type semiconductor region 13B at one end of the resistance element R2 different from the above, and the n-type semiconductor region 13B at one end of the resistance element R3.
゛-type semiconductor region 13B and p4 of transistor Bipl
The mold base extraction regions 16 are connected to each other via a connection hole 19 by a wiring 2o. N-channel MISF
n-type semiconductor region 10 forming part of the source of ETQnl
A connection hole 22 is formed between the n-type semiconductor region 13B at a different end of the resistance element R3 and the n-type emitter region 15 of the transistor Bipl by the second layer wiring 23.
．． Wiring 20. They are connected via respective connection holes 19 . The wiring 23 is a wiring for supplying the ground potential Vss (OV).

Next, the resistance element R2 of the resistance elements R1, R2, and R3, the transistor Bipl, and the N-channel MISF
A method for forming ETQnl and P-channel MISFETQpl will be explained.

Note that a description of an annealing process for activating impurities introduced by ion implantation will be omitted.

4 to 7 show transistor Bipl, N-channel MISFETQnl, and P-channel MISFETQp.
FIG. 1 is a cross-sectional view of each manufacturing process of FIG.

A method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention includes:
As shown in FIG. 4, a p-type semiconductor substrate 1 is formed with a p° type buried layer 2, an n1 type buried layer 3, a p
- type well region 4, n- type well region 5, and field insulating film 6 are formed. Next, a gate insulating film 7 made of a silicon oxide film, for example, a tungsten silicide (WSi2) film or the like is formed on a polycrystalline silicon film. Gate electrodes 8 each consisting of a two-layer film made of laminated high melting point silicide films are formed.

Next, a mask 3 made of a resist film with a pattern that exposes the regions of the resistive element R2 and the N-channel MISFET Qn1
form 0. Then, an n-type impurity such as phosphorus (P) is introduced by ion implantation to form the n-type semiconductor region 13A of the resistance element R2 and the N-channel M I S F E
An n° type semiconductor region 9 forming part of the source and drain of T Q n 1 is formed. The dose is l x 1013
/■ Make it about 2. After this ion implantation, the mask 30
remove. Next, in order to form a p° type semiconductor region 11 that forms part of the source and drain of the P-channel MISFET Qpl, a mask made of a resist film that covers the area other than the P-channel MISFET region is formed, and then ion implantation is performed. P-type impurities such as boron fluoride (B
F) is introduced to form the p-type semiconductor region 11 (FIG. 5). The dose amount is about I x 10"/as". After the p-type impurity ion implantation, the mask made of the resist film is removed. Next, a mask made of a resist film to be used for forming the n''' type collector extraction region 17 of the transistor Bipl is formed,
After this, ion implantation is performed to add n-type impurities such as phosphorus (P).
) is introduced to form an n-type collector extraction region 17. The dose amount is about 5×10''/CM''. After that, the mask made of the resist film is removed. Next, a mask 31 (FIG. 5) made of a resist film for forming the p-type base region 14 of the transistor Bipl is formed, and then, as shown in FIG. Introducing (B) and p
A mold base region 14 is formed. The dose is 2×101
It is about 4/■2. After ion implantation, mask 31 is removed. Next, by CVD, for example, the gate electrode 8 is
A silicon oxide film is formed covering it, and this is etched back by reactive ion etching to form a sidewall 24 (FIG. 6). Next, N channel M I S F
A mask 3 made of a resist film with a pattern exposing the E T Q n 1 region and the portion where the n◆ type semiconductor region 13B, which is the lead-out region at both ends of the resistance element R2, is formed.
After that, an n-type impurity such as arsenic (As) is introduced by ion implantation to form the n-type semiconductor region 1.
0 and n.type semiconductor regions 13B are formed. The dose amount is
The value is set to a value sufficient to establish ohmic contact between the n.type semiconductor region 10 and the n.type semiconductor region 13B and the aluminum film. After this ion implantation, the mask 32 is removed. Next, after forming a mask consisting of a resist film with a pattern that exposes the P-channel MISFET QPI region, a p-type impurity such as boron difluoride (BF2) is introduced by ion implantation to form part of the source and drain. A p' type semiconductor region 12 (FIG. 7) is formed.

The dose is set to be sufficient to establish ohmic contact with the aluminum film. After ion implantation, the mask made of resist film is removed. Next, a mask made of a resist film with a pattern that exposes the region where the n-type emitter region 15 of the transistor Bip1 is formed is formed, and then ion implantation is performed to inject n-type impurities such as arsenic (
As) is introduced to form an n° type emitter region 15 (FIG. 7). The dose amount is about 5×10”/12.

After ion implantation, the mask made of resist film is removed. Next, a mask 33 (FIG. 7) made of a resist film is formed in order to form the p0 type base extraction region 16 of the transistor Bipl, and then a p type impurity such as boron (B) is introduced by ion implantation to form the p1 base region 16. A mold base extraction region 16 is formed. The dose is set to a value sufficient to establish ohmic contact with the aluminum film. After ion implantation, mask 33 is removed.

In this way, the n-type semiconductor region forming the resistance element R is N
It can be formed using the process of forming n-type semiconductor regions 9, which are part of the source and drain of the channel MISFETQnl, and the n-type lead-out regions 13 at both ends of the resistance element R can be formed using the process of forming the n-type semiconductor regions 9, which are part of the source and drain of the channel MISFETQnl. It can be formed using the process of forming the high concentration layers of the source and drain, that is, the n° type semiconductor region 10.

As can be seen from the above description, the following effects can be obtained according to this embodiment.

(1) Bipolar transistor B on the main surface of the semiconductor substrate 1
In the semiconductor integrated circuit device in which a predetermined circuit is configured by providing a resistor element R on a main surface of the semiconductor substrate 1 at a portion different from the bipolar transistor Bipl, the resistor element R is provided on the main surface of the semiconductor substrate 1. A part of the provided bipolar transistor has a semiconductor region of the same conductivity type as the collector region 5, that is, an n- type semiconductor region and an n+ region at both ends thereof.
By forming the resistive element R with the type lead-out region 13, the resistive element R can be provided in a semiconductor region (p-type well region 4) having a conductivity type opposite to that of the n-type collector region 5. Therefore, the semiconductor region (p-type well region 4) where the resistance element R is provided and the n-type well region 4 of the transistor
A semiconductor region for element isolation between the mold collector region 5 and the mold collector region 5 can be made unnecessary. Further, since the ground potential Vss can be applied from the p-type semiconductor substrate 1 to the p-type well region 4 in which the resistance element R is provided via the p-type semiconductor region 2 below, the resistance Motoko Rt! : It is not necessary to provide an n-type semiconductor region for applying a predetermined constant potential near the resistance element R, as in the case where the structure is made of a P-type semiconductor region on the surface of an n-type well region. good.

That is, the semiconductor region for applying a predetermined constant potential near the resistance element R can be eliminated.

For these reasons, it is possible to improve the degree of integration of a semiconductor integrated circuit device.

(2) P-type well region 4 where resistance element R is provided
Since a potential lower than the ground potential Vss, that is, a back bias −V a a can be applied to the resistive element R
Since the depletion layer between the n-type semiconductor region 13A and the n-type semiconductor region 13B forming the p-type well region 4 can be greatly extended, the parasitic capacitance of the resistance element R can be reduced. This makes it possible to speed up the circuit operation of the semiconductor integrated circuit device.

(3) Resistance element R is N-channel MISFET
Since it can be formed using the process of forming the source and drain of Qn, the resistance element R can be formed without increasing the manufacturing process.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

Needless to say, various changes can be made without departing from the spirit of the invention.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Since the resistance element is formed of a semiconductor region of the same conductivity type as the collector region of the transistor, the resistance element can be provided in a semiconductor region of the opposite conductivity type to the collector region. Therefore, there is no need for a semiconductor region for element isolation between the semiconductor region where the resistive element is provided and the collector region of the transistor, and the semiconductor integrated circuit device can be highly integrated.

[Brief explanation of the drawing]

1 is a plan view of the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the cutting line ■-■ in FIG. 1, and FIG. Equivalent circuits of the ECL circuit configured in the semiconductor integrated circuit device of the embodiment, FIGS. 4 to 7, show the transistor Bipl, N-channel MISFETQ
n1. 3A and 3B are cross-sectional views of each manufacturing process of P-channel MISFET Qp 1. FIG. In the figure, R1, R2, R3--resistance element, 13-n'' type lead-out region, 1--P- type semiconductor substrate, 2--p゛-type buried layer, 3--n° type buried layer , 4...p-
type well region, 5...n-type well region (or collector region), 9.10...source and drain of N-channel MISFET, 11.12...p-channel MISFE
T's source. Drain, 14...p type base region, 15...n' emitter region, 16...p' type base coloring region, 17... n' type collector extraction region.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a predetermined circuit is configured by providing a bipolar transistor on the main surface of a semiconductor substrate and providing a resistance element in a portion of the main surface of the semiconductor substrate that is different from the bipolar transistor. A semiconductor integrated circuit device, wherein the resistive element comprises a semiconductor region of the same conductivity type as a collector region of a bipolar transistor provided on the main surface. 2. The resistance element is an N-channel MISFE whose source and drain are composed of a low impurity concentration layer and a high impurity concentration layer.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed in the same process as the low impurity concentration layer of T.