JPH0273441A - Error control circuit for storage - Google Patents

Abstract

PURPOSE:To keep the throughput of a diagnostic processor by preventing the transmission of the error attention signal after the count value of the error detecting frequency reaches a prescribed level or after the attention preventing signal is received. CONSTITUTION:An error detecting circuit 12 detects an error and sends the error information to an error information holding circuit EIF 13. Then the circuit 12 transmits the error detecting signals to an attention transmission control circuit 14 and a counter 15. When an EIF read command signal is sent from a diagnostic processor 11, the EIF 13 sends the error holding information to the processor 11. The counter 15 inputs the error detecting signal and sends the count value to the circuit 14. The circuit 14 inhibits the transmission of the attention signal in case the count value of the counter 15 reaches a prescribed level or the attention signal is received when the error detecting signal is received. Thus it is possible to keep the throughput of the processor 11 without producing a very busy state just with execution of the 1-bit error processing in case many 1-bit errors occur continuously.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to error detection and reporting in information processing at.

The present invention relates to improvements in retention methods, and particularly to circuits for controlling errors in storage devices.

(Prior art) Conventionally, the control circuit of this type of storage device has been configured as shown in FIG. 2. In FIG. 21 is a diagnostic processor (DGP) f, and the diagnostic processor 21 is a so-called service processor (SVP).
). Further, 22 is an error detection circuit.

23 is a 2-F# information holding circuit IIF).

The error detection circuit 22 receives a symptom signal such as a syndrome from a signal line 24. When an error is detected, the error detection circuit 22 sends error information to the error information holding circuit (gIF) 23 via the signal line 25, and directly sends an error detection signal to the diagnostic processor 21 via the signal line 26. Thereafter, the error information held in the error holding circuit 23 is sent to the diagnostic processor 21 via the signal line 28 in response to the FfIF read command signal sent from the first diagnostic processor 21 to the signal @27.

(Problems to be Solved by the Invention) In the conventional error control circuit described above, when an error is detected, the error is immediately reported. Therefore, for example, 2-bit error detection, 1-bit error correction (EDAC)
If a 1-bit error occurs frequently in a functional storage device, the problem will not disappear unless the faulty storage chip is replaced. It is very likely that one-bit errors occur frequently as described above.

In the above situation, the cycle from error detection to sending of error holding information described above is repeated endlessly, and the diagnostic processor, which normally has other important tasks, is so busy handling only the 1-bit error that it cannot perform its original work. work (service)
The disadvantage is that the process is delayed. Furthermore, if there is an additional note,
As error information to point out a defective chip.

As for a one-bit error, information on several errors is enough to point out a faulty chip using well-known techniques.

An object of the present invention is to send an error attention signal to a diagnostic processor, to count the number of error detections with a counter, and to send an attention signal when the count value of the counter reaches a predetermined value or when an instruction is given by the diagnostic processor. Until the inhibition signal arrives, the attention signal is sent, but after reaching a predetermined value or after the arrival of the attention inhibition signal, the error attention signal is suppressed to eliminate the above drawback, and the diagnostic processor We propose an error information holding circuit that is configured in such a way that the processing power is not reduced.

(Means for determining problem a) The error control circuit of the storage device according to the present invention is connected to a diagnostic processor and includes an error detection circuit and an error information holding circuit.

This configuration includes a counter and an attention sending control circuit.

The counter is used to count the number of times an error is detected when sending the 2-attention signal to the B/J processor.

The attention sending control circuit continues until the count value of the counter reaches a predetermined value or the diagnostic processor! All error attention signals are sent until the instructed attention suppression signal arrives, but after reaching a predetermined value or after the arrival of the attention suppression signal, the amount of error attention signal transmission is suppressed.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

Figure WJ1 is a block diagram showing one embodiment of an error control circuit according to the present invention. In FIG.

Reference numeral 10 denotes an error control circuit for detecting, reporting, and holding errors, and 11 denotes a diagnostic processor (LIGF), which may be a so-called service processor (SVP). 12 is engineering 2-
13 is an error information holding circuit; 14 is an attention sending control circuit; and 15 is a counter.

The error detection circuit 12 inputs error symptom signals such as syndromes via the signal line 101, and when an error is detected, sends error information to the error information holding circuit 13 via the signal line 102, and issues an attention via the signal line 103. It sends out an error detection signal to the sending control circuit 14 and the counter 15.

The error information holding circuit 13 receives error information from the signal line 102 and holds the error information. When an EIF read command signal is sent from the diagnostic processor 11 via the signal line 105, the error information holding circuit 13 sends error holding information to the diagnostic processor 11 via the signal line 106.

The counter 15 receives the error detection signal through the signal line 103, and the counter 15 is a counter that counts up every time the error detection signal is input. counter 1
5 sends the count value to the attention sending control circuit 14 via the signal line 107. The attention sending control circuit 14 receives the error detection signal on the signal line 103 and the signal 1
The count value on 11107 and the attention suppression signal on signal line 108 are input, and the signal line 104 is input as necessary.
sends an error attention signal to the diagnostic processor 11.

When the attention sending control circuit 14 receives the error detection signal through all the signal lines 103.

Determine whether the counter value has reached a predetermined value l,
If the above predetermined value l is not exceeded, or if the attention suppression signal has not arrived.

An error attention signal is sent via signal line 104. On the other hand, if the predetermined value has been reached or the attention suppression signal has arrived, the signal line 104
It operates so as not to send an error attention signal to the above.

The diagnostic processor 11 receiving the error attention signal from the signal line 104 sends the error attention signal to the signal line 105? : Sends an EIF read command signal through the signal line 106, and causes the error information holding circuit 13 to send error holding information via the signal line 106.

(Effects of the Invention) As described above, the present invention operates on sending an error attention signal to a diagnostic processor.

Along with counting the number of error detections with a counter.

An error attention signal is sent until the count value reaches a predetermined value or until an attention suppression signal instructed by the diagnostic processor arrives, but an error attention signal is sent after reaching the predetermined value or after the attention suppression signal arrives. By suppressing the transmission of 1, for example, if you are using a storage device with an EDAC function and 1-bit errors occur frequently or in succession, the 1-bit error processing will not overwhelm the diagnostic processor with only 1-bit error processing. This has the effect of providing the following services.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an error control circuit according to the present invention. FIG. 2 is a block diagram showing an example of an error control circuit according to the prior art. 10.20...Error control circuit 11.21...Diagnostic processor 12.22...Error detection circuit 13.23...Error information holding circuit 14...Error attention sending control circuit 15...
Counters 24-28, 101-107...Signal lines Fig. 1

Claims (1)

[Claims] An error control circuit for a storage device connected to a diagnostic processor and equipped with an error detection circuit and an error information holding circuit, the circuit comprising: an error control circuit for counting the number of error detections when sending an error attention signal to the diagnostic processor; a counter, and until the count value of the counter reaches a predetermined value,
Alternatively, the error attention signal is transmitted until the attention suppression signal instructed by the diagnostic processor arrives, but after the predetermined value is reached or after the attention suppression signal arrives, the error attention signal is suppressed from being transmitted. 1. An error control circuit for a storage device, comprising: an attention sending control circuit.