JPH01219934A - Storage device - Google Patents

Abstract

PURPOSE:To reduce the burden on a diagnostic processor by controlling a device so that an error warning signal is not sent to the diagnosing processor when the number of times of sending of the error warning signal reaches a prescribed value. CONSTITUTION:When an error symptom signal 101 is inputted to an error detecting circuit 12 and error is detected, information 102 is sent to an error information holding circuit 13, and an error detection signal 103 is sent to an error warning signal sending control circuit 14 and a counter 15. When an error information read command signal 105 from a diagnosing processor 11 is given to the error information holding circuit 13, the circuit 13 sends error holding information 106 to the processor 11. The counter 15 sends its counted value 107 to the error warning signal sending control circuit 14. When the counted value reaches a prescribed value, the error warning signal 104 is not sent.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device for an information processing device, and particularly to error control of the storage device.

〔overview〕

The present invention provides a storage device that sends an error warning signal to a diagnostic processor when an error is detected by an error detection circuit, in which the error warning signal is reported to the diagnostic processor until a predetermined number of errors occur, and when the predetermined number is exceeded. By suppressing the sending of error warning signals, the burden on the diagnostic processor for 1-bit error processing is reduced, and other processing services can also be performed.

[Conventional technology]

Conventionally, a control mechanism of a storage device that performs this type of error detection and control has the configuration shown in FIG.

In FIG. 2, the reference numeral 20 surrounded by a dashed line indicates a block showing only error detection, reporting, and retention circuits in the storage device, and the reference numeral 21 indicates a diagnostic processor (D
GP). Note that another service processor may be used as the diagnostic processor 21.

The error detection/report/holding block 20 includes an error detection circuit 22 and, when an error is detected by the error detection circuit 22,
an error information holding circuit (EIF) 2 that holds error information and reports error information according to instructions from the diagnostic processor 21;
It has 3. To explain its operation, first,
An error symptom signal 24 such as a syndrome is input manually from a storage element etc. to an error detection circuit 22, and when an error is detected, an error information 25 is output to an error information holding circuit 23, and the error detection signal 2G is used as an error warning signal for diagnosis. It is sent to the processor 21. Thereafter, an error information read command signal 27 is given to the error information holding circuit 23 from the diagnostic processor 21, and the error information 28 held from the error information holding circuit 23 is sent to the diagnostic processor 21.

[Problem that the invention seeks to solve]

In the conventional error control mechanism described above, the error detection circuit 2
If an error is detected in step 2, the error will be reported immediately. For example, in a storage device having 2-bit error detection, 1-bit error correction functions, if 1-bit errors occur frequently, the occurrence of errors will not disappear unless the faulty storage chip is replaced.

In such a state, due to the above-mentioned error detection, the cycle of transmitting the error retention information is repeated and postponed, and the diagnostic processor 21, which originally needs to perform an important service, is forced to process this one-bit error. This has the disadvantage that the service that should be performed by the original diagnostic processor is delayed. Also,
As for the error information to point out a faulty chip, in the case of a 1-bit error, only a few times of error information is enough to point out a faulty chip, so operating the fault diagnosis processor with continuous error detection signals requires less resources. It will be wasted.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks, and to provide a storage device that can reduce the burden on a diagnostic processor when 1-bit errors occur frequently and provide services according to the original job.

[Means for solving problems]

The present invention includes an error detection circuit that performs an error check on data read from a storage element and sends an error warning signal to a diagnostic processor when an error is detected; A storage device comprising: an error information holding circuit that reports error information to a diagnostic processor; and a control circuit that suppresses the sending of the error warning signal after the error warning signal reaches a predetermined value.

[Effect]

In the present invention, the count value of the counter is incremented every time the error detection circuit detects an error. The value of this counter is input to the error warning signal sending control circuit which is manually operated by the output of the error detection circuit, and until the value of this counter reaches a predetermined value, the error warning signal is not sent from the error warning signal sending control circuit. , when the value exceeds a predetermined value, the error warning signal is controlled not to be sent to the diagnostic processor, thereby reducing the burden on the diagnostic processor when one-bit errors occur frequently or repeatedly.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 10 is an error detection/report/hold block corresponding to the error detection/report/hold block 20 in FIG. Similarly to FIG. 2, a diagnostic processor 11, an error detection circuit 12, an error information holding circuit (
E IF) 13.

The characteristic configuration of this embodiment is that, in addition to the conventional circuit, there is a counter 15 to which the error detection signal output of the error detection circuit 12 is manually input, and the output of this counter 15 is input, and the value of this counter 15 is set to a predetermined value. In the following cases, the error detection signal of the error detection circuit 12 is sent to the diagnostic processor 11, and when the error detection signal exceeds a predetermined value, the error warning signal is used to control the sending of the error detection signal to the diagnostic processor 11. This is because a transmission control circuit (ATT transmission control circuit) 14 is provided.

Next, the operation of the apparatus according to the present invention will be explained.

An error symptom signal 101 such as a syndrome is input to the error detection circuit 12, and when an error is detected, the error information 102 is sent to the error information holding circuit 13, and the error warning signal transmission control circuit 14 and the counter 15 are notified of the error detection. A signal 103 is sent out. The error information holding circuit 13 is
The error information 102 is manually generated to hold the error information,
Error information read command signal 1 from diagnostic processor 11
If 05 is given, the error holding information 106 is sent to the diagnostic processor 11.

The counter 15 is a counter to which the error detection signal 103 is input, and for example, counts up every time the error detection signal 103 is input, and the counter value is 10.
7 is sent to the error warning signal sending control circuit 14. The error warning signal sending control circuit 14 outputs the error detection signal 103
and counter value 107, and sends an error warning signal 104 to the diagnostic processor 11 as necessary. When this error warning signal sending control circuit 14 receives the error detection signal 103, it determines whether the counter value has reached a predetermined value, and if it has not reached the predetermined value, it issues an error warning signal 104. Send. On the other hand, if the predetermined value is reached, the error warning signal 104 is not sent.
Controls the transmission of 04.

The diagnostic processor 11 that received the error warning signal 104
As in the conventional example, the error information holding circuit 13 sends an error holding information read command signal 105 to the error information holding circuit 13, and reads the error holding information 106 from the error information holding circuit 13.

Note that the counter 15 is reset by the diagnostic processor 11.
This can be done by any method, such as by control from the central processing unit, every time a certain period of time passes, or every time a series of processing is completed in the central processing unit.

Further, similar operation is possible even if another service processor is used in place of the diagnostic processor 11.

〔Effect of the invention〕

As described above, when the storage device of the present invention sends an error warning signal to the diagnostic processor, even if 1-bit errors occur frequently, if the number of detected errors reaches a predetermined number, the error is not detected. Since the sending of warning signals to the diagnostic processor is suppressed, even if 1-bit errors occur frequently, the burden on the diagnostic processor for 1-bit error processing is reduced, allowing the diagnostic processor to perform its original job and provide services. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a conventional example. 10.20...Error detection/reporting/holding block, 1
1.21...Diagnostic processor (DGP), 12.2
2...Error detection circuit, 13.23...Error information holding circuit (EIF), 14...Error alarm signal sending control circuit, 15...Counter.

Claims (1)

[Claims] 1. An error detection circuit that performs an error check on data read from a storage element and sends an error warning signal to a diagnostic processor when an error is detected; and an error detection circuit that holds error information and responds to instructions from the diagnostic processor. A storage device equipped with an error information holding circuit that reports held error information to a diagnostic processor, and a counter that counts the number of error detections by the error detection circuit, and the above error warning until the value of this counter reaches a predetermined value. A storage device comprising: a control circuit that sends a signal to a diagnostic processor and suppresses sending of the error warning signal after reaching a predetermined value.