JPH0227444A - Memory - Google Patents

Abstract

PURPOSE:To efficiently execute the diagnosing processing by operating so as to suppress the sending of an attention signal after a prescribed value set beforehand is reached. CONSTITUTION:At the time of sending an error attention signal to a diagnosing processor 11 by an attention sending control circuit 14, the number of the times of an error is counted by a counter 15, and until the prescribed value is reached by the counted value, the error attention signal is sent and after an arbitrarily settable prescribed value is reached from an external device, the sending of the error attention signal is suppressed. Consequently, when for example, in the memory having 2-bit error detecting and 1-bit error correcting functions, the 1-bit error occurs many times and continuously, the diagnosing processor 11 cannot be cancelled only by the 1-bit error processing. Thus, the diagnosing processing can be efficiently executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in information processing devices, and particularly to error control in storage devices thereof.

(Prior Art) Conventionally, in this type of storage device, an error control method as shown in FIG. 2 has been adopted.

In FIG. 2, 20 indicates error detection/reporting of the storage device.
Holding block, 21 is a diagnostic processor (DGP), 22
23 is an error detection circuit, and 23 is an error information holding circuit (FfI
F).

Here, the diagnostic processor 21 is a service processor (svp
) is also fine.

The error detection circuit 22 inputs an error symptom signal such as a syndrome from the signal line 24, and when an error is detected, sends the error information to the error information holding circuit 23 via the signal line 25, and directly sends it to the diagnostic processor 21 from signal #26. : Sends an error detection signal.

After the test, when an EIF read command signal is sent from the diagnostic processor 21 onto the signal line 27, the error information holding circuit 23
The error information held from the memory is sent to the diagnostic processor 21 via the signal line 28.

(Problems to be Solved by the Invention) In the conventional error control method described above, when an error is detected, the error is immediately reported. Therefore, for example, EDAC (2-bit error detection, 1-bit error correction)
In storage devices with functions, 1 and 1 errors occur frequently.
In such cases, the error will not go away unless the faulty memory chip is replaced. It is very likely that one-bit errors occur frequently and consecutively.

In the above-mentioned state, the cycle from error detection to transmission of error-retained information is repeated endlessly, and the diagnostic processor 21, which is originally engaged in other important tasks, is busy with only this 1-bit error processing, The disadvantage is that the work (services) of people are delayed.

Additionally, as information for pointing out a faulty chip, in the case of a single-bit error, information on several (or several) errors is enough to point out a faulty chip using well-known technology. The drawback is that it does not provide the above information.

An object of the present invention is to count the number of error detections with a counter when sending an attention signal to a diagnostic processor, and send out an attention signal until the count value reaches a predetermined value. Provided is a storage device equipped with an error detection/report/holding block configured to eliminate the above-mentioned drawbacks and efficiently execute v-cutting processing by operating in a manner that suppresses the sending of attention signals after the value has been reached. It's about doing.

(!!Means for Solving the Problem) The error detection/report/holding block of the storage device according to the present invention is configured to include an error detection circuit, an error information holding circuit, a counter, and an attention sending control circuit. It is something.

The error detection circuit receives an error symptom signal, and when it detects the error, it provides an error detection signal to the diagnostic processor and sends error information to the error information holding circuit.

The error information holding circuit receives and holds error information sent from the error detection circuit, and also sends the held error information to the diagnostic processor in response to an EIP read command signal from the diagnostic processor.

The counter is for counting the number of error detections when sending an error attention signal to the diagnostic processor.

The attention sending control circuit sends an attention signal until the count value of the counter reaches a preset predetermined value, but operates to suppress the sending of the attention signal after the predetermined value is exceeded. .

(Example) Next, one aspect of the present invention will be explained with reference to the drawings.

FIG. 1 shows error detection/reporting/error detection/reporting of a storage device according to the present invention.
FIG. 2 is a block diagram showing an example of a holding block.

In FIG. 1, 10 is an error detection/report/holding block, 11 is a diagnostic processor, 12 is an error detection circuit, and 13 is an error detection/report/holding block.
1 is an error information holding circuit, 14 is an attention sending control circuit, and 15 is a counter.

In FIG. 1, the diagnostic processor 11 may be a service processor.The error detection circuit 12 inputs an error symptom signal such as a syndrome from the signal #101, and when an error is detected, the error information holding circuit 13 is sent to the error information holding circuit 13 via the signal line 102. The error detection signal is sent to the attention sending control circuit 14 and the counter 15 via the signal line 103.

The error information time holding circuit 13 inputs error information via the signal 11J102, holds the error information, and when an EIF read command signal is sent from the diagnostic processor 11 via the signal 1!105, it inputs the error information through the signal line 106. The error holding information is sent to the diagnostic processor 11 via the diagnostic processor 11.

The counter 15 inputs the process 2-detection signal from the signal line 103, and counts up every time an error detection signal is input, for example, and the count value is input to the signal line 107.
It is sent to the attention sending control circuit 14 via.

The attention sending control circuit 14 inputs the error detection signal on the signal line 103, the predetermined value setting signal on the signal line 10g, and the counter value on the signal 11107, and sends an error attention signal via the signal line 104 as necessary. It is sent to the diagnostic processor 11. Attention sending control circuit 14
A predetermined value is set in advance by a predetermined value setting signal sent from the diagnostic processor 11 to the signal line 108. signal line 10
3, the Azone 71 output control circuit 14 determines whether the count value has reached a predetermined value, and if the count value has not reached the predetermined value, sends an error attention signal to the signal line 104. Send upward. On the other hand,
If the predetermined value has been reached, signal #104 is turned on.
Avoid sending signal.

The diagnostic grosser 11 that has received the error attention signal from the signal line 104 sends out an EIF read command signal onto the signal line 105 , and sends the EIF read command signal from the error information holding circuit 13 to the signal line 10 .
6, have the error retention information sent.

Note that the predetermined value of the attention sending control circuit 140 is the signal #
It is possible to arbitrarily set the value using a predetermined value setting signal on 108, but it goes without saying that the value can also be set using a known technique from a central processing unit (CPU) or the like.

(Effects of the Invention) As explained above, the present invention counts the number of error detections using a counter when sending an error attention signal to a diagnostic processor, and the error attention signal is not output until the count value reaches a predetermined value. However, after reaching a predetermined value that can be set arbitrarily from an external device, the exit of the error attention signal is suppressed.
When 1-bit errors occur frequently or continuously in a storage device having an AC function, the diagnostic processor can provide the original service without overloading the diagnostic processor with only 1-bit error processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of error detection/report/retention blocks provided in a storage device according to the present invention. FIG. 2 is a block diagram showing an example of an error detection/report/holding block provided in a storage device according to the prior art. 10.20--Error detection/report/holding block 11, 21--Diagnosis block 12, 22--Error detection circuit 13.23--Molar information holding circuit 14...Error adensity transmission control circuit 15...
counter

Claims (1)

[Claims] an error detection circuit for inputting an error symptom signal and, when an error is detected, giving an error detection signal to a diagnostic processor and transmitting error information; and receiving and holding error information transmitted from the error detection circuit;
An error information holding circuit for sending the held error information to the diagnostic processor in response to an EIF read command signal from the diagnostic processor, and counting the number of error detections when sending an error attention signal to the diagnostic processor. a counter for transmitting the attention signal until a predetermined value preset by the count value of the counter is reached, but operating to suppress the transmission of the attention signal after reaching the predetermined value; A storage device comprising an error detection/report/holding block configured with an attention sending control circuit.