JPH0283646A - Memory error monitoring circuit - Google Patents

Abstract

PURPOSE:To reduce overhead loss due to an error processing operation and to improve availability by counting the number of times of a one-bit error instead of the report of the one-bit error to a central processing unit even when the one-bit error occurs in read data from a memory circuit. CONSTITUTION:When the one-bit error occurs in the read data 100, a one-bit error signal 102 is not sent directly to the central processing unit, and an error gate circuit 4 is provided on a middle way, and selection whether or not an error report should be issued is performed by an instruction signal 500 from the central processing unit. Meanwhile, a one-bit error counter circuit 3 counts the number of times of the one-bit error, and count data 301 is sent to the central processing unit via a gate circuit 6, and the gate circuit 6 suppresses the count data 301 by an instruction signal 600 from the central processing unit. In such a way, it is possible to prevent the availability of the system from being affected by the error report of a correctable one-bit error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory error monitoring circuit for read data from a memory, and in particular, for detecting errors in read data read from a main memory in an information processing device. and a memory error monitoring circuit that performs correction.

[Prior Art] When a 1-bit error is detected in read data from a memory circuit, a conventional memory error monitoring circuit corrects the read data error and always centrally detects that a 1-bit error has occurred. It was reported to the processing equipment. Therefore, the central processing unit collects necessary data each time.

[Problems to be Solved] The conventional memory error monitoring circuit described above detects and corrects 1-bit errors for bit data from memory, and whenever a 1-bit error occurs, it is always reported to the central processing unit. As a result, the central processing unit collects the necessary data each time, and as a result of the processing operation, overhead loss increases, and if one-bit errors occur frequently due to element failure, etc., the central processing unit cannot operate the system. The problem of having an impact on the environment has been resolved.

2. The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a memory error monitoring circuit that does not affect system operation due to error reporting of correctable 1-bit errors.

[Means for Solving the Problems] In order to achieve the above object, the memory error monitoring circuit of the present invention detects a 1-bit error in read data from the memory, and sends a 1-bit error signal when a 1-bit error is detected. a memory error detection circuit that outputs correct data based on read data and a 1-bit error signal transmitted from the memory error detection circuit; and an error correction circuit that transmits correct data based on the read data and 1-bit error signal transmitted from the memory error detection circuit; and an error information reporting control circuit that controls the occurrence and counting of l-bit errors, and the reporting of information regarding overflow of the bit error counter.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a memory error monitoring circuit according to an embodiment of the present invention.

In the figure, ] detects a 1-bit error and a 2-bit error for the 1S data from an external memory circuit,
This is a memory error detection circuit that sends out a 1-bit error signal or a 2-bit error signal. Further, 2 is a read data signal sent from this memory error detection circuit 1 and 1 is
This is an error correction circuit that inputs a bit error signal, corrects erroneous read data, and sends correct data to the central processing unit.

Next, 3 is a 1-bit error counter circuit that counts up +1 by the 1-bit error signal sent from the memory error detection circuit 1, and 4 is a 1-bit error counter circuit that also gates the 1-bit error signal from the memory error detection circuit 1, and An error gate circuit that suppresses error reporting to the processing device;
5 is a mode register circuit that controls the inhibition signal to the error gate circuit 4 and sets whether or not to report an error to the central processing unit, and 6 is an error count signal from the 1-bit error counter circuit 3. This is a gate circuit that suppresses this by a gate signal from the central processing unit.

That is, these Ebit error counter circuit 3 to gate circuit 6 constitute an error information reporting control circuit.

In the above configuration, paste-j・data 1 from the memory circuit
00 is input to the memory error detection circuit 1, and 1-bit error and 2-bit error are detected. Note that the error detection method employs a method of adding a simple FCC to data, and can be easily implemented.

Here, if the read data 100 has a one-hit error, the one-bit error is detected by the memory error detection circuit 1, and the one-bit error signal 102 and the data signal 101 are input to the error correction circuit 2. Then, the error correction circuit 2 corrects the fixed data signal from the memory circuit together with the FCC, and corrects the correct data signal.
01 to the central processing unit.

On the other hand, 2-hit errors are generally considered uncorrectable. Therefore, when the memory error detection circuit 1 detects a 2-bit error in the read data 100, a 2-bit error signal 103 is sent to the central processing unit.

By the way, in the case of a 1-bit error, the data signal 201 has been correctly corrected, so the central processing unit can be used as is as if no error had occurred.

On the other hand, in the case of a 2-bit error, the data signal 201 is the same as the one in which the error occurred and cannot be used by the central processing unit. However, since it can be determined by the 2-bit error signal 103 sent from the memory error detection circuit 1, it can be dealt with by re-reading.

Now, the 1-bit error signal 102 detected by the memory error detection circuit 1 is also sent to the 1-bit error counter circuit 3 and the error gate circuit 4.

This 1-bit error counter circuit 3 has a counting function that uses the 1-bit error signal 103 as a trigger to increment by 1. In other words, the number of occurrences of one-bit errors can be counted.

On the other hand, the 1-bit error signal 102 input to the error gate circuit 4 is sent to the central processing unit.

By the way, normally in a central processing unit, even if a 1-bit error occurs, the data itself is corrected and is used as is, but the fact that a 1-bit error has occurred is recorded. That is, when a 1-bit error occurs, a 1-bit error signal 102 is sent out from the memory error detection circuit 1, and is directly notified to the central processing unit. Then, the central processing unit uses this 1-bit error signal as a trigger to collect status information such as memory state information.

However, when collecting the status, general processing operations are interrupted, which inevitably leads to a decrease in performance. This significantly degrades the performance of the central processing unit when one-bit errors occur frequently due to failure of elements or the like. That is, even though error correction has been performed and the system is operating correctly, the processing operation becomes slow, which often causes problems.

In contrast, in this embodiment, the 1-bit error signal 102
The error gate circuit 4 is provided in the middle without directly sending the data to the central processing unit.

Whether or not to report an error can be selected by an instruction signal from the central processing unit. That is, a mode register circuit 5 is provided so that it can be set or reset by an instruction signal 500, and the mode is determined by a mode signal 501 which is an output signal thereof.

As a result, when the mode register circuit 5 is at the logic 11011, a 1-bit error is not reported to the central processing unit, but when the mode register circuit 5 is at the logic 1'111, it is immediately reported.

On the other hand, the 1-bit error counter circuit 3 counts the number of 1-bit errors instead of the central processing unit collecting memory status data every time a 1-bit error occurs. The count data 301 is then sent to the central processing unit through the gate circuit 6. In addition,
The 1-bit error counter circuit 3 is reset by the central processing unit.

By the way, the gate circuit 6 suppresses the count data 301 in response to an instruction signal 600 from the central processing unit. That is, it is used when the central processing unit needs count data, for example, when it wants to know the number of errors that have occurred at regular intervals.

However, if the 1 and error counter 3 overflows, the
Reported to central processing unit. This is because an overflow of the 1-bit error counter circuit 3 means that a large number of 1-bit errors have occurred in a short period of time, and there will be reliability problems in future operations. Therefore, in this case, it is possible to directly report to the central processing unit and take necessary measures such as disconnecting the memory.

In this way, this embodiment includes a memory error detection circuit that detects 1-bit errors and 2-bit errors in read data from an external memory circuit, and sends out a 1-bit error No. 15 or 2-bit error signal, and this memory An error correction circuit inputs the read data signal and 1-bit error signal sent from the error detection circuit, corrects the error or -lζ data, and sends correct data to the central processing unit, and the memory error detection circuit described in L. a 1-bit error counter circuit that counts up by +1 in response to the sent 1-bit error signal; and an error gate circuit that also gates the 1-bit error signal from the memory error detection circuit to suppress error reporting to the central processing unit; A 1-bit processor-report register circuit that controls the push-up signal to this error gate circuit and remotely sets whether or not to report an error to the central processing unit; and an error count gate circuit that suppresses the count signal by a gate signal from the central processing unit.

In addition, the present invention is not limited to extremely hypertrophy,
It includes various modifications within the scope of the gist. For example, in the above-described embodiment, various gates are provided to suppress signal transmission, but the combination of the silk and the like is arbitrary.

[Effects of the Invention] As explained above, even if a 1-bit error occurs in the read data of the memory circuit or 1':), the present invention does not report the 1-bit error to the central processing unit and can send an alternative. Since the number of 1-bit errors is counted, it is possible to omit the collection of status information, etc. that was not performed by the central processing unit when an error occurred, reducing overhead loss due to error handling operations. As a result, it is possible to provide a memory error monitoring circuit that can improve not only operability but also maintainability.

[Brief explanation of the drawing]

FIG. 1C is a block diagram of a memory error monitoring circuit according to an embodiment of the present invention. Camorillo I Each prisoner 1: Memory error detection circuit 2: Error correction circuit 3: l-bit error counter circuit 4: Error gate circuit 5: Mort register circuit 6: Gate circuit A 9: (Physical device 1

Claims (1)

[Claims] A memory error detection circuit that detects a 1-bit error in read data from memory and sends a 1-bit error signal when a 1-bit error is detected, and a 1-bit error in the read data sent from this memory error detection circuit. The error correction circuit that sends correct data based on the signal and the 1-bit error signal sent from the memory error detection circuit are input, and each information about the occurrence and counting of 1-bit errors and the overflow of the 1-bit error counter is input. A memory error monitoring circuit comprising: an error information reporting control circuit for controlling reporting.