JPS61103252A - Memory device for fault analysis - Google Patents

Abstract

PURPOSE:To reduce the fault analysis load and to secure satisfactory information when a fault occurs by adding a fault analyzing memory device to supply the fault information, etc. through an applied device of a microcomputer. CONSTITUTION:For a microcomputer application device 1, a fault detecting part 12, a main memory part 13, an input/output part 14 and a fault analyzing memory connection part 2 are connected to a CPU11 via an internal bus 16. The CPU1 is connected to the part 12 by an uninhibitable interruption signal (NMi) 17. Then the CPU11 usually executes programs in a normal mode of a control program, etc. on the part 13 and controls an external device D to be controlled via the part 14. If the part 12 detects such a fault as an abnormal parity, the time-up, out-of-area access, etc. while the CPU11 is executing a program, an interruption is applied to the CPU11 by the signal (NMi) 17. Thus the CPU11 knows the fault and executed a fault processing program.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] This invention is directed to a microcomputer application device that receives and stores information for failure analysis when a failure occurs from a microcomputer application device that is equipped with means for detecting the occurrence of a failure in itself. The present invention relates to a memory device for failure analysis.

[Conventional technology and its problems]

Conventionally, when a failure occurs in a microcomputer application device (hereinafter referred to as microcomputer application device), it is detected by hardware, and an interrupt is generated to the CPU to execute a pre-installed failure analysis program routine. Processing was performed from the beginning. But 1,
Many microcomputer-applied devices have limited display and output device capabilities due to miniaturization and low cost, and have the disadvantage of not being able to provide sufficient information necessary to analyze failure details. Particularly important is the process control device t1, which is a microcomputer-applied device. In this case, a long-term shutdown of the device will cause serious damage, so prompt recovery processing is necessary. Therefore, when a failure occurs, the control device must be immediately The disadvantage is that it is often reset, and sufficient information for failure analysis cannot be obtained.

On the other hand, the operation of ordinary microcomputer-applied equipment does not require sufficient knowledge of troubleshooting. Therefore, disability +14.
One drawback is that when a problem occurs, it is difficult to take appropriate countermeasures and analysis is performed based on incorrect failure information.

[Purpose of the invention]

This invention eliminates the above-mentioned drawbacks and provides a microcomputer-applied device capable of detecting the occurrence of its own failures. The present invention aims to provide a memory device for failure analysis that can reduce the load for failure analysis.

[Key points of the invention]

The main point of this invention is to provide a fault detection section and a memory connection section in a microcomputer application device, and to create a new memo that is read directly into the memory connection section. A fault analysis memory is connected through the J Tl1-fi section, and when a fault occurs, the IC is configured to write all the fault information in the microcomputer application device and the contents of the main memory to this fault analysis memory. If a failure occurs, the microcomputer application device will immediately
On this evening, processing started, and in addition to minimizing downtime, the failure analysis memory device sent the contents of the failure analysis memory to a failure analysis device such as a host computer for analysis. Note that this failure analysis memory is transmitted to the host computer via a public communication interface attached to the failure analysis memory device.

In other words, the main point of the present invention is that a microcomputer application device having a means for detecting the occurrence of a fault in itself (such as a fault detection section) and a means for sending out the fault information, etc. (such as a memory connection section for fault analysis), and a memory connection means (memory connection unit, etc.) for inputting data by inputting the fault information in the application device and the memory connection means when the fault occurs. Similarly, a reception storage means (fault analysis use (memory unit, etc.) and data output means for outputting predetermined storage contents in the reception storage means, or in other words, the data output means is equipped with a telephone number stored in the reception storage means. - From this, an auto-dial means (such as an auto-dial unit) that calls the fault analysis means via a subscriber telephone line, and the fault analysis means that calls out the fault information stored in the same manner and the data in the main storage unit. If the telephone number is set to a predetermined value (
NUL code, etc.), the above-mentioned transmission is not performed. The output is what you get, and that's the point.

[Embodiments of the invention]

The present invention will be described in detail below based on FIGS. 1 to 5-ζ. FIG. 1 is a block diagram showing the configuration of a memory device for failure analysis as an embodiment of the present invention, FIG. 2 is a diagram showing an example of the format of the information for failure analysis received by the device shown in FIG.
FIG. 3 is a block diagram showing a schematic configuration of a system to which an embodiment of the present invention is applied, FIG. 4 is a block diagram showing an example of the configuration of a microcomputer application device, and FIG. 5 is an error caused by the device shown in FIG. 3 is a flowchart showing an example of a processing program. In each figure, the same reference numerals indicate the same or corresponding parts.

In the system schematic diagram shown in FIG. 3, the microcomputer application device 1 is connected to a fault analysis memory device [3I] via a fault analysis memory connection section 2 provided inside the microcomputer application device 1. The failure analysis memory device 3 is connected to a host computer 5Iζ via a subscriber telephone line 4 as a failure analysis means.

In addition, in the microcomputer application device II shown in FIG.
A failure detection unit 12, a main storage unit 13, an input/output unit 14, and a failure analysis memory connection unit 2 are connected to each other via an internal bus 16. The CPU II and the failure detection section 12 are connected through a non-inhibitable interrupt signal (NMi) 17.

Normally, the CPU II executes a normal program (referred to as a regular program) such as a control program on the main memory section 13, and controls external devices 91, controlled devices, etc. via the input/output section 14. There is. CPU II.

When the failure detection unit 12 detects an abnormality such as a constant program being executed, a parity abnormality, a watchdog timer time increase, or an out-of-area access, a non-prohibitable interrupt signal 1 is generated.
7 causes an interrupt to the CPU II. When CPU II determines an abnormality based on this NMi signal 171, it executes an abnormality processing program as shown in FIG.

In other words, in step 101 in FIG. 5, the telephone number of the host computer 5, which has been stored in advance in the main storage unit 13 of the failure analysis memory device 3I, is sent via the failure analysis memory connection unit 2. do.

Next, in step 102Iζ, the contents of the abnormality information, for example, the abnormality number as a number representing the contents of the abnormality, the hardware status, the register, etc., are transferred to the memory device 3 via the memory connection section 2, and then in step 103
In this case, data necessary for fault analysis in the main memory section 13 (referred to as main memory data) is transferred. The fault analysis memory connection section 2 is composed of a part of the internal bus 16 and a simple circuit for driving those signals.

After the transfer to the failure analysis memory device 3 is completed, the CPU II performs abnormality processing specific to the device 1 in step 104+, such as stopping the CPU, notifying the operator of the abnormality, and continuing the execution of the program by re-initializing. etc.

FIG. 2 shows the format of data (referred to as failure analysis information 30) transferred from the microcomputer application device 1 to the failure analysis memory device 3 in this manner.

That is, the phone number 31 of the host computer 5 is added to the beginning, and the failure information 32. It is composed of main memory data 33.

Next 1 In the memory device 3 for failure analysis shown in Figure 1, C
The PU 21 connects the main storage unit 22°, the failure analysis memory unit 23. Auto dial unit 25° controls serial data transmitting unit 26. The memory connection unit 24 is connected to the failure analysis memory connection unit 2 of the microcomputer application device 1, receives the failure analysis information 30 shown in FIG. 2, and stores 1% of this information 3.
0 is stored in the failure analysis memory section 23#.

When the memory connection unit 24 detects the transfer of the failure analysis information 30 from the microcomputer application device 3, it notifies the CPU 21 by turning on the write detection signal 20. C.P.
The U 21 detects that the transfer of the information 30 is completed when the write detection signal 20 becomes 0FFtC, and starts communication processing to the host computer 5 based on the contents of the failure analysis memory section 23. The failure analysis memory unit 23 is configured as a so-called common memory, and the memory connection unit 24
and the CPU 21° via the internal bus 29.
The write detection signal 20 is used to control access to prevent collisions.

Furthermore, the failure analysis memory section 23 is protected against power outages caused by batteries, so that the failure analysis information 30 can be retained for a long period of time. The CPU 21 calls the auto dial section 2 from the telephone number 311 in the information 30.
5. Subscriber telephone line 4 via network control unit (NCU) 27
The host computer 5 connected to is called. The CPU 21 is connected to the host computer 5 through the subscriber telephone line 4I.
The contents of the fault analysis memory section 23 (fault information 32 and main memory data 334 are transmitted to the host computer 5 for fault analysis by a modem (MOL) EM connected via the serial data transmitting section 26).

In this manner, the host computer 5 can obtain more detailed fault information by analyzing the fault analysis information received from the fault analysis memory device 3.

In the present invention, in cases where the above-mentioned communication using a single-talk line is not necessary or impossible,
If the first telephone number is 31 or a NUL code, the call will not be made via telephone line 4. Further, in this case, the information for fault analysis Φ in the memory section 23 can be read directly from the host computer 5I via the memory connection section 24.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, apart from the microcomputer application device, when a failure occurs, failure information, etc. is transmitted from the microcomputer application device...
GA7't61'BM4@m l % 1 mFIl'
&Hm "61" configuration reduces the burden of failure analysis that must be performed by the microcomputer application device, and allows the microcomputer application device to obtain sufficient information for failure analysis. This failure analysis information is configured to be sent from the failure analysis memory device to the host computer, so that the cause of the failure can be quickly identified and the downtime of the microcomputer application equipment can be shortened. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a diagram showing an example of the format of failure analysis information received by the equipment in the IT diagram, Figure 3 is a block diagram showing an example of the overall schematic configuration of a system to which the present invention is applied, and Figure 4 is a microcomputer application. A block diagram showing an example of the configuration of the device,
Figure 5 is Figure 4! 70-chart illustrating the main part of the operation performed by the device. 1...Microcomputer application device (microcomputer application device), 2...Memory connection unit for fault analysis, 3...Memory device for fault analysis, 4...・
・Subscription telephone line 1 line, 5...Host computer, 11.21...CPU, □12...
...Fault detection unit, 13.22...Main storage unit, 14...Input/output unit, D...Controlled equipment, 16.29...・・Internal bus, 17・・・・
- Non-inhibitable interrupt signal (NMi). 20...Write detection signal, 23...Memory part for failure analysis% 24...Memory connection part,
25...Auto dial section, 26...
Serial data transmitter, 27...Network control device (
NCU), 28...modem (MODEM). 30...Fault analysis information, 31...Telephone number, 32...Fault information, 33...
Main memory data. Figure 23 tr -,'(3!”+ - Figure 5

Claims (1)

[Scope of Claims] 1) Memory connection means for inputting data via the sending means from a microcomputer application device having means for detecting the occurrence of a fault in itself and means for sending out fault information, etc.; When a failure occurs in the application device, a telephone serving as a failure analysis means analyzes failure information in the application device, data in the main storage unit, etc., and the contents of the failure in the application device based on the information and data, etc., via the memory connection means. 1. A failure analysis memory device comprising: reception storage means for receiving and storing a number; and data output means for outputting predetermined storage contents in the reception storage means. 2) In the failure analysis memory device according to claim 1, the data output means is an automatic system that calls the failure analysis means via a subscriber telephone line using the telephone number stored in the reception storage means. A memory device for fault analysis, characterized in that it is equipped with a dialing means and a transmitting means for transmitting the similarly stored fault information and data in the main storage unit to the called fault analysis means. 3) In the memory device for memory failure analysis according to claim 2, the data output means does not perform the transmission when the telephone number is a predetermined value. Memory device for failure analysis. 4) In the failure analysis memory device according to claims 1 to 3, the data output means is capable of outputting the storage contents in the reception storage means via the memory connection means. A memory device for failure analysis characterized by the following.