JP3070282B2 - Failure handling method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer fault handling system having a plurality of processors.

[0002]

2. Description of the Related Art A conventional fault handling system for a computer system of this type will be described with reference to FIGS.

FIG. 9 is a typical configuration example of a conventional computer system, and FIG. 10 is a flowchart showing an operation of a fault processing of the processors 903 and 904 in the conventional computer system.

In FIG. 9, reference numeral 901 denotes a diagnostic processing device;
Reference numerals 3 and 904 denote processors, 405 denotes a memory control device, 906 denotes an input / output processing device, and 907 denotes a main storage device. The diagnostic processing device 901 has a diagnostic interface 902 as a direct interface dedicated to diagnostic control between each device 903 to 907 in the computer system, and performs initialization processing, configuration control processing, and fault processing of each device in the computer system. Various controls are executed collectively.

The diagnostic interface 902 mainly has a function of notifying a failure from each device of the computer to the diagnostic processing device 901, a function of reading internal information of each device of the computer from the diagnostic processing device 901, and storing the information in a flip-flop of each device of the computer. It has a function of scanning out the obtained data and various instructions for various devices of the computer.

The diagnostic processing unit 901 uses the diagnostic interface 902 to perform fault processing for each device in the computer. A typical control procedure will be described with reference to a flowchart of FIG. FIG. 10 shows an operation of a failure process for a corresponding processor when a failure occurs in the processor.

First, upon receiving a failure notification from a processor (S101 in FIG. 10), the diagnostic processing unit 901 collects the content information of the relevant processor via the diagnostic interface 902 (S102). Next, a fault state in the processor is cleared (S103), and the processor is restored by restarting the processor from the instruction at the time of the fault occurrence (S104).

After executing the recovery processing of the processor, the diagnostic processing unit 901 confirms the normal operation of the processor (S
105). If it is normal, the recovery processing is successful, and the computer continues to operate (S106). If not,
The recovery processing has failed, and the diagnostic processing device 401 stops the operation of the corresponding processor (S107) and disconnects it from the configuration of the computer system (S108).

Next, the process of taking over the processor will be described. When the recovery process at the time of the processor failure has failed, and there is another normal processor, the diagnostic processing device 901 determines that the processor that has failed in the recovery can perform the process executed by the processor that has failed in recovery to another normal processor. Let it take over. The procedure first instructs a normal processor to stop the process currently being executed.

When the processing is stopped normally, since the internal information of the failed processor is collected before executing the recovery processing, the internal information necessary for taking over the processing is extracted from the information. And set this for a normal processor. Then, the normal processor is instructed to start the inherited processing. By this processor takeover processing, even when a failure occurs in one processor, the processing executed by that processor can be taken over by another normal processor.

[0011]

In the above-described conventional fault processing system, fault processing for a plurality of processors is concentrated in one diagnostic processing apparatus, and a memory used by software in the diagnostic processing apparatus. The load on software, such as the large expansion of the upper area and the complicated control, becomes extremely large .

According to the present invention, there is provided a failure processing method for a diagnostic processing apparatus for managing a failure of a computer having a plurality of processors, the method being started by a failure notification from the processor and having internal information of the processor. collection, recovery processing of the processor, and the notification of the diagnosis processor restoration processing results to, and row Upu Rose <br/> Tsu controlled means collectively by the control of firmware or software, the processor Receiving the notification from the control means, extracting the internal information of the processor stored in the processor control means, disconnecting the processor from the computer based on the result of the restoration processing, and performing the embedded configuration change control Diagnostic processor status management means , each processor control means
Are provided for the two processors,
When processor recovery processing fails when a server failure occurs
Suspends the processing being executed for the other normal processor.
Internal information collected from the failed processor
Extract the information necessary to continue the processing, and
Configuration in the failed processor.
The normal processing is passed to the normal processor,
The two processors controlled by processor control means
With respect to the processor without the control of the diagnostic processing unit.
It is possible to take over the sa .

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. In the figure, a diagnosis processing device 1 collectively manages failure processing of each device in a computer system. The diagnostic processing apparatus 1 includes n processor control units 30 to 3 (n-1) corresponding to the n processors 40 to 4 (n-1) configured in the computer system. The processor control means 30 to 3 (n-1) has a diagnostic interface 8 dedicated to diagnostic processing between the corresponding processors 40 to 4 (n-1). ３3 (n-1) is executed exclusively under the control of firmware or software. The state management means 9 controls the configuration of the processors in the computer system based on the result of the processor failure processing performed by the processor control means 30 to 3 (n-1). For simplicity, the description of the diagnostic interface between the memory control device 5, the main storage device 6, the input / output processing device 7, and the diagnostic processing device 1 is omitted.

FIG. 2 shows the diagnostic processing apparatus 1, the processor control means 30 to 3 (n-1) and the processor 40 shown in FIG.
6 shows details of an interface between the three parties to (4) (n-1) and a configuration inside the processor control device 3m.

Signal line 21 in diagnostic interface 8
Reference numeral 0 denotes a fault notification line from the processor 4m. When this signal becomes logic "1", the processor control unit 3m
The fault processing means 205 realized by the firmware or software in it is activated. Failure handling means 20
Reference numeral 5 uses the diagnostic interface 8 to extract information from the processor 4m and execute various controls on the processor 4m. The extracted internal information is temporarily stored in the memory 206.

On the other hand, the processor 4 m
Is made on the signal line 207, and the state management means 9 is activated. The state management means 9 recognizes the result of the failure processing in the processor control means 3m via the processor control interface 2. Further, data of the memory 206 in which the internal information of the processor 4m is stored can be read through the interface 2.

Hereinafter, the processor devices 40 to 40 according to the present invention will be described.
4 (n-1) will be described with reference to the flowcharts of FIGS. 3 and 4.

FIG. 3 shows a flow of control of the failure processing of the processor 4m in the processor control means 3m. First, when a failure occurs in the processor 4m, the processor control unit 3m receives a failure notification from the processor 4m.
Is notified of the failure. The processor control means 3m receives this failure notification and receives the failure notification means of the processor.
5 is started (S31 in FIG. 3).

In the fault processing means 205, first, the internal information at the time of the fault of the processor 4m is extracted via the diagnostic interface 8 and stored in the temporary memory 206 (S32). Next, the failure state of the processor 4m is cleared by a clear instruction via the diagnostic interface 8 (S33). Then, based on the extracted internal information, it is determined whether or not the failure occurring in the processor 4m can be recovered (S3).
4) If recovery is possible (S35), a recovery process is executed (S36). Typical restoration processing includes re-execution of a software instruction. In this recovery process, processor 4
If m operates normally, the recovery is determined to be successful (S37).
When the processor 4m does not operate normally even after performing the recovery processing, or when it is determined that the recovery processing cannot be performed, it is determined that the recovery has failed (S37).

After executing the fault processing, the processor control means 3m
Notifies the diagnostic processing device 1 via the signal line 207 that the processor 4m has failed (S38, S3).
9). The above is the control of the processor control unit 3m.

Next, the control in the diagnostic processing apparatus 1 is shown in FIG.
This will be described with reference to FIG. FIG. 4 shows the control by the processor status management means 9 of the diagnostic processing device 1 which has received the result of the fault processing from the processor control means 3m.

The state management means 9 sends a failure report to the signal line 20.
7 (S41 in FIG. 4), the result of the failure processing is read out from the processor control means 3m via the processor control interface 2, and the success / failure of the recovery processing is determined (S42). If successful, the operation of the computer system is continued as it is (S43). In the case of failure, the corresponding processor 4m is stopped (S44) and disconnected from the configuration of the computer system (S45). Then, regardless of the success / failure of the recovery processing, the processor control unit 3m
Of the processor 4m stored in the memory 206 is read out via the processor control interface 2.

As described above, the processors 40 to 4
When a fault occurs in (n-1), the fault processing is performed by the processor control means 30 to 3 (n-
The diagnostic processing device 1 only needs to recognize the failure processing result, collect the failure information, and control the configuration of the computer system based on the failure processing result. Diagnostic processing device 1
Can reduce the load of processing concentration.

FIG. 5 is a block diagram of a second embodiment of the present invention. In the figure, reference numerals 50 to 5 (n-1) denote processor control means for handling failure processing of two processors. The components other than the processor control means 50 to 5 (n-1) are as follows.
The components are the same as those in the first embodiment shown in FIG.

FIG. 6 shows processor control means 50 to 5.
(N-1) 1 single 5 m and the processor 4 of the (2M-
2) to 4 (2m-1) and the details of the interface between the three parties of the diagnostic processing apparatus 1 and the configuration within the processor control means 5m.

The processor control means 5m can execute fault processing for the two processors 4 (2m-2) and 4 (2m-1), and the processing procedure is as follows.

Signal line 21 in diagnostic interface 8
Reference numeral 0 denotes a failure notification line from the processor 4 (2m-1). When this signal becomes logic "1", the failure processing unit 600 in the processor control unit 5m is activated. The fault processing means 600 uses the diagnostic interface 8 to extract internal information of the processor 4 (2m-1) and execute various controls on the processor 4 (2m-1). The extracted internal information is temporarily stored in the memory 206.

Next, the processor takeover processing in the processor control means 5m will be described with reference to the flowchart of FIG. The fault processing means 600 is the processor 4 (2m-1)
Of the other processor 4 (2) under the control of the processor control unit 5m.
If m-2) is continued and normal, the failure processing means 600 determines that the processor takeover processing is possible, and
Activate the processor takeover means 601. The processor takeover unit 601 first instructs the other normal processor 4 (2m-2) connected to the processor control unit 5m to stop the currently executing process.

Next, from the internal information of the faulty processor collected from the faulty processor before the recovery processing and stored in the memory 206, information of software appearance necessary for taking over the processing is extracted, and this is extracted as the normal processor 4 ( 2m-1). And this normal processor 4 (2m-
Instruct 1) to start processing. In this manner, the two processors 4 (2m-1) and 4 (2m-1) under the processor control means 5m are not controlled by the control of the diagnostic processing apparatus 1.
The processor takeover process is performed between (2m−2), and only the success or failure of the recovery process from the failure and the execution result of the processor takeover process when the recovery process fails are reported to the diagnostic processing device 1.

According to the present embodiment, the processor takeover process between two processors can be executed without going through the processing of the diagnostic processing device, so that even if the number of processors in the computer system is increased, There is no need for the diagnostic processing device to directly carry out the handover process, and the effect of reducing the load due to the concentration of processing on the diagnostic processing device due to the increase in the number of processors can be obtained.

FIG. 8 is a block diagram showing a third embodiment of the present invention. In the figure, reference numeral 801 denotes a diagnostic processing device,
02 (n-1) is processor control means. 8030
Reference numeral 803 (n-1) denotes a failure processing result holding unit that holds the results of the processor recovery process and the processor takeover process, while the failure instruction signal 812 from the data transfer control unit 810 in the diagnostic processing device 801 is valid. , And flip-flops that sequentially shift the data to be stored one bit at a time in series.

The step instruction signal 812 is distributed to all the processor control means 8020 to 802 (n-1), and while this signal is at logic "1", all the processor control means 8020 to 802 (n The failure processing result holding means 8030 to 803 (n-1) in -1) step by one bit and execute the diagnostic processing device 80 via the serial interface 811.
The bits are sequentially transferred one by one toward 1. For example, the data in the processor control means 802 (n-1) is transmitted via the serial interface 811 to the processor control means 802 (n-1).
(N-1) → 802 (n-2) → ... → 8021 → 8
020 → transferred to the diagnosis processing device 801. On the other hand, the diagnostic processing device 801 converts this into the shift register 804 (n-
1) → 804 (n−2) → ・ ・ ・ → 8041 → 8040
And is sequentially received one bit after another.

Here, the state management means 808 holds the configuration states of the processors configured in the computer system in the configuration information control means 8090 to 809 (n-1). For example, if one processor is configured in a computer system, the configuration corresponding to that processor
The value of the information control means 8091 becomes logic "1". Configuration information
When the output of the information control means 8091 is logic "1", the switching circuit 8071 selects the output from the shift register 8041. Data corresponding to all processors configured by this control is stored in the shift register 804m corresponding to each processor.

Data transfer control means 810 sets stepping instruction signal 812 to logic "0" when all data transfer is completed.
At this timing, the configuration information control means 8090 to 809
The contents of the shift register 804 corresponding to the processor whose output is logic “1” in (n−1) are converted into the data register 805 by the set signal of the output of the AND gate 806.
m.

The state management means 808 fetches the contents of the data register 805, recognizes which processor has a failure, recognizes the result of the failure processing by the processor control means, and executes the state management control as a computer system.

According to the present embodiment, various kinds of information in the processor control means are stored in one processor by connecting all the processor control means in series.
Providing a serial interface that serially extracts bits one by one has the effect of avoiding concentration of interface cable connection to the diagnostic processing device due to an increase in the number of processors, and of reducing the size of the diagnostic processing device.

[0037]

As described above, according to the fault handling system of the present invention, the processor control means for executing fault handling of the processor unit at a time and notifying the diagnostic processing device only of the result of the fault handling is provided by the processor. By providing in units,
Even when the number of processors in the computer system is increased, the processor reads out the internal information of the processor collected by the processor control unit from the processor control unit when a failure occurs in the processor, and manages the configuration state of the plurality of processors in the system. Only, it is possible to reduce the load due to processing concentration on the diagnostic processing device due to the increase in the number of processors.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a detailed block diagram of the first embodiment.

FIG. 3 is a flowchart of a failure process by a processor control unit according to the first embodiment.

FIG. 4 is a flowchart of a failure process in the diagnostic processing device according to the first embodiment.

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a detailed block diagram of a second embodiment.

FIG. 7 is a flowchart of a processor takeover process by a processor control unit according to the second embodiment.

FIG. 8 is a block diagram of a third embodiment of the present invention.

FIG. 9 is a block diagram showing an example of the related art.

FIG. 10 is a flowchart of a failure process by a processor in a conventional example.

[Explanation of symbols]

1,801,901 Diagnosis processing device 2 Processor control interface 30-3 (n-1), 3m, 50-5 (2n-1), 5
m, 8020-802 (n-1) Processor control means 40-4 (2n-1), 4m, 4 (2m-2), 4 (2
m-1) , 903,904 processor 5,905 memory control device 6,907 main storage device 7,906 input / output processing device 8,902 diagnostic interface 9,808 state management means 205,600 failure processing means 206 memory 601 processor Takeover means 8030 to 803 (n-1) Failure processing result holding means 8040 to 804 (n-1) Shift register 8050 to 805 (n-1) Data register 8060 to 806 (n-1) AND gate 8071 to 807 (n -1) Switching circuits 8090 to 809 (n-1) Configuration information control means 810 Data transfer control means 811 Serial interface

Claims (2)

(57) [Claims] 1. A computer having a plurality of processors.
The fault handling method used in the diagnostic processing device
And activated by a failure notification from the processor,
Collection of internal information of the processor, recovery of the processor
Old processing and communication of restoration processing results to the diagnostic processing unit
Knowledge is controlled by firmware or software
Processor control means for performing collective processing and processor control
Receiving the notification from the means and storing it in the processor control means.
Fetching the stored internal information of the processor,
The program from the computer based on the result of the restoration process
Before disconnecting the processor and performing built-in configuration change control
A state management unit of the diagnosis processing device, wherein each of the processor control units is provided for two of the processors, and when a processor recovery process fails when a processor failure occurs, the other normal processor By instructing the processor to stop the process being executed, extracting information necessary for processing continuation from the internal information collected from the failed processor and setting the information in the normal processor, the execution by the failed processor is executed. The normal processing is transferred to the normal processor, and the processor 2 is controlled by the processor control means.
Base of the diagnosis processor takeover not through the control of the processing unit is disabled you wherein the possible <br/> harm processing method with respect to the processor. 2. A failure processing method in a diagnostic processing device for performing failure processing of a computer having a plurality of processors, the diagnostic processing apparatus being activated by a failure notification from the processor,
A processor control unit that collectively collects internal information of the processor, performs a restoration process of the processor, and notifies a result of the restoration process to the diagnostic processing device under the control of firmware or software; and The diagnostic processing apparatus that receives the notification of the above, extracts the internal information of the processor stored in the processor control unit, disconnects the processor from the computer based on the result of the recovery processing, and controls the configuration change of the built-in processor State management means, the processor control means, the processor failure recovery processing result,
Holds various information such as a processor takeover processing result, and holds a failure processing result composed of serially connected flip-flops that sequentially shifts stored data by one bit at a time according to a step instruction from the diagnostic processing device. Means, the plurality of failure processing result holding means are connected in series,
A serial interface unit for sequentially shifting the contents of all the fault processing result holding means by one bit and transferring the serial data to the diagnostic processing device in series while the step instruction from the diagnostic processing device is valid; The state management means holds the configuration information of the processor, and the diagnostic processing device sequentially receives the failure processing result information transferred by the serial interface means one bit at a time while the step instruction is valid. Te, the data receiving means of the diagnostic processing device capturing the contents of the fault processing result holding means corresponding to said processor configured in a computer system based on the processor configuration information managed by said state managing means, the total While the contents of the failure processing result holding means are serially transferred one bit at a time, the stepping instruction is valid, and the stepping instruction is output periodically. To include a data transfer control unit by the series interface means, the total processor control unit of the fault processing result failure processing method, wherein the periodic recognizable to.