JPS54147743A - Transmission system for error information - Google Patents

Transmission system for error information

Info

Publication number
JPS54147743A
JPS54147743A JP5579378A JP5579378A JPS54147743A JP S54147743 A JPS54147743 A JP S54147743A JP 5579378 A JP5579378 A JP 5579378A JP 5579378 A JP5579378 A JP 5579378A JP S54147743 A JPS54147743 A JP S54147743A
Authority
JP
Japan
Prior art keywords
error
signal
information
control unit
detects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5579378A
Other languages
Japanese (ja)
Inventor
Shigeharu Hasu
Hiroshi Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5579378A priority Critical patent/JPS54147743A/en
Publication of JPS54147743A publication Critical patent/JPS54147743A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To detect the content of error at the controlled unit and to eanble to perform retrial surely, by stopping the unit and feeding the error detection signal to the control unit and the information relating to the error to the data signal line, when the controlled unit detects an error.
CONSTITUTION: The data from the control unit is received at the data reception section 11, and it is inspected at the error inspection circuit 12 and the information relating to the error is stored in the error information register (EL) 14. On the other hand, the operation signal from the control unit is detected at the operation signal detection section 13, and this detection signal is inputted to EL 14. When the circuit 12 detects the error at the circuit 12, the error detection signal ER is continued to be fed to the signal line 5 and the information ED relating to the error is to the data signal line 3. When the control unit receives the signal ER, the data transmission is stopped, and after a given time elapsed, the information ED is read out and the level of the operation signal is lowered. The detection section 13 detects it to reset EL14 and to stop the signal ER and the information ED . The detection section 13 detects this, resets EL14 and stops the signal ER and the information ED. In the controlled unit, the condition is returned from stop to operation, and the control unit detects the content of error from the information and ensures the retrial.
COPYRIGHT: (C)1979,JPO&Japio
JP5579378A 1978-05-11 1978-05-11 Transmission system for error information Pending JPS54147743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5579378A JPS54147743A (en) 1978-05-11 1978-05-11 Transmission system for error information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5579378A JPS54147743A (en) 1978-05-11 1978-05-11 Transmission system for error information

Publications (1)

Publication Number Publication Date
JPS54147743A true JPS54147743A (en) 1979-11-19

Family

ID=13008782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5579378A Pending JPS54147743A (en) 1978-05-11 1978-05-11 Transmission system for error information

Country Status (1)

Country Link
JP (1) JPS54147743A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103252A (en) * 1984-10-26 1986-05-21 Fuji Electric Co Ltd Memory device for fault analysis
JPH02129727A (en) * 1988-11-10 1990-05-17 Masaru Kiregawa Error collecting method for sort processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949363A (en) * 1972-09-14 1974-05-13
JPS5164339A (en) * 1974-12-02 1976-06-03 Fujitsu Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949363A (en) * 1972-09-14 1974-05-13
JPS5164339A (en) * 1974-12-02 1976-06-03 Fujitsu Ltd

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103252A (en) * 1984-10-26 1986-05-21 Fuji Electric Co Ltd Memory device for fault analysis
JPH02129727A (en) * 1988-11-10 1990-05-17 Masaru Kiregawa Error collecting method for sort processor

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