JPH0271283U - - Google Patents

Info

Publication number
JPH0271283U
JPH0271283U JP15150888U JP15150888U JPH0271283U JP H0271283 U JPH0271283 U JP H0271283U JP 15150888 U JP15150888 U JP 15150888U JP 15150888 U JP15150888 U JP 15150888U JP H0271283 U JPH0271283 U JP H0271283U
Authority
JP
Japan
Prior art keywords
data transfer
antenna element
transfer circuit
phased array
radar device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15150888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15150888U priority Critical patent/JPH0271283U/ja
Publication of JPH0271283U publication Critical patent/JPH0271283U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示すブロツク図
、第2図は従来のフエーズド・アレー・レーダ装
置を示すブロツク図、第3図はアンテナ素子へ伝
送する時間的に直列なデイジタル信号を示す図で
ある。 図において、1は第1のアンテナ素子、2はデ
ータ転送回路、3は第2のアンテナ素子、4は第
3のアンテナ素子、5はアドレス・メモリ、6は
制御メモリ、7は伝送路、8はコネクタ、9はア
ドレス・データ、10は制御データ、11は並列
伝送路、12はアドレスを固定したデータ転送回
路である。なお、各図中同一符号は同一または相
当部分を示す。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a block diagram showing a conventional phased array radar device, and Fig. 3 shows a temporally serial digital signal transmitted to an antenna element. It is a diagram. In the figure, 1 is a first antenna element, 2 is a data transfer circuit, 3 is a second antenna element, 4 is a third antenna element, 5 is an address memory, 6 is a control memory, 7 is a transmission line, and 8 1 is a connector, 9 is address data, 10 is control data, 11 is a parallel transmission line, and 12 is a data transfer circuit with a fixed address. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数個のアンテナ素子を配列してそれぞれのア
ンテナ素子の位相量を制御し、合成された空中線
ビームを任意の方向に指向するフエーズド・アレ
ー・レーダ装置において、アンテナ素子単体を構
成するデータ転送回路をアンテナ素子から分割し
てアドレスを固定し、このデータ転送回路とアン
テナ素子との間を任意に接続及び分離できるよう
にし、かつ、データ転送回路の相互間を信号の伝
送路に対して並列に接続したことを特徴とするフ
エーズド・アレー・レーダ装置。
In a phased array radar device that arranges multiple antenna elements, controls the phase amount of each antenna element, and directs the combined antenna beam in an arbitrary direction, the data transfer circuit that constitutes a single antenna element is used. The data transfer circuit is divided from the antenna element, the address is fixed, and the data transfer circuit and the antenna element can be arbitrarily connected and separated, and the data transfer circuits are connected in parallel to the signal transmission path. A phased array radar device that is characterized by:
JP15150888U 1988-11-21 1988-11-21 Pending JPH0271283U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15150888U JPH0271283U (en) 1988-11-21 1988-11-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15150888U JPH0271283U (en) 1988-11-21 1988-11-21

Publications (1)

Publication Number Publication Date
JPH0271283U true JPH0271283U (en) 1990-05-30

Family

ID=31425616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15150888U Pending JPH0271283U (en) 1988-11-21 1988-11-21

Country Status (1)

Country Link
JP (1) JPH0271283U (en)

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