JPH0270441U - - Google Patents
Info
- Publication number
- JPH0270441U JPH0270441U JP15024188U JP15024188U JPH0270441U JP H0270441 U JPH0270441 U JP H0270441U JP 15024188 U JP15024188 U JP 15024188U JP 15024188 U JP15024188 U JP 15024188U JP H0270441 U JPH0270441 U JP H0270441U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- contact block
- measurement
- attached
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005259 measurement Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図ａ，ｂは本考案の一実施例の平面図及び
断面図、第２図ａ，ｂは従来のＩＣの測定治具の
一例の平面図及び断面図である。
１……基板、２……コンタクトブロツク、３…
…ポゴピン、４……位置決めピン、５……ポゴピ
ンソケツト、６……配線、７……コンデンサ、８
……絶縁被覆導線、９……絶縁層、１０……ポリ
イミド管、１２……テスター端子。
1A and 1B are a plan view and a sectional view of an embodiment of the present invention, and FIGS. 2A and 2B are a plan view and a sectional view of an example of a conventional IC measuring jig. 1... Board, 2... Contact block, 3...
... Pogo pin, 4 ... Positioning pin, 5 ... Pogo pin socket, 6 ... Wiring, 7 ... Capacitor, 8
...Insulated conductor wire, 9...Insulating layer, 10...Polyimide tube, 12...Tester terminal.
Claims (1)
クと、前記コンタクトブロツクに電気的に絶縁さ
れて取付けられ被測定半導体集積回路の端子に接
触するための測定用ピンと、前記コンタクトブロ
ツクの上面に絶縁層を介して形成されかつ一端が
前記測定用ピンに電気的に接続する配線とを含む
ことを特徴とする半導体集積回路用測定治具。 A contact block made of a conductive material is attached to a substrate, a measurement pin is attached to the contact block in an electrically insulated manner for contacting a terminal of a semiconductor integrated circuit to be measured, and an insulating layer is provided on the upper surface of the contact block. 1. A measurement jig for a semiconductor integrated circuit, characterized in that the measurement jig includes a wiring formed of a semiconductor integrated circuit and having one end electrically connected to the measurement pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024188U JPH0270441U (en) | 1988-11-17 | 1988-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024188U JPH0270441U (en) | 1988-11-17 | 1988-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0270441U true JPH0270441U (en) | 1990-05-29 |
Family
ID=31423207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15024188U Pending JPH0270441U (en) | 1988-11-17 | 1988-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0270441U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113443U (en) * | 1991-03-19 | 1992-10-05 | 安藤電気株式会社 | Probe overload prevention mechanism |
-
1988
- 1988-11-17 JP JP15024188U patent/JPH0270441U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113443U (en) * | 1991-03-19 | 1992-10-05 | 安藤電気株式会社 | Probe overload prevention mechanism |