JPH0270234A - Reactive power compensator - Google Patents

Abstract

PURPOSE:To stabilize a power system while preventing overload of a transformer by providing a limiter for limiting the output current from a reactive power compensator below a current level for causing overload of the transformer. CONSTITUTION:A voltage detecting circuit 7 and a current detecting circuit 10 detect the system voltage V and the output current are Isvc from a reactive power compensator (SVC) respectively, then an operating unit 9-2 takes the difference between the difference V of a set voltage Vref and the system voltage V and the output current Isvc multiplied by a constant K, thereafter a command for bringing the difference to zero is fed through a proportional integrator 12 to a firing angle determining circuit 13 thus controlling the SVC. If the detected current exceeds over the allowable load of transformer, an output for cancelling the excessive portion is provided from a negative value pass circuit 17 or a positive value pass circuit 18 and added to the output from the proportional integrator 12 through primary delays 19-1, 19-2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a reactive power compensator used for stabilizing a power system.

(Prior art) A reactive power compensator (hereinafter referred to as SVC) is a reactive power supply device that uses semiconductor switches such as thyristors to stabilize the voltage of the power system and improve its stability by adjusting its output amount. It is something.

Figure 3 shows an SVC that combines a thyristor-controlled reactor (hereinafter referred to as TCR) and a capacitor, which is an example of an SVC configuration.
An example of a configuration of a VC and a conventional control device is shown.

First, the configuration will be explained.

1-1.1-2 is a thyristor, 2 is a reactor, 3 is a capacitor, 4 is a transformer, 5 is a potential transformer (hereinafter referred to as PT), and 6 is a potential current transformer (hereinafter referred to as CT). be.

Next, 7 is a voltage detection circuit for measuring the system voltage, 8 is a reference voltage setter, 9-1.9-2 is a subtracter, and 10 is Sv
In the current detection circuit that detects the output current of C, the leading current is negative,
The lagging current is output as positive. 11 is a proportional circuit, 12 is a proportional-integral circuit with a limiter (hereinafter referred to as PI circuit), and 13 is a point of thyristor 1-1.1-2 from which TCR current (ITCR), which is the output of PI circuit 12, is output. A firing angle determining circuit 14 determines the firing angle α, and 14 is a thyristor 1-1.1-2 that is configured to set the firing angle α without being synchronized with the grid voltage.
This is a gate pulse generation circuit (hereinafter referred to as a PG circuit) that generates a gate pulse to the PG circuit.

Next, its effect will be explained.

The grid voltage (2) is detected by the PT 5 and the voltage detection circuit 7 connected to the power grid, and the error voltage ΔV, which is the difference between it and the reference voltage Vrer indicated by the reference voltage setter 8, is detected by the subtracter 9-1.

Next, the output current l5 of the SVC is determined by CT6 and the current detection circuit 10.
KS・l5vc where VO is detected and multiplied by Ks in the proportional circuit
Which error voltage △V is the difference between (△V- to -Isvc)
is taken by the reducer 9-2 and then input to the PI circuit 12. The PI circuit 12 outputs a TCR current ITOR such that ΔV-K·l5vc becomes zero. The firing angle determination circuit 13 determines the firing angle α such that the TCR outputs this one OR, and the next PG circuit 14 outputs a gate pulse with the firing angle α to the thyristor 1-1.1-2. TCR supplies the same current as ITOR indicated by P1 circuit 12 to the power system.

Figure 4 shows the SVC created by the control device in this way.
This is an example of voltage-current characteristics (hereinafter referred to as V-1 characteristics) of .

'lIl axis is grid voltage V, horizontal axis is SVC output current l5
VC is shown. Here, the Vi characteristics shown by the solid line O-■-■-○ are when the reference voltage ■ref is set to 0.9 pu, and the V-1 characteristics shown by the dashed-dotted lines O-0 to ■-■ are when the reference voltage Vref is set to 0.9pu. This is the case when the value is set to 1.1 pLI. The magnitude of the slope of -0 and 0-[F] is determined by the gain Ks of the proportional circuit 110.

(Problem to be solved by the invention) Here, transformer 4 temporarily advances the current that causes overload (-)
, and the delay (+) current are both 1pu, the reference voltage Vrer
If the voltage is set as low as 0.9 pu, even at a normal voltage such as the 0 point, the SvC will output a large amount of delayed current and the transformer will be overloaded. On the other hand, if you set the reference voltage Vref = 1.1 pu to a higher value, it will try to output the maximum current even at a fairly high voltage such as the 0 point, so the higher the voltage, the larger the current will be, which is bad for the transformer. becomes overloaded.

The purpose of the present invention is to prevent the SVC from being disconnected from the grid to prevent overloading of the transformer.
The output of C<,! ``The object of the present invention is to provide an SVC having an overload prevention circuit that prevents overload of the transformer while still being connected to the grid and contributing to the stabilization of the grid.

(Structure of the Invention) (Means for Solving the Problems) The means for structuring the present invention is to provide an overload prevention limiter to the SVC so that the output current of the SVC does not exceed a current value at which the transformer is overloaded. is included in the output current control circuit.

(Function) The function of the present invention is that the overload prevention limiter limits the output current of the SVC so that the output current of the SVC does not exceed the overload current of the transformer.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, and the portion surrounded by dotted lines corresponds to the portion of the present invention, which is added to the conventional example shown in FIG. 3.

Items with the same numbers as those used in the conventional example have the same functions. 9-3.9-4.9-5, 9-6 is a subtracter, 1
5 is a setting device that indicates the overload value of the lead current of the transformer 4, for example, +1. Indicates Opu. Reference numeral 16 denotes a setting device indicating the overload ratio of the lagging current of the transformer 4, which indicates, for example, +1.0 pu. 17
is a negative value passing circuit that allows only negative values to pass in order to prevent the limiter from being limited by J: when the output current of SvC is not greater than -1, Opu. 18 is SV
The output current of C is delayed +1. If the value is not more than OPU, there is a positive value passing circuit that allows only the positive value of the medallion to pass so as not to be limited by the limiter.

19-1 and 19-2 are first-order delay circuits with a gain K and a time constant T. 19-1. The reason why 19-2 is a first-order lag circuit is that the overload curve of the transformer is such that if the current flowing into the transformer exceeds +1 pu, which is not indicated by the setting device 15.16, the transformer will be immediately destroyed. This is because they can withstand large currents for short periods of time rather than for long periods of time. First-order delay circuit 19-1.19-
The gain of 2 and the time constant are chosen to suit the overload curve of the transformer.

The operation of this embodiment will be explained, but the parts explained in the conventional example will be omitted.

V-1 characteristic (0
−0−[F]−■), the leading current at 0 point−
1.1 pu, the limit of the lead current of transformer 4 is -1°O
It exceeds pu. This is because the current detection circuit 10 detects -1, lpu in FIG. The difference between -1,0pu indicated by the setter 15 and the subtractor 9-3 is taken, and -o,ipu
is calculated.

After passing through the next negative value passing circuit 17, the first-order lag circuit 19-1
is input. When the gain K of the first-order lag circuit 19-1 is large, the effect of the limiter is large. In other words, the SVC output current is immediately set to a leading current of -1, Opu or less.

In this explanation, it is assumed that ni=1.0.

At point 0 in FIG. 4, the output of the P1 circuit 12 is O, which is the ITOR that the TCR should output, but when the current that the TCR should output becomes O, the lead current output from the capacitor 3 is the overload value of the transformer 4. Oru - 1.0 pu more o, ipu is too much to bear. Therefore, since the first-order delay circuit 19-1 temporarily sets = 1.0, its output becomes -0,
14 is output and the subtracter 9-5 outputs the output of the P1 circuit 12 op.
The output -0, 19u of the first-order lag circuit 19-1 is added to u with the polarity inverted, and the output of the subtracter 9-5 becomes 0.1 pu. On the other hand, since the negative input of the subtracter 19-2 is O for the following reason, the output of the subtracter 9-6 is +0.1 pu. The input of the subtractor 9-4 is -1,lpu, and when the difference from i, Opu indicated by the setter 16 is taken, -2,1p1. However, the output of the positive value passing circuit 18 is the first-order lag circuit 1 due to O.
The output of 9-2 is O. As explained earlier, the output of the subtracter 9-6 is +〇, lpu, so the TCR outputs a delayed current of 0.1pu, and together with the output current of the capacitor 3 -1.1pu, the output of the SVC. The horn current is −
1,0ptj, and the transformer 4 is not overloaded. Even if the gain K of the first-order lag circuit 19-1 is 1 or more, the lead current will not become smaller than -1, Opu.

The larger the gain K is, the faster the limiter effect becomes.

Next, the case where the output current of SvC is equal to or greater than delay+i, opu will be explained.

In the V-I characteristic shown in Figure 4, if the overload prevention limiter
If there is no point [F] on the board and +1.1Pυ, this is the limit of transformer 4. +1. It goes beyond Opu.

In this case, the current detection circuit 10 of the SVC control circuit in FIG. 1 detects +1.1 pU.

Next, +1 indicated by the setting device 16. The difference from Opu is the subtractor 9-
4 is calculated and +〇, 1pu is output. Next, the SVC output current lags +1. The signal passes through the positive value pass circuit 18, which has a limiter effect only when it is equal to or greater than Opu, and is input to the first-order lag circuit 19-2.

Assuming that the gain of this first-order lag circuit 19-2 is 1, O
Then, the output becomes +0.1 pu after a while.

On the other hand, the negative side input of the first-order lag circuit 19-1 is O for the following reason. Since the output of the current detection circuit 10 is +1.1 pu, the output of the subtracter 9-3 is +2.1 pu by subtraction with -1 and Opu indicated by the setter 15, but the output of the negative value passing circuit 17 is 01. The output of the first-order delay circuit 19-1 is O. Therefore, the output of the subtracter 9-6 is the P1 circuit 12.
It is the value obtained by subtracting the output of the first-order lag circuit 19-2 from the output of the first-order delay circuit 19-2. The output of the PI circuit 12 indicates an output current of 1.1 pu at point [F], which is the limiter upper limit of the PI circuit.

The difference between the output of the first-order lag circuit 19-2 and 1 pLl is taken by the subtracter 9-6, and the output current of the SVC is +1. The TCR current that becomes Opu is output from the subtracter 9-6. osvc
If the output current becomes delay +i, opu, no overload current will occur for the transformer 4.

As explained above, if this embodiment is used, the transformer becomes SV
It is possible to avoid a situation where the SVC is overloaded by the output current of C and the SVC is disconnected from the grid.

FIG. 2 is a diagram showing another embodiment of the present invention.

Components having the same numbers as those used in the conventional example and FIG. 1 have the same functions.

20-1.20-2 is an integrator.

Suppose that the output current of SvC advances at the 0 point in Figure 4 by -1,1.
If it is pu, the difference between -1 and Opu indicated by the setter 15 is taken by the subtractor 9-3, and the output is 10.1 pu. The integrator 20-1 integrates the output -0, 1 plJ as input. Since the output of the integrator 20-1 is negative, the negative value passing circuit 1
7 and its output is added to the output of the PI circuit 12 with its polarity inverted in a subtracter 9-5. P1 at 0 points
The output of the circuit 12 is trying to bring the TCR current to O, but since the output of the negative value passing circuit 17 is added with the polarity reversed by the subtracter 9-5, the CR current is increased. The effect of the integrator 20-1 continues until the SVC current advances and becomes less than -1.0 pu.

Next, the SVC output current lags +1. A case where the number is equal to or larger than Opu will be explained. Assuming that the SVC output current is [
F] point, the output of the current detection circuit 10 is +1.1 pu
It is necessary. 1 indicated by the setting device 16. Subtractor 9 for the difference with Opu
-4, the output will be 10, lpu. The integrator 20-2 integrates this as input. Since the output of the integrator 20-2 is a positive value, it passes through the positive value passing circuit 18 and is sent to the subtracter 9.
-6. In the subtracter 9-6, a positive value passing circuit 18
The output of works in the direction of decreasing the TCP current.

This continues until the SVC output current falls below +1.0 pu.

(Effects of the Invention) As explained above, by using the present invention, the SVC can supply reactive power to the grid while preventing the overload of the transformer due to the output current of the SVC, thereby contributing to the stabilization of the power grid.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, Fig. 3 is a block diagram of a conventional device, and Fig. 4 is a voltage diagram of the conventional device. - It is a current characteristic diagram. 1-1.1-2...thyristor, 2...1 noactor, 3...capacitor, 4...transformer, 5...instrument transformer, 6...instrument current transformer , 7... Voltage detection circuit, 8... Reference voltage setter, 9-1 to 9-6... Subtractor, 10... Current detection circuit, 1... Proportional circuit, 2... Proportional integral circuit with limiter, 3... Firing angle determining circuit, 4... Gate pulse generation circuit, 5.16... Setting device, 17... Negative value passing circuit, 8... Positive value passing Circuit, 19-1.19-2...1st order lag circuit. Agent: Patent Attorney: Nori Chika, Kenichi Daishimaru

Claims (1)

[Claims] In a reactive power compensator connected to a power grid via a transformer, overload prevention imposes a limit on the output of the reactive power compensator so that the transformer is not overloaded by the output of the reactive power compensator. A reactive power compensator characterized by comprising a limiter.