JPH0268966A - Field effect type semiconductor - Google Patents

Abstract

PURPOSE:To improve amount of breakdown resistance and a device which is hard to damage due to overload by providing a buffer layer which is formed between the bottom surface of a third semiconductor area and a second semiconductor area and reduces injection efficiency of a carrier between second and third semiconductor areas. CONSTITUTION:It has a first conductive type first semiconductor area 1, a second conductive type second semiconductor area 2 formed within the surface of the first semiconductor area 1, a first conductive type third semiconductor area 3 formed within the surface of the second semiconductor area 2, a buffer layer 10 which is formed between the bottom surface of the third semiconductor area 3 and the second semiconductor area 2 and reduces injection efficiency of a carrier between the second and third semiconductor areas 2 and 3, a gate insullation film 5 which is formed on the surface of the second semiconductor area 2 between the first semiconductor area 1 and the third semiconductor area 3, a gate electrode 6 formed on the gate insulation film 5, and an electrode 7 formed on the surface of the third semiconductor are 3 and on the surface of the second semiconductor area 2. For example, the above buffer layer 10 is the oxidation layer 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a field effect semiconductor device, and particularly to an improved structure for improving its breakdown resistance.

[Prior Art] FIG. 5 is a plan view showing the surface of a plurality of basic MOS unit cells formed in a polygonal shape of a conventional n-channel power MO8FET. In addition, Fig. 6 shows the I-I shown in Fig. 5.
It is a sectional view of a line part.

In FIG. 6, an n-type drain region 1b is formed on the n-type drain region 1a. n-type drain region 1b
A plurality of p-type semiconductor regions 2 are selectively formed separately within the surface of the semiconductor device. The p-type semiconductor region 2 generally has a polygonal shape on the surface shown in FIG. 5, and here it has a rectangular shape.

In the surface of the p-type semiconductor region 2 and along its periphery, an n-
An n+ type source region 3 is selectively formed in an annular shape at substantially constant intervals from the type drain region 1b. This annular n+ type source region 3 and n- type drain region [p between 1b
Shaped semiconductor Jfj! The vicinity of the surface of 2 is defined as a channel forming region 4. Further, a gate insulating film 5 is formed on the channel forming region 4 in common for each block. A gate electrode 6 is formed thereon. Furthermore, the source electrode 7 is connected to the ρ-type semiconductor region 2
It is formed in common in each block so that the central surface of the n+ type source region 3 and a part of the surface of the n+ type source region 3 are short-circuited. Gate electrode 6 and source electrode 7 are insulated and separated by interlayer insulating film 8 . In addition, the drain electrode 9 is an n+ type drain region 1.
a Formed on the back side.

Next, the operation will be explained. In the conventional power MO8FET shown in FIG.
and the drain voltage V. Apply 8. Further, when a gate voltage vGS is applied between the gate electrode 6 and the source electrode 7, a channel is formed in the channel forming region 4, and a drain current 1 flows between the drain electrode 9 and the source electrode 7 through this channel. This drain current I.

is controlled by the gate voltage vGS. Note that the potential of the channel forming region 4 is determined by short-circuiting the central surface of the p-type semiconductor region 2 and a partial surface of the n+-type source region 3 through a source electrode 7.

Next, the destruction mode of this power MO3FET will be explained. Figure 7 shows a power MO8FE constructed by arranging a plurality of basic MOS unit cells shown in Figure 6 adjacent to each other.
It is a graph showing the output characteristics of T. The horizontal axis is the drain voltage V. 8. The vertical axis is the drain current 19, and the parameter is the gate voltage ■. , is. The train voltage V is the breakdown voltage V
. S reaches S and the drain current I. increases rapidly and the power MO8FE
Tu enters into camp. Breakdown current J in power MO3FET
. When exposed to water, this device has a tendency to destroy instantly.

FIGS. 8(a) and 8(b) are a cross-sectional view of a schematic configuration of a basic MOS unit cell portion and a connection diagram showing several circuits thereof. As shown in FIG. 8(a), in the p-type semiconductor region 2, there is an internal resistance R1 along the depth direction of each n+ type source region 3, and an internal resistance R1 along the bottom surface of each n+ type source region 3. A resistor R3 is present.

As shown in FIG. 8(b), these are p-type semiconductor regions 1j
12, it is expressed as a composite internal resistance R2 along the depth direction of the n+ type source region 3 and an internal resistance R3 along the bottom surface of each n+ type source region 3. This internal resistance R8 becomes the base resistance of the strange transistor T consisting of the n-type source region 1b, the p-type semiconductor region [2, and the n-type source region [3]. Also, n-type drain region 11
b and the p-type semiconductor region 2 form a diode D.

The drain voltage VD8 applied between the source electrode 7 and the drain electrode 9 is increased, and when it reaches the breakdown voltage of the diode D formed by the n-type drain region 1b and the p-type semiconductor region 2, the drain voltage VD8 applied between the source electrode 7 and the drain electrode 9 is increased. As shown by the arrow in figure (a), the breakdown current is J. flows. Breakdown current J. flows into the bottom surface of the n+ type source region 3, the base potential of the parasitic transistor T increases. The condition for this parasitic transistor T to be conductive is that the potential difference between the base and emitter is greater than 0.6 .

JoXRa> 0.6 (V) −・
(1) Note that the composite internal resistance R2 existing along the depth direction of the n+ type source region 3 is sufficiently smaller than the internal resistance Ra, and therefore can be ignored. A breakdown current J that satisfies Equation (1) in the strange transistor T. When the current flows in, the parasitic transistor T becomes conductive.

At this time, the collector current flowing through the parasitic transistor T is the product of the base current and the DC current amplification factor hFE of the parasitic transistor T. Normally, the DC current amplification factor "FE" is a very large value, and the collector current flowing through the parasitic transistor Tr becomes a large current.

Therefore, a large current flows in a short time, and the power MO3F
ET is destroyed.

[Problem to be solved by the invention]

Since conventional field effect semiconductor devices such as power MO8FETs are configured as described above, they have a low breakdown resistance and tend to break down instantaneously when overload is applied.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to improve the breakdown strength and to obtain a field effect semiconductor device which is less likely to be destroyed by overload.

[Means to solve the problem]

A field effect semiconductor device according to the present invention includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed within a surface of the first semiconductor region, and a second semiconductor region of a second conductivity type formed within a surface of the first semiconductor region. 2
a third semiconductor region of the first conductivity type formed within the surface of the semiconductor region; a bottom surface of the third semiconductor region and the second semiconductor region;
a buffer layer formed between the first semiconductor region and the third semiconductor region to reduce carrier injection efficiency between the second and third semiconductor regions; a gate insulating film formed on the surface of the semiconductor region; a gate electrode formed on the gate insulating film; and a gate electrode formed on the surface of the third semiconductor region and the surface of the second semiconductor region. It is equipped with an electrode.

(Function) Since the buffer layer in this invention is formed between the bottom surface of the third semiconductor region and the second semiconductor region, carriers between the second semiconductor \A area and the third semiconductor region are Injection efficiency decreases.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure shows an n-channel power MO according to an embodiment of the present invention.
It is a sectional view of a basic MOS unit cell of 8FET. n
An oxide layer 10 is formed between the bottom surface of the type source region 3 and the p-type semiconductor region 2. This oxide layer 10 is for reducing carrier injection efficiency between the p-type semiconductor region 2 and the n + -type source region 3. Note that the oxide layer 10
is formed apart from the channel forming region 4, so
This does not affect the original operation of the n-channel power MO8FET.

The other configuration is a power MO8 constructed by arranging a plurality of conventional basic MOS unit cells adjacent to each other.
It is similar to FET. Moreover, its operation is also the same as the conventional one.

Next, the manufacturing method will be explained. Figure 2 (a) to (h)
is an n-channel type power MO8 according to an embodiment of the present invention.
FIG. 3 is a process cross-sectional view showing an example of a method for manufacturing an FET.

In FIG. 2(a), the n+ type drain region 1an
A shaped drain region 1b and a gate insulating film 5 are sequentially laminated. For the n+ type drain region 1a and the n- type drain region 1b, an epitaxial substrate in which an n type epitaxial layer is formed on an n+ type silicon substrate may be used. In FIG. 2(b), a gate electrode 6 made of polysilicon or the like is laminated and etched according to the pattern of the resist 11. As shown in FIG. In FIG. 2C, p-type impurity ions are implanted, and after removing the resist 11, diffusion is performed to form a p-type semiconductor region 2.

In FIG. 2(d), resist 12 is applied to the entire surface,
Patterning is performed so that the resist 12 remains on the gate electrode 6 and the gate insulating film 5 on the central portion of the p-type semiconductor region 2. Gate insulating film 5 on p-type semiconductor region 2 is removed by etching according to the pattern.

In FIG. 2(e), oxygen ions 13 are implanted into the opening with high energy so as to reach a sufficient depth. Furthermore, n-type impurity ions 14 are implanted into the openings of the same pattern from above. The implantation energy at this time is such that the n-type impurity ions 14 are implanted into a shallower region than the previously implanted oxygen ions 13.

In FIG. 2(), resist 12 is removed and heat treatment is performed. Oxygen ions 13 and n-type impurity ions 14 are diffused to form an oxide layer 1o and an n+ type source region 3, respectively.

In FIG. 2(a), a living room insulating film 8 is laminated on the entire surface,
Etch into a predetermined pattern. The central gate insulating film 5 used as a mask for ion implantation is also etched at the same time.

In FIG. 2(h), the patterned interlayer insulation i
! ! A source electrode 7 is formed on 8 and its opening, and a drain electrode 9 is formed on the back surface of n+ drain region 1a, to finally obtain the structure shown in the figure.

Next, it will be explained with reference to FIG. 3 that an oxide layer 10 of a desired thickness is formed at a desired depth by the oxygen ion implantation process into the silicon substrate used in the step shown in FIG. 2(e). do.

FIG. 3 is a graph showing an example of the distribution of oxygen ions resulting from implantation of buried ions into a silicon substrate. Figure 3 (a
), the horizontal axis is the depth from the silicon substrate surface (μm
), and the vertical axis is the oxygen/silicon composition ratio No/Jlsi. Implantation energy 150key/atom oxygen ion O
The distribution when + is implanted into the silicon 3i (111) plane is
The injection volume (0/ci) is shown as a parameter.

In addition, in FIG. 3(b), the implantation energy is 70 k
Oxygen ion 02+ of ey/atom is converted to silicon 3i (100
) shows the distribution when injected onto the surface.

As is clear from the above example, when the injection amount is increased, the distribution becomes saturated and changes from a Gaussian distribution to a trapezoidal distribution, and the width of the trapezoidal distribution becomes wider. The peak value of the composition ratio in the trapezoidal distribution is 2. This ratio is silicon oxidation! ! Equal to the proportion of oxygen in (Si02).

The depth position of the center of the distribution depends on the implantation energy. In the above example, since the implantation energy is constant, the center of the distribution is fixed at a specific depth position, but by changing the implantation energy, it can be moved to a desired depth position.

From these facts, it is understood that by appropriately controlling the implantation amount and implantation energy, the oxide layer 10 with a desired thickness can be easily formed at a desired depth position in the silicon substrate (p-type semiconductor region 2). It will be.

Next, the destruction mode of this power MO8FET will be explained. Power M according to an embodiment of the invention shown in FIG.
In the O8FET, since the oxide layer 10 is formed in the boundary region between the n+ type source region 3 and the p-type semiconductor region 2, carriers between the base and emitter of the parasitic transistor T are left in the vicinity of the channel forming region 4. injection efficiency is significantly reduced. Therefore, the DC N current amplification factor hFE of the parasitic transistor T becomes smaller, and the parasitic transistor T.

is difficult to activate, and even if activated, its collector current will be sufficiently small. That is, even if an overload is applied, a large current will not flow through the power MO8FET of this embodiment, making it difficult to break down instantaneously, resulting in a structure that achieves improved breakdown resistance.

FIG. 4 shows an n-channel (In5ula) provided with an oxide layer 10 which is another embodiment of the present invention.
ted Gate Bipolar Transist
FIG. 2 is a cross-sectional view of a basic unit cell of an insulated gate bipolar transistor. A p shadow region 15 is provided in contact with the drain electrode 9 . The rest of the structure is similar to the power MO8FET shown in FIG. In the case of IGBI-, there is a parasitic thyristor, but the above-mentioned MOS
As with the FET example, even if an overload occurs, it is difficult to activate, and even if it is activated, the current value is sufficiently small, so I
The destruction resistance of GBT is improving.

Furthermore, IGBTs often have a structure in which the current capacity is suppressed (non-latch-up structure) so that the saturation current value is below the latch-up current, but in the case of the IGBT according to this embodiment, latch-up does not occur. Since this is less likely to occur, the saturation current value can also be increased.

Further, in the above embodiment, oxide 1l110 was provided as the loose II layer, but instead of this oxide layer 10, another insulating layer such as a nitride layer may be provided. For example, in the case of a nitride layer, it is formed by implanting nitrogen ions, and the implantation depth and density of nitrogen ions can be controlled as well as the implantation of oxygen ions. In addition to the insulation layer! A damaged layer having local lattice defects may be provided between the p-type semiconductor region 2 and the n + -type source region 3 as the 1-layer. This damaged layer is formed by irradiation with other ions or protons. For example, in the case of proton irradiation, it is known that the depth at which a damaged layer is formed can be accurately controlled.

Since the damaged layer has lattice defects, it easily traps carriers, and the p-type semiconductor region w<2 and the n+-type source region 3
The injection efficiency of carriers between the two is significantly reduced. As a result, the same effect as in the example in which an insulating layer is provided as described above can be achieved.

In the above embodiments, power MO8FETs and IGBTs whose basic unit cells have a rectangular shape have been described, but the present invention can be similarly applied to those having other shapes.

Furthermore, the present invention is similarly applicable to p-channel MO8FETs of other conductivity types, p-channel IGBTs, and other types of field-effect semiconductor devices.

〔Effect of the invention〕

As described above, according to the present invention, since the buffer layer is formed between the bottom surface of the third semiconductor region and the second semiconductor region, the buffer layer is formed between the bottom surface of the third semiconductor region and the second semiconductor region. carrier injection efficiency decreases. Therefore, it is possible to obtain a field-effect semiconductor device that has improved breakdown resistance and is difficult to break down even when overloaded.

[Brief explanation of the drawing]

FIG. 1 shows a power MO8FET according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the manufacturing process of the power MO3FET shown in FIG. 1, FIG. 3 is a graph showing an example of the distribution of oxygen ions implanted into a silicon substrate, and FIG. A cross-sectional view of an example IGBT, FIGS. 5 and 6 are a plan view and a cross-sectional view of a conventional power MO8FET, respectively, FIG. 7 is a graph showing the characteristics of a conventional power MO8FET, and FIGS. ) are a configuration diagram of a MOS unit cell and a connection diagram of its equivalent circuit. In the figure, 1a is an n + type drain region, 1b is an n type drain region, 2 is a p type semiconductor region, 3 is an n + type source (a region, 4 is a channel forming region, 5 is a gate insulating film, 6 is a
7 is a gate electrode, 7 is a source electrode, 8 is an interlayer insulating film, 9 is a drain electrode, and 1o is an oxide layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed within a surface of the first semiconductor region; and a second semiconductor region of a second conductivity type formed within a surface of the second semiconductor region. a third semiconductor region of the first conductivity type formed; and a third semiconductor region formed between the bottom surface of the third semiconductor region and the second semiconductor region, and a carrier carrier between the second and third semiconductor regions. a buffer layer that reduces injection efficiency; a gate insulating film formed on the surface of the second semiconductor region between the first semiconductor region and the third semiconductor region; and a gate insulating film formed on the gate insulating film. the gate electrode and the third
and an electrode formed on the surface of the semiconductor region and the surface of the second semiconductor region.