JP2009099920A - Electronic switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic switch having a high speed and low resistance. <P>SOLUTION: A p-type semiconductor substrate or a film is used as an A film; a n-type or an i-type semiconductor film is formed on it to use the film as a B film; a p-type semiconductor film is formed on it to use the film as a C film; a n-type semiconductor film is formed on part of the C film to use it as a D film; and an insulating material film is formed so as to come into contact with the C film and the D film, and a conductive film is formed on the insulating material layer to use the conductive film as a gate electrode. The conductive film is brought into contact with the A film to use it as a collector electrode. The conductive film is brought into contact with the D film to use it as an emitter electrode. In the electronic switch, a potential difference between the emitter electrode and the gate electrode is fluctuated to change impedance between the collector electrode and the emitter electrode. The lifetime of a minority carrier in part of the region of the A film having a distance of ≥10 nm as a distance from the bonded faces of the A film and the B film is set to ≤1/100, or ≤50 ns in comparison with the B film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a current switching function.

  Conventionally, Insulated Gate Bipolar Transistor (IGBT) is used as an electronic switch for an inverter for power conversion and a switching power source. In recent years, in order to reduce the size of these electronic circuits, the switch frequency is increased to reduce the reactors and capacitances in the circuits, thereby reducing the size. However, in the IGBT, the current switch time is about 100 ns when it is turned on, and 1 μs is required to turn it off. Accordingly, the switch time limits the maximum operating frequency, and switch circuits using these electronic switches have been conventionally used with an upper limit of 100 kHz.

  For further miniaturization, it is desired to keep the switch time to 100 ns or less in both the ON and OFF operations. However, the switch time during the OFF operation is the charge accumulated in the element during the ON operation of the IGBT. It has been determined by the time to pull it out, and the structure has been devised so far. FIG. 2 shows a sectional view of an IGBT as a conventional technique.

  In order to turn on the IGBT, as shown in FIG. 3, the collector is set to a positive potential with respect to the emitter, and the gate is set to a positive potential. At this time, as shown in the figure, electrons are injected from the emitter into the i-type semiconductor layer, and at the same time, holes are injected from the p-type semiconductor layer close to the collector into the i-type semiconductor layer, whereby a current flows between the collector and the emitter. At this time, accumulation of electrons and holes occurs in the i-type semiconductor layer, and a certain time is required to remove the accumulated charge when the OFF operation is performed, and this is the main component of the switch time.

  Conventionally, in order to suppress the accumulation of electric charges with the aim of shortening the switch time, a method for suppressing the lifetime of carriers in the same layer by introducing a lifetime killer into the whole or part of the i-type semiconductor layer It has been. As a method for introducing a lifetime killer, gold atom diffusion, proton irradiation, and electron beam irradiation have been performed. By suppressing the lifetime of the carriers in the same layer by this method, the charges accumulated during the ON operation are positively recombined to suppress the accumulated charge amount. Although this method is effective in shortening the switch time, there has been an undesirable problem that the resistance (ON resistance) of the IGBT itself during the ON operation increases. This is because the conductivity modulation of the i-type semiconductor layer disappears by suppressing the lifetime of the same layer.

  As another attempt, by using an SiGe layer instead of Si for the p-type semiconductor electrode layer adjacent to the collector electrode layer by Asano et al., An energy barrier is formed between the same layer as the i-type semiconductor layer. A non-patent document 1 discloses a report of speeding up by removing holes accumulated in a semiconductor layer at high speed. However, even if the switch time is shortened, band discontinuity occurs in the valence band, and an undesired problem that the ON resistance increases occurs.

  As described above, the IGBT switching time and the ON resistance are in a trade-off relationship, and it is desired to develop a technology that satisfies both at the same time.

“Solid-State Electronics”, 2005, 49, p2006-2010

Indication of invention

Problems to be solved by the invention

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique that can shorten the switch time without deteriorating the ON resistance of the IGBT.

Means for solving the problem

The present invention suppresses the accumulated charge during the ON operation of the IGBT by spatially suppressing the lifetime of a part of the p-type semiconductor layer close to the collector electrode of the IGBT.
As a means for solving the problem, the schematic explanatory diagram of the electronic switch related to the prior art in FIG. 2 and the schematic diagram explaining the mechanism of charge accumulation during the ON operation of the electronic switch related to the prior art in FIG. I will explain.

The current during the ON operation of the IGBT flows as shown in FIG. At this time, the charge densities of the holes and electrons accumulated in the i-type semiconductor layer 2 are substantially equal to each other due to the charge neutral condition during a large current operation, and are uniformly distributed in the i-type semiconductor layer 2. It is known to do. At this time, the charge density of holes and electrons is set to ΔN. At this time, the electron current I _e is I _e = qAΔND _n / L _n
It is expressed. In this case, q is an elementary charge, A is an area of the IGBT operating region, D _n is an electron diffusion coefficient of the p-type semiconductor layer 1, and L _n is an electron diffusion length of the p-type semiconductor layer 1. In addition, the Hall current I _h is I _h = qAΔND _p / L _p
It is expressed. At this time, D _p represents the diffusion coefficient of holes in the n-type semiconductor layer 4, and L _n represents the diffusion length of holes in the n-type semiconductor layer 4. The total current I of the IGBT is I = qAΔN {D _n / L _n + D _p / L _p }
It is expressed. Further, Lp and Ln are expressed by the following equations.
L _p = (D _p τ _p ) ^1/2
L _n = (D _n τ _n ) ^1/2
Here, τ _p and τ _n are the lifetime of holes in the n-type semiconductor layer 4 and the lifetime of electrons in the p-type semiconductor layer 1, respectively. That is, if the carrier lifetime of the p-type semiconductor layer 1 or the n-type semiconductor layer 4 close to the collector is reduced, ΔN, that is, the charge density accumulated in the i layer can be suppressed when I is constant. .

  In the present invention, since no lifetime killer is introduced into the i-type semiconductor layer, the conductivity modulation effect during the ON operation is not lost, and deterioration of the ON resistance can be avoided.

  For example, it is not necessary to suppress the lifetime over the entire area of the p-type semiconductor layer 1 close to the collector. If the lifetime is suppressed in the entire area, a leakage current is generated in the OFF operation, which is not preferable. According to the device simulation, it is possible to suppress the occurrence of leakage current by installing a region for suppressing the lifetime in a region of 10 nm or more from the interface between the p-type semiconductor layer 1 and the i-type semiconductor layer 2 close to the collector. it can. The same applies to the n-type semiconductor layer 4, and the leakage current can be suppressed by setting the region where the lifetime is suppressed from the interface between the n-type semiconductor layer 4 and the p-type semiconductor layer 3 to a position farther than 10 nm. it can.

  Although the above lifetime is suppressed, the accumulated charge of the IGBT can be reduced to less than half by setting it to 1/100 with respect to the area around the suppressed area or by setting it to 50 ns or less as a numerical value. Is clarified from the calculation by device simulation.

In order to suppress the lifetime in a space-selective manner for the above applications, the object can be achieved by providing defects such as point defects, dislocations, and stacking faults in the semiconductor layer at 10 ⁵ / cm ² or more. The defect generates a recombination center near the center of the semiconductor forbidden band, through which minority carrier indirect recombination occurs, leading to a reduction in lifetime.

  As the above-described spatially selective lifetime suppressing method, the object can be achieved if the surrounding semiconductor is composed of Si and the region where the lifetime is to be spatially suppressed is composed of SiGe. At that time, it has been empirically clarified from a number of experiments that the lifetime can be formed at the above-mentioned concentration by making SiGe into a layer, the film thickness to be 0.1 μm or more, and the Ge concentration to be 4% or more. . Defects can cause distortion in the SiGe film due to lattice mismatch with Si in contact with SiGe, which causes the defects.

  When SiGe is used, there is a concern that the ON resistance may increase due to band discontinuity in the valence band. However, a junction surface between SiGe and Si is formed in the p-type semiconductor layer 1, and the p-type semiconductor layer is moderately doped. By maintaining the concentration, it is possible to suppress the resistance generated at the joint surface due to the tunnel effect, and to avoid an increase in the ON resistance.

  In addition to the above devices, by adding an appropriate lifetime killer to the i-type semiconductor layer 2, the IGBT accelerates indirect recombination in the same layer when the ON operation is performed, and reduces the amount of stored charge, thereby enabling a faster switch Expect to work. At that time, if the lifetime is less than 10 ns from the simulation calculation, the ON resistance is remarkably increased, and an undesirable problem of heat generation occurs. On the other hand, if it is 100 ns or more, a significant effect of reducing accumulated charge cannot be obtained.

  The above device has been described only for the p-type semiconductor layer 1 close to the collector layer. However, in the uppermost n-type semiconductor layer 4, the same device as the p-type semiconductor layer 1 close to the collector can be used. The accumulated charge during the ON operation can be reduced, and an effect can be brought about in realizing a high-speed operation. Further, when the gate electrode is in direct contact with the C layer without an insulating film, a switching element called a gate turn-off thyristor is obtained. Even in this case, the accumulated charge during the ON operation is reduced for the same reason as described above, and the effect of realizing a high-speed switch is brought about.

The invention's effect

  By using the present invention, an electronic switch such as an IGBT or a thyristor can be operated at high speed without sacrificing the ON resistance, and the switch circuit using the switch can be conveniently reduced in size by increasing the frequency.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a schematic explanatory view of a cross section of an electronic switch according to an embodiment of the present invention.

  The electronic switch of the present invention has a p-type semiconductor substrate or film, which is used as a p-type semiconductor layer 1, an n-type or i-type semiconductor film is formed thereon, and this is used as an i-type semiconductor film 2. A p-type semiconductor film 3 is formed thereon, an n-type semiconductor film 4 is formed on a part of the p-type semiconductor film 3, and a gate insulating layer 5 is formed so as to be in contact with the p-type semiconductor film 3 and the n-type semiconductor film 4. Then, a conductive film is formed over the insulator film, and this conductive film is used as the gate electrode layer 9. Further, a conductive film is brought into contact with the p-type semiconductor layer 1 to form a collector electrode layer 7. Further, a conductive film is brought into contact with the n-type semiconductor film 4 to form an emitter electrode layer 6. The impedance between the collector electrode 10 and the emitter electrode 8 is changed by changing the potential difference between the emitter electrode 8 and the gate electrode 11, and the junction between the p-type semiconductor layer 1 and the i-type semiconductor layer 2 is characterized. The lifetime of minority carriers is set to 1/100 or less with respect to the i-type semiconductor layer 2 for a part of the region of the p-type semiconductor layer 1 having a distance of 10 nm or more as a distance from the surface, or 50 ns or less, The region is a p-type semiconductor layer 12 whose lifetime is suppressed.

In the electronic switch having the above characteristics, except for the p-type semiconductor layer 12 whose lifetime is suppressed, it is made of Si single crystal. The doping concentration of the p-type semiconductor layer 1 was 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ and the thickness was 0.1 to 2 μm. The doping concentration of the i-type semiconductor layer 2 was 1 × 10 ¹⁴ / cm ³ and the thickness was 20 μm. The doping concentration of the p-type semiconductor layer 3 was 1 × 10 ¹⁶ / cm ³ and the thickness was 0.2 μm. The doping concentration of the n-type semiconductor layer 4 is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ and the thickness is 0.2 μm. The material of the gate insulating layer is SiO ₂ and the thickness is 0.2 μm. High-density polysilicon was used for the emitter electrode, gate electrode, and collector electrode. The lifetime of each semiconductor layer was 10 μs.

  In order to turn on this type of electronic switch, a voltage of about 10 V is applied to the gate electrode 9 with respect to the emitter electrode 8, and at the same time, the potential of the collector electrode 10 is set to a positive potential with respect to the emitter electrode 8. Do.

  In order to confirm the operation of this electronic switch, a device simulation was performed. This simulation was performed by solving the Poisson equation and the charge continuity equation consistently for each semiconductor layer.

The stored charge density ΔN of the i-type semiconductor layer when the electronic switch was turned on and the current density was flowing at 100 A / cm ² was determined. First, ΔN was 1.5 × 10 ¹⁷ / cm ³ when the p-type semiconductor layer 12 whose lifetime was suppressed, which is the main element of the present invention, was not provided. In contrast, the p-type semiconductor layer 12 whose lifetime is suppressed is provided in a region of 10 nm or more from the interface between the p-type semiconductor layer 1 and the i-type semiconductor layer 2. At this time, when the lifetime of the p-type semiconductor layer 12 was 50 ns, ΔN was reduced by 10%, and when it was further 1 ns, it was reduced by 80%. It became clear that the time required to switch from ON to OFF can be reduced by reducing ΔN, and that it can be reduced to 1/5 with a lifetime of 1 ns.

  Similarly, in addition to the above-described device, by providing a region with a suppressed lifetime in the n-type semiconductor layer 4 of the emitter, ΔN is reduced by about 10% compared to the case without it, and the time for switching from ON to OFF is reduced. Can be reduced.

As a manufacturing method of the p-type semiconductor layer 12 with a suppressed lifetime, it is effective to configure the surrounding semiconductor layer as Si and the p-type semiconductor layer 12 with a suppressed lifetime as SiGe. When the SiGe concentration is 4% or more and the thickness is 0.1 μm or more, dislocations can be generated in the same layer at 10 ⁵ / cm ² or more. As a result of actual measurement, it was confirmed that the lifetime of the same layer was 1 to 10 ns, which proved effective in obtaining the above effect.

  With the above structure, when the gate electrode layer 5 is in direct contact with the p-type semiconductor layer 3 without an insulating film, a switching element called a gate turn-off thyristor is obtained. Even in this case, it was confirmed by device simulation that the same effect as described above was obtained.

  Schematic explanatory diagram of an electronic switch according to an embodiment of the present invention   Schematic explanatory diagram of electronic switches related to the prior art   Schematic explaining the mechanism of charge accumulation during ON operation of electronic switches related to the prior art

Explanation of symbols

1 ... p-type semiconductor layer, 2 ... i-type semiconductor layer,
3 ... p-type semiconductor layer, 4 ... n-type semiconductor layer,
5 ... Gate insulating layer, 6 ... Emitter electrode layer,
7 ... Collector electrode layer, 8 ... Emitter electrode,
9 ... Gate electrode layer, 10 ... Collector electrode,
11: Gate electrode,
12 ... p-type semiconductor layer with suppressed lifetime,
13 ... Electron flow during ON operation
14 ... Hall flow during ON operation

Claims (6)

  There is a p-type semiconductor substrate or film, this is used as an A film, an n-type or i-type semiconductor film is formed thereon, this is used as a B film, and a p-type semiconductor film is formed thereon. This is used as a C film, an n-type semiconductor film is formed on a part of the C film, this is used as a D film, an insulator film is formed in contact with the C film and the D film, and a conductive film is formed on the insulator film. The conductive film is used as a gate electrode. Also, a conductive film is brought into contact with the A film, and this is used as a collector electrode. In addition, a conductive film is brought into contact with the D film to form an emitter electrode. By changing the potential difference between the emitter electrode and the gate electrode, the impedance between the collector electrode and the emitter electrode is changed, and the region of the A film having a distance of 10 nm or more from the junction surface of the A film and the B film An electronic switch characterized in that the lifetime of some minority carriers is set to 1/100 or less of the B layer, or 50 ns or less.   2. The electronic switch according to claim 1, wherein, in the region of the E layer, the lifetime of minority carriers is set to 1/100 or less of the B layer in a region at least more than 10 nm from the interface between the D layer and the E layer. And an electronic switch characterized by being 50 ns or less.   3. The electronic switch according to claim 1, wherein a lifetime of part or all of the B layer is set in a range of 10 to 100 ns. 4. The electronic switch according to claim 1, wherein defects such as dislocations are introduced into the semiconductor layer in order to suppress a lifetime, and the density of dislocations is 10 ⁵ / cm ² or more. Electronic switch.   5. The electronic switch according to claim 4, wherein in order to introduce dislocations, the B and C layers are Si semiconductors, and only the A layer, only the E layer, or both the A layer and the E layer are Si containing Ge. An electronic switch characterized in that the Ge concentration in the Si region containing Ge is 4% or more and the thickness thereof is 0.1 μm or more.   6. The electronic switch according to claim 1, wherein the gate electrode is in direct contact with the C layer without an insulating film interposed therebetween.

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