JP2002222951A - Method for controlling switching speed of insulated gate bipolar transistor(igbt) element, its structure and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate switching by shortening a life of a minority carrier in an insulated gate bipolar transistor(IGBT) element. SOLUTION: The insulated gate bipolar transistor(IGBT) element comprises a p-n-p type bipolar transistor having a p+-type silicon substrate 1 as a collector, an n+-type buffer layer 2 formed on the substrate 1 and having an n--type thin layer 3 on an upper part, and a p-type base region selectively formed on a main surface of the layer 3, an n+-type emitter region formed on a main surface of the base region, an emitter metal formed on the emitter region, and a gate electrode of a polysilicon formed on a gate oxide of a channel region of an upper part of a part surrounded by the p-type base region, n--type epitaxial layer and an n+-type emitter region. The transistor (IGBT) element further comprises a misfit transfer layer formed by a method for doping a germanium(Ge) in the n+-type buffer layer 2 in adjacent interfaces between the layer 2, the substrate 1 and the epitaxial layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling the switching speed of an insulated gate bipolar transistor (IGBT) and an insulated gate bipolar transistor (IGBT).
BT) and a method of manufacturing the same. In particular, the present invention relates to a low on-resistance power transistor device, a method of manufacturing the same, and a method of controlling a switching speed thereof.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional n-channel insulating gate.
Single-cell bipolar transistor (IGBT)
FIG. During manufacturing, high voltage and high current switches
Many cells corresponding to the switching elements are connected in parallel and I
A GBT element is formed. Each IGBT cell has n⁺
Buffer layer 2 is p⁺It is formed on a silicon substrate 1 and has n
⁻Layer 3 is the n⁺Epitaxial growth on buffer layer 2
And the p-type base layer 4 is⁻Epitaxy
Selectively formed on the main surface of the metal layer 3. like this
And the pnp bipolar transistor becomes p⁺Semiconductor layer
1, n-type layers 2 and 3 (n⁻And n⁺) And p-type base layer
4 is formed. n⁺The emitter region 5 further includes
It is selectively formed on the main surface of the mold base layer 4. policy
The gate electrode 7 of the recon is n⁻Epitaxial layer 3 and n⁺
The main part of the p-type base layer 4 sandwiched between the emitter regions 5
Deposited on the channel region 6 on the surface and
A gate insulating film 8 exists between the gate electrode 7 and the channel region 6.
Are there. Emitter metal (ie emitter electrode)
9 is formed on the main surface of the semiconductor substrate 10 and
p-type base layer 4 and n⁺Electrically connected to emitter region 5
Has been continued. Collector metal (ie, collector
Pole) 22 is the semiconductor substrate 10, that is, the p⁺Silico
It is electrically connected to the lower side of the main surface of the substrate 1.

[0003] The operating principle of IGBT elements is well known from the prior art. When the device is turned on by a forward bias, holes are injected from the substrate 1 into the n ^- epitaxial layer 3 (also called the drift layer) and dramatically reduce the on-resistance. The carrier concentration in the epitaxial layer 3 is changed from an original turn-off value of 10 ¹⁴ / cm ³ to 10 ¹⁶ / cm ³ to 10 due to a forward voltage bias.
¹⁷ / cm ³ . However, when switching from forward bias to reverse bias, such excess minority carriers are not possible because the high density of minority carriers (ie, holes) cannot be quickly eliminated in the drift layer. It slowly disappears through recombination in the form of a trace of current. When the collector current is reduced from the on-state current value to 10% thereof, the time taken is called the turn-off time. Therefore, in the conventional IGBT element, the n ⁺ silicon substrate of the MOSFET can be replaced with the p ⁺ silicon substrate 1, and the n ⁻ epitaxial layer 3 having high electric resistance can withstand a high breakdown voltage of 600 to 1500 volts. Can be used for It is also possible to inject holes from the p ⁺ silicon substrate 1 into said epitaxial layer 3 to reduce the forward voltage drop and reduce the on-resistance during the on-state. However, reducing the forward voltage drop slows down the switching speed and further increases the relaxation time. It also produces a large leakage current. In the prior art, to overcome this drawback, the epitaxial layer 3 (ie, the drift layer)
Have a high density of minority carrier recombination centers to increase the switching speed.

In the prior art, methods of improving switching speed include irradiating high energy particles, the most commonly used being electrons. This method is called an electron emission method. As seen in FIG. 2, the waveforms of the collector current before (a) and after (b) the electron emission show that the turn-off time is from 15 to 30 μs before the emission to after the emission depending on the radiation dose and annealing conditions. 10-20
0 ns. However, the electron emission has to go through low temperature annealing and requires special high voltage equipment, which is disadvantageous in terms of manufacturing cost.

[0005] The minority carrier lifetime can be reduced by other methods, for example, Pt or Au is added to the transistor element to increase the minority carrier recombination centers during transistor fabrication. Such prior art methods produce an effect similar to electron emission by uniformly doping and dispersing Pt or Au throughout the transistor, in other words accelerating the recombination of minority carriers. However, while the presence of Pt and Au shortens minority carrier lifetime and improves switching speed, the solubility of Pt and Au in silicon is limited and excess Pt and Au increase forward voltage drop. Cause high leakage current.

[0006]

SUMMARY OF THE INVENTION The power semiconductor devices provided by the present invention further improve their long-standing problems. The power device has a low resistance, can reduce the forward voltage drop, and has a high defect density at a specific location (ie, in and around the n ⁺ buffer region), which increases the switching speed of the device. , And also reduce turn-off time. The present invention also discloses a method for manufacturing the power semiconductor device on a silicon single crystal substrate without transfer more efficiently than the prior art manufacturing method. That is, the newly developed technology adds germanium atoms to the n ⁺ buffer region to generate high-density dislocation defects, increase switching speed, and reduce power consumption. As the concentration increases to the limit, misfit transitions occur due to the larger atomic size of germanium than silicon. The transition is a good recombination center.

[Means for Solving the Problems]

An object of the present invention is to provide an insulated gate bipolar transistor (IGBT) in which the recombination center is arranged not in the drift layer but in the buffer layer as in the prior art.
It is to provide an element. Therefore, without a forward voltage drop and increased leakage current, the on-resistance is kept low and the switching speed is faster, resulting in a reduced turn-off time.

It is another object of the present invention to provide a method of manufacturing the above-described insulated gate bipolar transistor (IGBT) device which is more efficient than conventional manufacturing methods.

It is a further object of the present invention to provide an insulated gate bipolar transistor (IGBT) device which can reduce minority carrier lifetime and improve switching speed without changing the forward voltage drop and leakage current of the device. It is an object of the present invention to provide a method for controlling the switching speed of a bipolar transistor (IGBT) device.

[0010] To achieve the above object, the first aspect of the present invention is as follows.
According to the aspect of p, ⁺Silicon substrate, front
Note p⁺N formed on a silicon substrate⁺Buffer layer
And said n⁺N formed on the buffer layer⁻Epitaxy
A p-type base region in the n-type region.⁻Epitaxy
Formed by selectively forming the main surface on the
Pnp bipolar transistor, the base region
N formed on the upper main surface⁺Emitter region, the emitter
Emitter metal formed on the⁻Epitaxy
Layer and n⁺The upper chip of the part surrounded by the layer emitter region
Polysilicon formed on the gate oxide in the channel region
Insulated gate bipolar transistor having a gate electrode
Misfit in transistor (IGBT) device
The transition layer is⁺Buffer layer and the p⁺Silicon base
Board and said n⁻Adjacent interfaces between epitaxial layers
The above n⁺Doping germanium (Ge) into the buffer layer
Formed by the way that
Shorter carrier life and faster switching speed
Insulated gate bipolar transistor characterized by the following:
An (IGBT) device is provided.

According to another aspect of the present invention, p ⁺ silicon substrate as a collector, the p ⁺ silicon substrate n ⁺ buffer layer bonded to, and a thin n wherein n ⁺ buffer layer thereon ^- the layer And p formed by selectively forming a p-type base region on the main surface on the n ⁻ thin layer.
an np bipolar transistor, an n ⁺ emitter region formed on the main surface on the base region, an emitter metal formed on the emitter region, a channel above a portion surrounded by the n ⁻ epitaxial layer and the n ⁺ layer emitter region In an insulated gate bipolar transistor (IGBT) device having a polysilicon gate electrode formed on a gate oxide in a region, the size of germanium is larger than that of silicon.
e) into the n ⁺ buffer by the method of doping e) into the n ⁺ buffer layer, the p ⁺ silicon substrate and the n ⁺ buffer.
^- formation of an interface to the misfit dislocation layer adjacent between the epitaxial layer becomes possible, the defect layer by wafer bonding is formed between the p ⁺ silicon substrate and the n ⁺ buffer layer, in that way, a small number Provided is an insulated gate bipolar transistor (IGBT) element characterized in that the switching speed is increased by shortening the life of the carrier.

According to a further aspect of the present invention, an insulating gate is provided.
Method of manufacturing bipolar transistor (IGBT) device
A method is provided wherein the insulated gate bipolar transistor is provided.
(IGBT) element has p as a collector⁺Silicon base
Board, said p⁺N formed on a silicon substrate⁺buffer
A layer, and the n⁺N formed on the buffer layer⁻Epita
X layers in order, and the n⁻On the epitaxial layer
By selectively forming a p-type base region on the main surface
Generated pnp bipolar transistor, said base
N formed on the main surface on the region⁺Emitter region,
Emitter metal formed on the emitter region, p-type base region
Area and n⁻Epitaxial layer and n⁺In the layer emitter area
Gate oxide in the channel region above the enclosed area
A polysilicon gate electrode formed thereon;
⁺Collector electrode formed on bottom main surface of silicon substrate
Having the size of an atom of germanium
Is larger than silicon, so n⁺Layer epitaxy
A small amount of GeH during growth ₄The epitaxial growth equipment
Germanium (Ge) by adding
n⁺Depending on the method of adding to the buffer layer, n⁺Bag
P-layer and the p⁺A silicon substrate and the n⁻Epitaki
A misfit transition layer is placed on the adjacent interface between the char layers.
Can be formed, and thus, the minority carrier
Features shorter life and faster switching speed
Insulated gate bipolar transistor (IGB)
T) A method for manufacturing a device is provided.

According to still another aspect of the present invention, there is provided a method of manufacturing an insulated gate bipolar transistor (IGBT) element, wherein the insulated gate bipolar transistor (IGBT) element has a p ⁺ silicon substrate as a collector, an n ⁺ buffer layer joined on a p ⁺ silicon substrate, and the n ⁺ buffer layer has a thin n ⁻ epitaxial layer thereon, and selectively has a p-type base region on a major surface on the n ⁻ thin layer Pn formed by forming
a p-type bipolar transistor, an n ⁺ emitter region formed on the main surface on the base region, an emitter metal formed on the emitter region, a p-type base region, and an n ⁻ epitaxial layer and an n ⁺ layer emitter region. A polysilicon gate electrode formed on the gate oxide in the channel region above the portion and a collector electrode formed on the bottom major surface of the p ⁺ silicon substrate, wherein the defect layer Formed by wafer bonding between the p ⁺ silicon substrate and the n ⁺ buffer layer, thereby shortening the minority carrier lifetime and increasing the switching speed. An IGBT) device manufacturing method is provided.

According to yet another aspect of the present invention, there is provided a method of controlling a switching speed of an insulated gate bipolar transistor (IGBT) element, wherein the insulated gate bipolar transistor (IGBT) element has p ⁺ as a collector. silicon substrate, n ⁺ buffer layer bonded to the p ⁺ silicon substrate, and the n ⁺ buffer layer is thinner n thereon ^- having an epitaxial layer, the n ^- p-type base on the main surface of the thin layer A pnp bipolar transistor formed by selectively forming a region, an n ⁺ emitter region formed on a main surface on the base region,
An emitter metal formed on the emitter region, a p-type base region and a polysilicon gate formed on a gate oxide in a channel region above a portion surrounded by the n ⁻ epitaxial layer and the n ⁺ layer emitter region. An electrode, and a collector electrode formed on the bottom major surface of the p ⁺ silicon substrate, wherein the germanium atoms are larger in size than silicon, so that a small amount is formed during the epitaxial growth of the n ⁺ layer. the method of adding germanium (Ge) in the ^{n +} buffer layer by the addition of GeH ₄ into the epitaxial growth apparatus, the ^{n +}
At the adjacent interface between the buffer layer and the p ⁺ silicon substrate and the n ⁻ epitaxial layer, a misfit transition layer can be formed, thus shortening the minority carrier lifetime and increasing the switching speed. Insulated gate bipolar transistor (IG
A method is provided for controlling the switching speed of a BT) element.

According to yet another aspect of the present invention, there is provided a method of controlling a switching speed of an insulated gate bipolar transistor (IGBT) element, wherein the insulated gate bipolar transistor (IGBT) element has p ⁺ as a collector. silicon substrate, n ⁺ buffer layer bonded to the p ⁺ silicon substrate, and the n ⁺ buffer layer is thinner n thereon ^- having an epitaxial layer, the n ^- p-type base on the main surface of the thin layer A pnp bipolar transistor formed by selectively forming a region, an n ⁺ emitter region formed on a main surface on the base region,
An emitter metal formed on the emitter region, a p-type base region and a polysilicon gate formed on a gate oxide in a channel region above a portion surrounded by the n ⁻ epitaxial layer and the n ⁺ layer emitter region. An electrode, and a collector electrode formed on the bottom main surface of the p ⁺ silicon substrate, wherein a transition layer is formed by a method of adding germanium (Ge) to the n ⁺ buffer layer; ^A defect layer is formed by wafer bonding between the ⁺ silicon substrate and the n ⁺ buffer layer, and
A method is provided for controlling the switching speed of an insulated gate bipolar transistor (IGBT) device, wherein the switching speed is increased by shortening the minority carrier lifetime.

According to another aspect of the present invention, the concentration of germanium preferably has a value between 0.5 and 4 atomic% of silicon.

In accordance with yet another aspect of the invention, the defect layer is formed by bonding a polished p ⁺ CZ wafer to an n ⁻ FZ wafer to have an n ⁺ top layer by wafer bonding. Wherein ⁿ - ^{n +} top layer of FZ wafer solid source diffusion,
It can be formed by gas source diffusion or ion implantation. Arsenic and antimony if ion implantation is used is preferably ion, the n ^- FZ polished surface of the wafer may be patterned prior to n ⁺ doped.

BEST MODE FOR CARRYING OUT THE INVENTION

The above objects, aspects and advantages of the present invention are:
It will become more apparent from the detailed description taken in conjunction with the following drawings. Here, FIG. 1 is a cross-sectional view showing a conventional n-channel insulated gate bipolar transistor (IGBT) element. 2A and 2B are collector current turn-off waveform diagrams before and after electron emission, respectively.
3A and 3B are cross-sectional views illustrating structures of a transition layer and a defect layer according to the present invention, respectively. 4A to 4M are cross-sectional views showing detailed manufacturing steps of an insulated gate bipolar transistor (IGBT) device according to the present invention.

Referring to FIG. 1, the invention provides a thickness of about 5 mm.
An n ⁺ buffer layer 2 doped with phosphorus of 〜12 μm is formed on the p ⁺ silicon substrate 1 and has a thickness of about 60 to 150 μm.
μm n ⁻ epitaxial layer 3 is the n ⁺ buffer layer 2
An insulated gate bipolar transistor (IGB) having a p ⁻ type base region 4 selectively formed on a main surface on the n ⁻ epitaxial layer 3.
T) providing an element; In this way, the pnp bipolar transistor is composed of the p ⁺ semiconductor layer 1, the n-type layers 2 and 3 (n ⁻
And n ⁺ ) and p-type base layers. An n ⁺ emitter region 5 is further selectively formed on the upper main surface of the p-type base layer 4. A gate electrode 7 of polysilicon is deposited on the channel region 6 above the main surface region of the n ⁻ epitaxial layer 3 and the p-type base layer 4 surrounded by the n ⁺ emitter region, and
And a gate insulating film 8 between the channel region 6. An emitter metal (that is, an emitter electrode) 9 is formed on an upper main surface of the semiconductor body 10 and is electrically connected to the p-type base layer 4 and the n ⁺ emitter region. Collector metal (ie, collector electrode) 11 is electrically connected to semiconductor body 10, that is, the lower surface of p ⁺ silicon substrate 1.

As shown in FIG. 3A, the present invention provides a method for improving the switching characteristics of an insulated gate bipolar transistor (IGBT) device. The fact that the atomic size of germanium is larger than that of silicon causes a well-known misfit transition structure. The transition layer 2 ′ is formed by adding germanium (Ge) during the growth of the n ⁺ epitaxial layer with a small amount of GeH ₄ into an epitaxial reactor (not shown).
Germanium concentration of 0.5 to 4 atomic% with respect to silicon
The n ⁺ buffer layer 2 can be formed by doping such that In that way, the minority carrier lifetime is reduced and the switching speed is increased. Then n
^An epitaxial layer 3 is epitaxially grown on said buffer layer 2;

According to the present invention, there is provided another method for improving the switching characteristics of an insulated gate bipolar transistor (IGBT) device. As shown in FIG. 3B,
The defect layer 2 ″ is formed between the p ⁺ silicon substrate 1 and the n ⁺ buffer layer 2 by wafer bonding. Reference numeral 2 ′ denotes a transition layer formed by germanium atoms.
The bonding surface formed between layers 1 and 2 was brought into contact at room temperature and then 0.1 PSI to 10 PSI (about 6.9 × 10 ²
It is formed by applying a constant pressure of Pa to 6.9 × 10 ⁴ Pa). The connection between the two surfaces is van der
Produced by the power of Waals. The bonded wafer at room temperature is further heated to 800-1200 ° C., thereby diffusing the atoms and joining the atomic lattice of the two layers. Referring again to FIG. 3B, n ⁻ FZ with n ⁺ top layer
The wafer is bonded to a polished p ⁺ CZ wafer (ie, a p ⁺ silicon substrate). The n ^- layer of the wafer so bonded is grounded and polished to the desired thickness. Wherein n ^- n ⁺ top layer of FZ wafer solid phase diffusion may be formed by implantation gas phase diffusion or ion. If ion implantation is arsenic and antimony is desirable if used, also the n ^- FZ polished surface of the wafer is patterned before the n ⁺ doped. The defect layer thus manufactured can control the switching speed of the IGBT by controlling the recombination speed of the excess minority carriers in the IGBT. According to the present invention, the recombination centers of minority carriers are formed in the buffer layer instead of the conventional drift layer. Therefore, it is possible to reduce the leakage current.

FIGS. 4A to 4M are cross-sectional views showing detailed steps of manufacturing an insulated gate bipolar transistor (IGBT) device according to the present invention. Such steps are performed after completion of the transfer layer or wafer bonding according to the present invention, and include the following steps. (1) As shown in FIG. 4A, a field oxide layer 11 is grown on the n ⁻ epitaxial layer 3; (2) As shown in FIG. 4B, a photoresist 12 is supplied to form ap ⁺ implantation opening 13 And etching the field oxide 11; (3) Perform ap ⁺ implant to perform p ^{+ as} shown in FIG. 4C.
Forming a base layer 14 and removing the photoresist layer; (4) driving-in a p ⁺ dopant to form the p-type base layer 14, as shown in FIG. 4D; (5) FIG. 4E 4G, the gate oxide 15 is grown and the polysilicon layer 16 is deposited. (6) As shown in FIG. 4F, the polysilicon gate electrode 17 is formed by masking and etching the polysilicon gate electrode. (7) As shown in FIG. 4G, p ^- implantation and p ^- drive-in are performed to form a base region 18; (8) As shown in FIG. 4H, n ⁺ photo performing n ⁺ implant is provided a resist layer; (9) as shown in FIG. 4I, the each resist layer is removed n ⁺ implantation of the drive - the emitter region 19 by performing an in Formed to; (10) as shown in FIG. 4J, BPSG (boro phospho
depositing an oxide inner layer 20 such as silicate and forming a contact photoresist layer; (11) etching the oxide inner layer 20 to form an emitter contact as shown in FIG. Removing the resist layer to metallize the emitter contacts; (12) forming a passive layer (oxide + nitride) 32; (13) polishing and cleaning the bottom surface of the wafer as shown in FIG. 4L. And a collector electrode metal (titanium, nickel) 22 is vapor-phase deposited; (14) A cross-sectional view of the completed insulated gate bipolar transistor (IGBT) device is as shown in FIG. 4M.

The above is a vertical double diffused n-channel I
Although described in the form of GBTs, the invention is also applicable to p ^- channel IGBTs and trench IGBTs. Furthermore, the present invention is not limited to the above-described ones, and various modifications and alterations are allowed, but the meaning and scope of the present invention should be determined based on the description in the claims. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional n-channel insulated gate bipolar transistor (IGBT) element.

FIGS. 2A and 2B are collector current turn-off waveform diagrams showing before and after electron emission, respectively.

3A and 3B are cross-sectional views illustrating structures of a transition layer and a defect layer according to the present invention, respectively.

FIG. 4A is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4B is a cross-sectional view showing a detailed manufacturing process of the insulated gate bipolar transistor (IGBT) device according to the present invention.

FIG. 4C is a cross sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4D is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4E is a cross sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4F is a cross sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4G is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention;

FIG. 4H is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4I is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4J is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4K is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention;

FIG. 4L is a cross-sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

FIG. 4M is a cross sectional view showing a detailed manufacturing step of the insulated gate bipolar transistor (IGBT) element according to the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 n ⁺ buffer layer 2 ′ transition layer 2 ″ defect layer 3 n ⁻ epitaxial layer 4 p-type base region 5 n ⁺ emitter region 6 channel region 7 gate electrode 8 gate insulating film 9 emitter electrode 10 semiconductor substrate 11 internal oxidation Object or field oxide 12 Photoresist layer 13 Opening 14 P-type base region 15 Gate oxide 16, 17 Polysilicon 18 P-type base region 19 Emitter region 20 Oxide inner layer 21 Passive layer 22 Collector electrode

Claims (12)

[Claims] 1. A p ⁺ silicon substrate as a collector, the p ⁺ silicon having an n ⁺ buffer layer formed on the substrate and the n ⁺ buffer layer is n on top ^- has a thin layer,
Forming a pnp bipolar transistor by selectively forming a p-type base region on the main surface on the n ⁻ thin layer; forming an n ⁺ emitter region on the main surface on the base region; Forming the emitter metal,
An insulated gate bipolar transistor (IGBT) in which a polysilicon gate electrode is formed on a gate oxide in a channel region above a portion surrounded by a p-type base region, an n ⁻ epitaxial layer, and an n ⁺ layer emitter region.
In the device, a method in which a misfit transition layer doped germanium (Ge) into the n ⁺ buffer layer into an adjacent interface between the n ⁺ buffer layer and the p ⁺ silicon substrate and the n ⁻ epitaxial layer. Characterized in that the switching speed is increased by shortening the life of the minority carrier in such an insulated gate bipolar transistor (IGBT) element. 2. An insulated gate bipolar transistor (IGBT) device according to claim 1, wherein the concentration of germanium is preferably in the range of 0.5 and 4 at% of silicon. 3. The collector as p⁺Silicon substrate, said
p⁺N bonded on a silicon substrate⁺With buffer layer
And n⁺The buffer layer has n⁻With thin layer
And said n⁻Selective p-type base region for main surface on thin layer
Pnp bipolar transistor
Is formed on the main surface of the base region. ⁺Emitter area
Region and form an emitter metal over said emitter region
And a p-type base region and n⁻Epitaxial layer and n⁺
In the channel region above the part surrounded by the layer emitter region
Forming a polysilicon gate electrode on a gate oxide
Insulated gate bipolar transistor (IGB)
T) In the device, the size of germanium atoms is
N⁺Buffer layer and the p
⁺A silicon substrate and the n⁻Neighbor between epitaxial layers
At the interface where they meet, germanium (Ge)
⁺Misfit due to doping method in buffer
A transition layer can be formed, and the defect
The p⁺A silicon substrate and the n⁺Buff
Between the minority layers and thus the minority carrier
Features shorter life and faster switching speed
Insulated gate bipolar transistor (IGB)
T) Element. Wherein said defect layer is a p ⁺ CZ wafers polished n ^- is formed to have an n ⁺ top layer through the bonded wafer by bonding the FZ wafer, the n ^- F
The n ⁺ top layer of the Z wafer is formed by solid source diffusion, gas source diffusion, or ion implantation, where arsenic and antimony are the preferred ions if ion implantation is used, and the polished surface of the n ^- FZ wafer is n
4. The insulated gate bipolar transistor (IGBT) device of claim 3, which can be patterned before ⁺ doping. 5. The collector as p⁺Silicon substrate, said
p⁺N formed on a silicon substrate⁺With buffer layer
And n⁺The buffer layer is n⁻With a thin layer,
The n⁻Selective formation of p-type base region on main surface on thin layer
To form a pnp bipolar transistor.
Formed on the main surface on the base region.⁺Emitter area
Forming an emitter metal over said emitter region;
n⁻Epitaxial layer and n⁺Surrounded by a layer emitter region
Over the gate oxide in the channel region above the
Insulated gate type bar formed with a silicon gate electrode
In a method for manufacturing an bipolar transistor (IGBT) element,
And the atomic size of germanium is larger than silicon
So n⁺During epitaxial growth of buffer layer
A small amount of GeH₄Into the epitaxial growth equipment
By the said n ⁺Germanium (G
e) by adding⁺Buffer layer and front
Note p⁺A silicon substrate and the n⁻Between epitaxial layers
Misfit transition layer at the adjacent interface of
And a small number of carry
That the switching speed has been shortened by shortening the life of
Insulated gate bipolar transistor (IG
BT) A method for manufacturing an element. 6. The method of manufacturing an insulated gate bipolar transistor (IGBT) device according to claim 5, wherein the concentration of germanium is preferably in the range of 0.5 and 4 at% of silicon. 7. The collector as p⁺Silicon substrate, said
p⁺N bonded on a silicon substrate⁺With buffer layer
And n⁺The buffer layer has n⁻With thin layer
And said n⁻Selective p-type base region for main surface on thin layer
Pnp bipolar transistor
Is formed on the main surface of the base region. ⁺Emitter area
Region and form an emitter metal over said emitter region
And a p-type base region and n⁻Thin layer and n⁺Layer emitter area
Acid in the channel region above the enclosed area
Of polysilicon gate electrode on oxide
Manufacture of gate type bipolar transistor (IGBT) device
In the fabrication method, the defect layer is⁺Silicon substrate and said
n⁺Formed by wafer bonding between buffer layers,
Switch to shorten the minority carrier life
Gate type insulator characterized by increased
A method for manufacturing a polar transistor (IGBT) element. Wherein said defect layer is a p ⁺ CZ wafers polished n ^- is formed to have an n ⁺ top layer through the bonded wafer by bonding the FZ wafer, the n ^- F
The n ⁺ top layer of the Z wafer is formed by solid source diffusion, gas source diffusion, or ion implantation, where arsenic and antimony are the preferred ions if ion implantation is used, and the polished surface of the n ^- FZ wafer is n
The insulated gate bipolar transistor (IGBT) device of claim 7, which can be patterned before ⁺ doping. 9. p ⁺ silicon substrate as a collector, the p ⁺ silicon having an n ⁺ buffer layer formed on the substrate and the n ⁺ buffer layer is n on top ^- has a thin layer,
Forming a pnp bipolar transistor by selectively forming a p-type base region on the main surface on the n ⁻ thin layer; forming an n ⁺ emitter region on the main surface on the base region; Forming the emitter metal,
An insulated gate bipolar transistor (IGBT) in which a polysilicon gate electrode is formed on a gate oxide in a channel region above a portion surrounded by a p-type base region, an n ⁻ epitaxial layer, and an n ⁺ layer emitter region.
In the method of controlling the switching speed of the device, since the size of germanium atoms is larger than that of silicon,
A small amount of Ge during epitaxial growth of the n ⁺ buffer layer
The method of adding germanium (Ge) in the n ⁺ buffer layer by the addition of H ₄ in the epitaxial growth apparatus, the n ⁺ buffer layer and the p ⁺ silicon substrate and the n ^- adjacent between the epitaxial layer An insulated gate bipolar transistor (IGBT) device characterized in that a misfit transition layer can be formed at the interface, thereby shortening the life of minority carriers and increasing the switching speed. How to control the switching speed of a device. 10. The insulated gate bipolar transistor (IGBT) according to claim 5, wherein the concentration of germanium is preferably in the range of 0.5 and 4 at% of silicon.
A method of controlling the switching speed of an element. 11. p ⁺ silicon substrate as a collector, the p ⁺ silicon having an n ⁺ buffer layer which is bonded to a substrate and said n ⁺ buffer layer is thinner n thereon ^- having a thin layer, wherein the n ^- pnp bipolar transistor formed by selectively forming a p-type base region on the main surface of the thin layer, the n ⁺ emitter region formed on the main surface on said base region, an emitter on the emitter region An insulated gate type in which a metal is formed and a polysilicon gate electrode is formed on a gate oxide in a channel region above a portion surrounded by a p-type base region and an n ⁻ thin layer and an n ⁺ layer emitter region. In a method for controlling the switching speed of a bipolar transistor (IGBT) device, a misfit defect layer includes germanium (G) in the n ⁺ buffer layer.
e) and a defect layer is formed by wafer bonding between the p ⁺ silicon substrate and the n ⁺ buffer layer, thus shortening minority carrier lifetime and increasing switching speed. Insulated gate bipolar transistor (IG
BT) A method for controlling the switching speed of an element. 12. The defect layer a p ⁺ CZ wafers polished n ^- is formed to have an n ⁺ top layer through the bonded wafer by bonding the FZ wafer, the n ^-
The n ⁺ top layer of the FZ wafer has solid source diffusion, gas source diffusion,
Or formed by ion implantation, an ion implantation is arsenic and antimony are preferred ion if used, also the n ^- FZ polished surface of the wafer is insulated gate according to claim 11 capable of patterned before n ⁺ doped A method for controlling the switching speed of a bipolar transistor (IGBT) element.