JPH0267631A - Microprogram branch control system - Google Patents

Abstract

PURPOSE:To effectively use the area of a control storage (CS) by accessing an address in the CS corresponding to a suboperation code. CONSTITUTION:An instruction control part 8 executes the fetching of an instruction, decoding of an instruction code or the like. A selector 10 selects an address based upon an instruction code, a suboperation code or a CS data next address information under the control of a CS address selecting circuit 9 and sets up the selected address in a CS address register 11. At the end of the processing of an instruction, an address corresponding to an instruction code is selected as the next CS address without fail. The contents of a microprogram setting up the address as the leading address are successively read out from the CS 12 and processed by an instruction execution part 14.

Description

[Detailed Description of the Invention] [Summary Regarding the control of a microprogram that performs processing related to the execution of an instruction having a co-sub-operation code, the same micro-program related to the processing of an instruction having a sub-operation code is redundantly stored in the control storage. The purpose is to effectively use control storage by eliminating the presence of sub-operation codes in the control storage. means for causing a common microprogram to process a part of the control related to the execution of an instruction having the instruction, and means for transmitting information instructing a branch to an area of the control storage by a specific program step in the microprogram. It is constituted by providing.

[Industrial Field of Application] The present invention relates to the control of a microprogram in an information processing device configured to perform processing related to the execution of instructions using a microprogram, and in particular to the control of a microprogram when an instruction is accompanied by a sub-operation code. Related to control.

[Prior Art] Operations such as reading, decoding, and executing instructions in an information processing device involve basic operations such as accessing main memory, loading data into registers, shifting data, and outputting data to adders. This is achieved through a combination.

Although the process of breaking down instructions into basic operations and executing them can also be achieved using logic circuits, it is performed by a program (microprogram) that specializes in basic operations. Many information processing apparatuses of this type are manufactured because it is possible to do this and it is easy to take measures such as changing the operation.

On the other hand, in recent years, in order to increase the processing speed and functionality of information processing devices, there has been a demand for multifunctional instructions, and an increase in the number of instructions has become necessary.

As the number of instructions increases in this way, the number of bits allocated to conventional instructions (operation codes) is no longer sufficient, so in the case of a specific instruction code, a sub-operation code is added to it to further expand the bits from that instruction code. A plurality of new instructions are created.

[Problems to be Solved by the Invention] Conventionally, instructions with sub-operation codes have been arranged by determining the start address of a microprogram for each sub-operation code or by grouping instructions with sub-operation codes. The method used was to set the address and execute it from each starting address. Regarding the processing of instructions with sub-operation codes, there are many parts that are processed by executing similar micro-steps, even though they are different sub-operations.
For example, as shown in Figure 4, the microsteps of instructions with sub-operation codes #A, #B, and #C are exactly the same from M-00 to M-01-M-02; Different microsteps (M-A
O, M-BO, M-Co).

Conventionally, even in such cases, the start address of the microprogram was determined for each sub-operation code and placed on the control storage.

The present invention makes it possible for instructions with different sub-operation codes to commonly use parts that perform processing by exactly the same microprogram as described above,
It is an object of the present invention to provide a microprogram control method that can avoid the same microprogram from being duplicated on a control storage and make effective use of a control storage area.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention provides an information processing apparatus configured to control the execution of instructions by a microprogram and having an instruction code accompanied by a sub-operation code. A means for providing an area for storing information instructing a branch, a means for having a common microprogram process part of the control related to the execution of instructions having different sub-operation codes, and a sub-operation code of the instruction when the information is detected. This microprogram branch control system is provided with means for selecting a sub-operation code and accessing an address on a control storage corresponding to the sub-operation code.

[Operation] FIG. 1 is a diagram explaining the present invention in detail, in which 1 represents a register in which an instruction code is set, the instruction code is set in 1a, and the sub-operation code is set in Ib.

Further, 2 is a selector, 3 is a CS address selection control unit, and 4 is a selector.
is a CS address register, 5 is a control storage (hereinafter also referred to as C8), 6 is an area for displaying branch instructions, and 7 is a CS data register of the instruction execution section.

In the figure, when an instruction code and a sub-operation code are first set in register l, the CS address selection control unit 3 selects the instruction code by selector 2, and the corresponding address on O8 is set in the CS address register. Set to 4.

And by the address, control storage (
Instructions are executed by accessing C5) and reading the microprogram. The microsteps constituting the microprogram are read out based on the next address information of the immediately preceding microstep. At this time, while reading the microprogram, a branch instruction is displayed (for example, "1") in the area 6 corresponding to the read microstep. ”), this is transmitted to the CS address selection control unit 3, and the CS address selection control unit 3
Instructs selector 2 to select sub-operation code 1b.

This causes selector 2 to change to sub-operation code 1.
b is selected, and the address corresponding to the sub-operation code is set in the Cs address register 4.

Then, by accessing the area of C8 at the address, an instruction execution operation specific to the sub-operation code is performed.

In the present invention, among the instructions having different sub-operation codes due to the above operation, if there is a common part in microprogram processing, there is no need to place all of them on the C8 for each sub-operation, and the same After the microprogram is used in common, it can be branched from a necessary point, so the area of C8 can be used effectively.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention, showing a CS address control system of a microprogram-controlled instruction processing device, where 8 is an instruction control section and 9 is a CS address selection circuit. 10 is a selector, 11 is a CS address register, 12 is a control storage, 13 is a branch display area, 14 is an instruction execution unit, 15 is a CS data register, 1
6 represents a decoder.

In the figure, an instruction control unit 8 takes out instructions, decodes instruction codes, and so on.

The selector 10 is controlled by the CS address selection circuit section,
An address based on the instruction code, sub-operation code, or netast address information of CS data is selected and set in the CS address register 11. - When the processing of an instruction is completed, the address corresponding to the instruction code is always selected as the next first CS address. Then, the microprograms having this address as the start address are sequentially read out from the control storage 12 and processed by the instruction execution unit 14.

When the CS address selection circuit section 9 learns that "1" has been read out from the branch display area 13 during microstep reading, it instructs the selector 10 to select a sub-operation code. As a result, the selector IO selects the sub-operation code and sets the corresponding address in the CS address register 11.

For example, the CS address is 12 pits and the instruction code is
'81, even if it is an instruction with a sub-operation code, the CS address register 11 will contain X'081 regardless of the sub-operation code.
is set.

Then, when it is detected that "1" is displayed in the branch display area of the microstep read from the control storage 12, the CS address selection circuit section 9 instructs the selector 10 to select a sub-operation code. .

], the sub-operation code is x'83 (that is, when the code of the entire instruction is X'8183)
For example, if X'83 is set in the CS address register,
1. :X'883 is set to the value added by X'800.

Figure 3 is a diagram explaining the state of such operation, and #A,
#B and #C indicate instructions having different sub-operation codes.

In the same figure, #A, #B, and #C have the same instruction code, and the microsteps between M-00 and M-02 are common, so the microstep of M-00 is always the first step. is selected and begins processing. And the number 1
At step Mo2 indicated by 7, "l" is set in the branch display area 13 of the control storage 12.

As a result, instruction #A branches to microstep M-AO, instruction #B branches to microstep M-BO, and instruction #C branches to microstep M-CO.

In the conventional method, in such a case, the microstep M
It was necessary for instructions #A, #B, and #C to each have microsteps M-00 to M-02 on C8, but according to the method of the present invention, microsteps M-00 to M-02 are -0
Since it is only necessary to have one set of 2, the area required for control storage is reduced.

For ease of explanation, on the right side of Figure 3, three instructions share a three-step microinstruction, but in reality, many more instructions share many microsteps. It is possible to share the control storage area, and the efficiency of use of the control storage area can be greatly increased.

[Effects of the Invention] As explained above, according to the present invention, in processing related to the execution of an instruction having a sub-operation code, parts of a microprogram that perform a common operation are controlled and stored in a control storage for each different instruction. This eliminates the need to store multiple microprograms in one set of microprograms, and different instructions can easily be used for one set of microprograms, which has the advantage that the control storage area can be used effectively.

Claims (1)

[Claims] In an information processing device configured to control execution of instructions by a microprogram and having instruction codes accompanied by sub-operation codes, each microprogram step in a control storage storing the microprograms is provided. A means for providing an area for storing information instructing branching in correspondence with each other, and having a common microprogram handle part of the control related to the execution of instructions having different sub-operation codes; 1. A microprogram branch control system comprising means for selecting a sub-operation code and accessing an address on a control storage corresponding to the sub-operation code.