JPH0263544U - - Google Patents
Info
- Publication number
- JPH0263544U JPH0263544U JP14355288U JP14355288U JPH0263544U JP H0263544 U JPH0263544 U JP H0263544U JP 14355288 U JP14355288 U JP 14355288U JP 14355288 U JP14355288 U JP 14355288U JP H0263544 U JPH0263544 U JP H0263544U
- Authority
- JP
- Japan
- Prior art keywords
- package
- ceramic
- glass layer
- recess
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例を示す半導体装置の
断面図、第２図は従来の半導体装置を示す断面図
である。 １……セラミツク容器、２……高融点硝子層、
３……リード、４……半導体チツプ、５……ボン
デイング層、６……低融点硝子層、７……キヤツ
プ、８，９……硝子層。
断面図、第２図は従来の半導体装置を示す断面図
である。 １……セラミツク容器、２……高融点硝子層、
３……リード、４……半導体チツプ、５……ボン
デイング層、６……低融点硝子層、７……キヤツ
プ、８，９……硝子層。
Claims (1)
- セラミツク容器の凹部底面に設けた素子載置部
と、前記凹部上段水平面に設けた高隔点硝子層に
より固着して前記セラミツク容器の外部に導出さ
れたリードとを有するパツケージと、前記素子載
置部に搭載して前記リードと電気的に接続された
半導体チツプと、前記パツケージの周縁部上に重
ねたセラミツクキヤツプと、前記セラミツクキヤ
ツプと前記パツケージの間に設けて前記パツケー
ジを封止する低融点硝子層とを有することを特徴
とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14355288U JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14355288U JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263544U true JPH0263544U (ja) | 1990-05-11 |
Family
ID=31410475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14355288U Pending JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263544U (ja) |
-
1988
- 1988-11-01 JP JP14355288U patent/JPH0263544U/ja active Pending