JPH0263093A - Brightness adjusting device for plasma display panel - Google Patents

Abstract

PURPOSE:To inhibit maintenance pulses in each frame periodically and uniformly, to stably adjust brightness at the time of a half-tone display, and to prevent a flicker and an irregularity in brightness by inhibiting the application of maintenance pulses in synchronism with a horizontal synchronizing signal. CONSTITUTION:A brightness adjusting circuit 23 makes an adjustment so that maintenance pulses PS are applied intermittently according to the horizontal synchronizing signal PH. Consequently, the time when no maintenance pulse PS is applied becomes periodically in synchronism with the horizontal synchronizing signal PH and a constant number of maintenance pulses PS are supplied in each frame of the plasma display panel PDP 7 to prevent beats from being generated. Consequently, a signal component of <=60Hz does not appear in light emission on the PDP 7 and the flicker and irregularity in brightness are prevented. Consequently, the brightness is adjusted without generating the flicker nor brightness irregularity.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a brightness adjustment device for a plasma display panel (hereinafter referred to as PDP), and more particularly to a brightness adjustment device for an X-Y matrix type AC type PDP. The purpose of this device is to provide a brightness adjustment device for a PDP that can adjust brightness without causing flicker or brightness unevenness during display. In a brightness adjustment device for a plasma display panel, which has a plurality of discharge cells driven in synchronization with a horizontal synchronizing signal and is applied with sustain pulses having a predetermined alternating cycle, the application of the sustain pulses is controlled between the horizontal intervals. w1
It is configured to include a brightness adjustment circuit that intermittently inhibits the brightness in synchronization with the signal.

[Industrial application field]

The present invention relates to a brightness adjustment device for a PDP, and more particularly to a brightness adjustment device for an AC type PDP of an XY matrix type.

Conventionally, CRT (Cathode Ray Tube
) was the main type of display device, but recently, with the advancement of the information society, display devices have diversified, and flat display devices have been developed. Currently, flat display devices include those using active elements such as electroluminescence (EL), light emitting diodes (LED), and FDP, as well as those using active elements such as liquid crystal (LCD) and electrochromic (ECD).
) and other devices using passive elements are known.

FDP has A depending on the type of driving voltage applied to the discharge cell.
They are classified into C-type PDPs (indirect discharge type) and DC-type PDPs (direct discharge type). In addition, the present invention is classified into an X-Y matrix type and a segment type according to the structure type.
It is related to. Such AC type PDPs are becoming popular as character and graphic display devices for word processors, personal computers, and the like.

[Conventional technology]

FIG. 10 shows an outline of a display device using an AC type PDP. This device is broadly divided into a display drive unit 1 and a display control unit 2 that controls the display drive unit 1.

When the address data control signal is input to the interface circuit 3 of the display control unit 2, it is applied to the Y drive circuit 5 of the display drive unit 1 via the display address buffer 4. The Y drive circuit 5 drives a plurality of FDPs 7 (for example,
400 Y electrodes 8 are driven. On the other hand, in response to the address data control signal input to the interface circuit 3, the display control circuit 9 of the display control unit 2 causes the display drive pulse generator 10 to apply a display drive pulse to the X drive circuit 11 of the display drive unit 1. The X drive circuit 11 drives a plurality of (for example, 600) X electrodes 13 of the FDP 7 designated via the X matrix circuit 12. In this way, Y electrode 8 and X electrode 4I! 13 selectively drives the discharge cells 14 at the intersections of the corresponding Y electrodes 8 and X electrodes 13 to discharge plasma and emit plasma. Images of various characters, figures, etc. will be formed. In the above example, the total number of discharge cells on FDP7 is 400 (Y)X600 (X>
It becomes a dot. Note that the Y drive circuit 5, Y matrix circuit 6, X drive circuit 11, and X matrix circuit 12 are each divided into two parts when the number of each of the X-Y electrodes is as large as m x n. This is to make it easier to take out the terminals since the electrode spacing becomes narrower.

As shown in FIG. 11, the voltage for driving the FDP 7 is a pulse (hereinafter referred to as a write pulse) for writing display data into each discharge cell 14 of the FDP 7.
P, and a pulse for maintaining the written display data (that is, maintaining the discharge) (hereinafter referred to as a sustain pulse)
Ps and a pulse (hereinafter referred to as an erase pulse) PE for erasing the previously written display data (that is, stopping the discharge) are used.

There are various methods for writing, maintaining, and erasing display data, but they can be roughly divided into two methods: a method in which each discharge cell 14 is individually selected and discharged, and a method in which each Y electrode 8 is temporarily
After discharging all the discharge cells on 8, erase pulse PE
There is a method of selectively erasing the discharge cells 14 by using the method.

The explanation here relates to the latter line sequential driving method. According to the line sequential driving method, after all the discharge cells 14 on the selected Y electrode emit light, unnecessary discharge cells 14 are selectively erased, and a desired image is formed with the remaining discharge cells 14. The Rukoto. This is the 11th
This will be explained in further detail using figures.

FIG. 11 is a diagram showing the correspondence between drive pulses and light emission according to the conventional line sequential drive method. First, when a certain X electrode 13 is not selected (erasing operation) at 1゛A, the FDP7
In one horizontal period (IH) of the corresponding Y1! A write pulse Pw is applied to the pole, and the same Y
An erase pulse PE is applied to the electrodes, and then a sustain pulse Ps is applied to all Y electrodes. As a result, the corresponding X electrode 13 becomes L due to the writing pulse P and the erasing pulse PE.
They each emit light as shown in A, but thereafter do not emit light until the next write pulse P is applied.

On the other hand, when the X electrode 13 is selected (writing operation) T
In B, during the IH period of the PDP 7, a write pulse Pw is similarly applied to a certain Y electrode, but an erase pulse PE is not applied at the next timing, and a sustain pulse Ps is applied to all Y electrodes. As a result, the corresponding X electrode 13 continues to emit light like LB until the write pulses P and 4 and the erase pulse PE are applied thereafter. In other words, it exhibits a memory function.

The above operations are performed for each Y electrode in synchronization with the IH synchronization signal vII, and 1
2 screens are formed.

In this manner, according to the conventional driving method, a write pulse P- is first applied to one Y electrode to cause all discharge cells on that Y electrode to emit light, and then, if necessary, an erase pulse is applied to the same Y electrode. Either the pulse PE is applied to erase the selected discharge cell, or the sustain pulse Ps is applied to drive only the selected discharge cell to maintain light emission.
The brightness can be adjusted by controlling the frequency of the sustain pulse Ps.

Here, an example of a conventional brightness adjustment circuit is shown in FIG. 12. The brightness adjustment circuit receives the first sustaining pulse control signal P and the brightness adjustment signal PB, calculates the logical product of both, and controls the second sustaining pulse. A that outputs the signal Psc'
It is composed of an ND circuit 15. First sustain pulse control signal P
so is a signal that controls the frequency of the sustain pulse P3,
The frequency used is usually 20 to 50KH7. The brightness adjustment signal P is generated by an oscillation circuit (not shown) provided separately based on the vertical synchronization signal Pv, as shown in FIG.
The frequency of the brightness adjustment signal Pa is set lower than the frequency of the first sustaining pulse control signal P8o (see FIG. 13). not present.

In the above configuration, as shown in FIG. 13, when the first sustain pulse control signal P8o and the brightness adjustment signal Pa are ANDed, the first sustain pulse control signal P, which is the meat input signal, is
The output of the AND circuit 15 is “HI” only when both C and the brightness adjustment signal Pa are at the “H” level.
Occurs at the I level. Therefore, the brightness adjustment signal PB is “
During the L II level period, it acts as a prohibition signal and the AN
No output from D circuit 15 occurs.

As a result, the second sustain pulse control signal Psc' is intermittently (
In FIG. 12, only 1 pulse is generated among the three first sustain pulse control signals Psc. This second sustaining pulse control v4 signal Psc' causes the Y electrode 8 and the X electrode 4ai13 to
A sustain pulse Ps is applied to. In this way, the second sustain pulse control signal Psc' is intermittently inhibited.
This is substantially equivalent to lowering the frequency of the sustain pulse P8, and a lower frequency of the sustain pulse P means a lower brightness.

Therefore, by arbitrarily adjusting the frequency of the brightness adjustment signal P8, the brightness of the PDP 7 can be adjusted arbitrarily.

On the other hand, in order to display the image on the PDP 7 more accurately and with fine nuances, halftone (or gradation) display is required. As a method for displaying halftones, there is a method that uses the relative difference in the first wall voltage (W, 'D, Petty,
H.G.Slottow, “Multiple 5ta
tesand variable 1ntensity
in the plasIla display
asIla”, IEEE Trans, ED-18
, 654-658 (1971)), a method of controlling the number of light emissions by the relative difference in second wall voltage (11, De Jute
et al, Digest of 5ynps o
f 5ID (1971)), the third field hourly division method (Hiroshi Kurahashi, et al.: “Halftone Display in Plasma Displays”, Materials from the 8th TV Society Image Display System Study Group (1972)), etc. It is being this house,
The third method attempts to display gradations by controlling the light emission time for each field period by turning on and off the application of the sustain pulse Ps and determining it by the sum of the light emission times of a plurality of fields within one frame. be.

[Problem to be solved by the invention]

Among the above-mentioned conventional halftone display methods, the third method can obtain an appropriate brightness level by combining fields in one frame period with light emission and non-light emission. This is excellent in that it is possible to display halftones relatively easily because it is intentionally turned ON and OFF.

However, when performing brightness adjustment in this third method, P
There is a problem in that flickers and uneven brightness occur on the screen of the DP7. Due to brightness adjustment, when the brightness level is lowered, the light emission time in each frame is not constant, and as shown in Figure 15, the 60H7 component, which is the critical frequency of the afterimage effect in the human eye, and the brightness adjustment signal Waviness occurs with the frequency of P8, and flicker occurs due to this waviness having a frequency lower than 60H. The cause of this waviness is that the brightness adjustment signal P8 is oscillated with a random phase.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a brightness adjustment device for a plasma display panel that can adjust brightness without causing flicker or brightness unevenness when displaying halftones on a PDP 7.

[Means to solve the problem]

In order to achieve the above object, the present invention has a plurality of X electrodes 13 and Y electrodes 4[!] arranged in a matrix, as shown in FIG. In a brightness adjustment device for a plasma display panel 7, the device has a plurality of discharge cells 14 formed at intersections with 8, is driven in synchronization with a horizontal synchronizing signal PH, and is applied with a sustain pulse Ps of a predetermined alternating cycle. , a brightness adjustment circuit 23 that intermittently prohibits application of the sustain pulse Ps in synchronization with the horizontal synchronization signal PH.

[Effect]

According to the invention, the brightness adjustment circuit 23 uses the horizontal synchronization signal P
Based on this, the application of the sustain pulse Ps is adjusted to be applied intermittently. Therefore, the time during which the sustain pulse P 1 is not applied becomes periodic in synchronization with the horizontal synchronizing signal P11, and a constant number of sustain pulses Ps are always applied in each frame of the PDP 7, making it possible to prevent beats from occurring. As a result, signal components of 60H7 or less do not appear in the light emission on the PDF) 7, and flicker and brightness unevenness can be prevented.

〔Example〕

Next, embodiments according to the present invention will be described based on the drawings.

Recruitment ixt Futoshi A first embodiment of the present invention is shown in FIGS. 2 and 3.

In addition, in FIG. 2, the same or overlapping parts as in FIG. 12 will be described below using the same reference numerals.

The brightness adjustment circuit 23 in this embodiment uses a horizontal synchronization signal P
1 to 1/N (where N is an integer) and outputs a trigger signal P1 based on the trigger signal P. The brightness adjustment signal generation circuit 17 is composed of a single shot circuit that generates the brightness adjustment signal PB■, and an AND circuit 15.

The trigger signal generation circuit 16 generates at least the horizontal synchronization signal P1.
A trigger signal P1 that alternately inverts positive and negative at a frequency lower than the frequency of 1 is generated.

The brightness adjustment signal generation circuit 17 outputs "L" of the trigger signal P1.
``In the level period TTL, an "L" level single shot pulse PBL having a pulse width corresponding to a time constant τ (-CR) determined by an external variable resistor R and a capacitor is generated from the falling point of the trigger signal PT.

Next, the operation will be explained (see FIG. 3).

The horizontal synchronization signal P1 (Fig. 3 (
When a)) is input, the trigger signal generation circuit 16 sequentially counts the horizontal synchronizing signal P11, and when it reaches the preset value N (5 in the figure), outputs the trigger signal P1, resets, and starts the next count. Resume operation. After this, repeat this operation. Therefore, the trigger signal P is as shown in FIG. 3(b).
As shown in FIG. This trigger signal P1 is output to the brightness adjustment signal generation circuit 17.

The brightness adjustment signal generation circuit 17 generates a single shot pulse PB based on this trigger signal P, and eventually outputs the brightness adjustment signal P shown in FIG. 3(c) as a composite signal. This brightness adjustment signal P is the AND circuit 1
Since the first sustain pulse control signal P8 (FIG. 3(d)) is input to one end of the AND circuit 15, the pulse width τ of the single shot pulse PBL is
The first sustain pulse control signal PSc is masked for a period corresponding to .

That is, the output of the first sustain pulse control signal P8o is prohibited by the single shot pulse PBL, and the first sustain pulse control signal P corresponds to the "H" level period of the brightness adjustment signal PB. is output, and the second sustain pulse control signal Psc' having the waveform shown in FIG. 3(e) is generated. This second sustain pulse control signal PsC' is the sustain pulse P
Therefore, a sustain pulse P8 having a waveform corresponding to the second sustain pulse control signal Psc' is applied to the PDP 7. The second sustain pulse control signal Psc' has a waveform in which the sustain pulse Ps is thinned out by the pulse width τ of the sustain pulse P, and the number of times of application of the sustain pulse Ps is reduced accordingly. Can be adjusted arbitrarily.

In this way, the brightness adjustment signal P8 inhibits the first N-th pulse control signal PSo by a predetermined pulse width τ in synchronization with the horizontal synchronization signal P, so that
The single shot pulse PB-pulse width τ does not change in each frame, and therefore, generation of beat can be prevented.

Furthermore, since the pulse width of the single shot pulse PBL can be changed arbitrarily by changing the size of the variable resistor R, the number of pulses of the second sustaining pulse control signal Psc' can be changed without generating beat, and the pulse width of the second sustain pulse control signal Psc' can be changed arbitrarily. You can adjust the brightness level.

Mth fall A second embodiment of the present invention is shown in FIGS. 5 and 6.

Note that in FIGS. 5 and 6, the same or overlapping parts as in FIG. 12 are given the same reference numerals and will be described below.

As shown in FIG. 4, this embodiment has a period during which the application of a sustain pulse P is prohibited (hereinafter referred to as an OFF period) for brightness adjustment.

) If too many TOFFs are set, each discharge cell 1
Since the sustain pulse Ps is not applied to the memory cell 4 and there is a risk that the memory function that should be originally provided may be lost, this structure is designed to prevent extreme thinning of the sustain pulse Ps.

This kind of thing occurs not only in the conventional case (Fig. 12), but also in the case of
This may also occur in the case of the first embodiment (FIG. 2).

In order to solve the above problem, in this embodiment, the sustain pulse Ps is applied within the OFF period [, to the extent that the memory function is not lost.

As shown in FIG. 5, the brightness adjustment circuit of this embodiment uses an m-ary counter (m =
1/M);
An OR circuit 19 that calculates the logical sum of the brightness adjustment signal P and the mask signal PH and outputs the masked brightness adjustment signals P and '.
and the masked brightness adjustment signal P6. ' and the first sustain pulse control signal Pso to obtain the second sustain pulse control signal P. '.

There are two possible brightness adjustment signals Pa: a conventional signal from an oscillation source of an arbitrary frequency is used, and a brightness adjustment signal PB generated in the first embodiment (FIG. 2) is used. When the conventional brightness adjustment signal P8 is used, the purpose of this embodiment, which is to prevent the memory function of the PDP 7 from disappearing, can be achieved, and when combined with the first embodiment, the PD
In addition to preventing loss of the memory function of P7, it is possible to realize a brightness adjustment circuit that is more stable and does not cause flicker.

A configuration in combination with this first embodiment is shown in FIG. 7, and detailed explanation thereof will be omitted. In the following description, it is assumed that the brightness adjustment signal PB may be any of the above.

Next, the operation will be explained (see FIG. 6).

A horizontal synchronizing signal P is supplied to the mask signal generating circuit 18. is input, the mask signal generation circuit 18 sequentially counts the horizontal synchronizing signal P, outputs the mask signal PH every time it reaches the preset value M (two in the figure), resets, and starts the next counting operation. resume. Thereafter, this operation is repeated, so that the mask signal PM becomes a signal whose positive and negative values are alternately inverted every M value (pulse width of period TH), as shown in FIG. 6(b). This mask signal P8 is output to the OR circuit 19.

The OR circuit 19 generates a masked brightness adjustment signal P8' shown in FIG. 6(d) based on the input mask signal P8. In other words, since the OR circuit 19 takes OR logic,
Brightness adjustment signal P only during the “H” level period of mask signal PM.
During the OFF period of B, ToEF is set to "H'" level and output. This masked brightness adjustment signal P8' is applied to one input of the AND circuit 20.

The AND circuit 20 has the first sustain pulse control signal PSo given to the other input, and is an AN of the first sustain pulse control signal P8o and the masked brightness adjustment signal P a '.
A second sustain pulse control signal P, shown in FIG. 6(e), is obtained by taking the D logic. ′ is generated.

In other words, the OFF period of the brightness adjustment signal PB is 4. Since the first sustain pulse control signal PSC is passed during the period corresponding to the "H" level of the mask signal PH in the OFF period, the OFF period is 1''. , 1 is prevented from continuing for a long period of time.

By the subsequent operation, as shown in FIG. 6(g), for example, the OFF period of the brightness adjustment signal Pa in FIG. 6(c) [[
In this case, the number of sustain pulses Ps that are not applied becomes 6 pulses, and the line that emits light after the n-th Y electrode 8 is n+7.
The Y voltage of the line: i8 is formed, but according to this embodiment, since the standby period of the mask signal PM is in the middle, it will emit light once at the n+3rd line and the n+4th line, and then will not emit light again. Become.

Therefore, there is no possibility that the application of the sustain pulse Ps will be omitted continuously over a long period of time, so that a stable brightness adjustment operation can be performed without impairing the memory function of the PDP 7.

11 dog fake A third embodiment of the present invention is shown in FIGS. 8 and 9.

Note that in FIGS. 8 and 9, the same or overlapping parts as in FIG. 12 are given the same reference numerals and will be described below.

In this embodiment, the OF of the sustain pulse P is similar to the second embodiment.
The purpose of this is to prevent loss of memory function that occurs when the F period TOFF is long.

This embodiment differs from the first embodiment in that the second embodiment uses the mask signal PH to generate masked brightness adjustment signals P,', whereas the first embodiment
By regularly thinning out the sustain pulse control signal Psc at a constant period, it is possible to prevent the application of the sustain pulse Ps from being prohibited for a long period of time and to perform smooth brightness adjustment.

As shown in FIG. 8, the brightness adjustment circuit of this embodiment has a first
Sustain pulse control signal Pso is 1/L (however, is an integer)
The gate signal P is obtained by dividing the frequency into the period of . a gate signal generation circuit 21 consisting of a linear counter (j=1/L) that outputs
A second sustain pulse control signal Psc which is frequency-divided by taking the logical product of the gate signal P6 and the first sustain pulse control signal P3o.
and an AND circuit 22 that outputs '.

Next, the operation will be explained (see FIG. 9).

The first sustain pulse control signal P8 is supplied to the gate signal generation circuit 21.
When o is input, the gate signal generation circuit 21 sequentially counts the first sustain pulse control signal P8c, and outputs the gate signal PG1 every time the preset value L (L=2 in the case of FIG. 9(b)) is reached. This gate signal P repeats the operation of resetting and starting the next counting operation. 1 is AND
It is applied to one input of the circuit 22.

The AND circuit 22 performs an AND logic between the first sustain pulse control signal P3° and the gate signal PG1. Therefore, A.N.
Second sustain pulse control signal P output from D circuit 22
' is the gate signal P. It becomes a signal with the same C period and the same phase as 1. That is, the gate signal P61 is the first sustain pulse control signal P. Since it is a signal whose frequency is divided by 1/2, the first sustain pulse control signal Pso is thinned out once every two times. To change this intermittency ratio, it is sufficient to change the preset value of the gate signal generation circuit 21. By setting L=3, the gate signal PG2 shown in FIG. 9(c) can be obtained, and in that case, the The second sustain pulse control signal Psc' also has a similar waveform. - Numerically, L is preset to n (an integer) as long as the memory function of the PDP 7 is not lost.

According to the above embodiment, although the first sustain pulse control signal P8o is not synchronized with the horizontal synchronization signal P1, it is a signal generated with an accurate period, and this first sustain pulse control signal P8o Since the frequency of the first sustaining pulse control signal P8o is divided in synchronization with Brightness adjustment can be performed without the occurrence of beats as shown in FIG.

Although FIG. 8 shows the frequency division value as L, it is fixed, but in order to make it variably adjustable, for example, it may be operated by a variable resistor R using the brightness adjustment signal generation circuit 17 shown in FIG. The brightness level can be adjusted to any desired level by configuring the brightness level as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, by prohibiting the application of sustain pulses in synchronization with the horizontal synchronizing signal,
Sustain pulses are prohibited periodically and uniformly in each frame, eliminating the occurrence of beats, making it possible to stably adjust brightness when performing intermediate displays, and preventing flickering and uneven brightness. .

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of the first embodiment, Fig. 3 is an operation timing chart of the first embodiment, and Fig. 4 shows an example of a long OFF period of the sustain pulse. Timing chart, Fig. 5 is a block diagram of the second embodiment, Fig. 6 is an operation timing chart of the second embodiment, Fig. 7 is an applied block diagram of the second embodiment, and Fig. 8 is a block diagram of the third embodiment. Block diagram, Figure 9 is the operation timing chart of the third embodiment, Figure 10 is the operation timing chart of the third embodiment.
The figure is a schematic diagram of a display device using an AC type PDP, Figure 11 is a waveform diagram showing a conventional driving method, Figure 12 is a block diagram of a conventional brightness adjustment circuit, and Figure 13 is the operation timing of Figure 12. The chart, FIG. 14 is an explanatory diagram of the brightness adjustment signal, and FIG. 15 is an explanatory diagram of conventional problems. 1...Display drive unit 2...Display control unit 5...Y drive circuit 6...Y matrix circuit 7...PDP 8...Y electrode 11...X drive circuit 12... X matrix circuit 13...X electrode 14...Discharge cell 15...AND circuit 16...Trigger signal generation circuit 17...Brightness adjustment signal generation circuit 18...Mask signal generation circuit 19... OR circuit 20...AND circuit 21...Gate signal generation circuit 22...AND circuit 23...Brightness adjustment circuit Pll...Horizontal synchronization signal Pl...Trigger signal P,,P,'... - Brightness adjustment signal Psc...First sustain pulse control signal Psc'...Second sustain pulse control signal PH...Mask signal, P61. P6□...Gate signal Pl4...Write pulse Ps...Sustain pulse PE...Erase pulse 1,000 synchronization signal Ps This invention Q original j! Explanation of Thai Mini / 7' Mart No. 4 Arotsuku diagram of the second example of the example No. 3 49! Block diagram of J 718th 3rd addition A row movement T Gui ζng chart 9, 9th Fig. M2 Application of actual example 70th time 7th Fig. Waveform diagram showing the conventional drive 77 method Explanation of four-layer adjustment No. 4 Fig. 14 Follow-nu r > MM point &amp;

Claims (1)

[Claims] A plurality of discharge cells (14) formed at the intersections of a plurality of X electrodes (13) and Y electrodes (8) arranged in a matrix
In a brightness adjustment device for a plasma display panel (7), which is driven in synchronization with a horizontal synchronization signal (P_H) and is applied with a sustain pulse (P_S) having a predetermined alternating cycle, the sustain pulse (P_S) The horizontal synchronization signal (
A brightness adjustment circuit (
23) A brightness adjustment device for a plasma display panel, comprising: