JPH02135421A - Multilevel display control driving device for matrix display panel - Google Patents

Abstract

PURPOSE:To easily and inexpensively perform multilevel displays by controlling the clock frequency of a pulse width modulation (PWM) control circuit with a compensation circuit by using a data-side driver incorporating the PWM control circuit. CONSTITUTION:The clock signal CK2 which decides the pulse width used by a data-side driver 4 for making PWM control is variably controlled at a clock frequency change circuit 9 with the compensating value of a charging time constant corresponding to each display element. In other words, outputs of compensating factors alpha and betafrom ROMs 11 and 13 operate as the control voltage of a voltage-controlled oscillation circuit (VCO) 15 after the sum of the outputs is taken by an adder 14 and the output of the VCO 15 is supplied to a PWM control circuit 5 as signals CK2. On the other hand, the pulse width of the output of a counter circuit 18 is inverse proportion to the frequency of the signals CK2 and becomes narrower or wider as the compensating factors become larger or smaller, since the output of the circuit 18 is produced by counting the signals CK2. Therefore, the charging time is fixed and luminance is uniformized by changing the supplying time of modulating voltages to each display element against the same multilevel displaying level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to EL (11/Ctroarchine Minebusesi λ),
The present invention relates to a gradation control driving device for a matrix display panel constructed of capacitive display elements such as a PDP (2000 Hz).

Conventional technology Thin film EL as a matrix display device of capacitive display elements
This will be explained using a display device as an example. The matrix electrodes of an EL display panel are generally comprised of ITO transparent electrodes as data electrodes and aluminum electrodes as scan electrodes. Since each electrode resistance value is the ITO electrode resistance or aluminum electrode resistance due to the difference in materials, the charging time constant for the display element is almost determined by the ITO transparent electrode resistance value. The equivalent circuit of the load seen from the data electrode side is as shown in Figure 7.
It is shown as a continuous π-shaped circuit. Here, r corresponds to the ITO electrode resistance per pitch, C corresponds to the EL capacitance per display element, and n corresponds to the number of scanning electrodes.

Output voltage V for input voltage v1 in this equivalent circuit
The transfer characteristic of o is shown in FIG. The relationship between the input voltage Vi and the output voltage Vo with respect to time t is expressed by the following equation.

Vi/Vo=δ=(1-4/vr)-Σa(AφEx
p-(B4)) However, Σa: a=O~o.

A=(-1)”/(2a+1) B=(2a+1
)・yr 2/4T=t/(nr-nc) Simplifying the above formula, δ(n, t)''; 1-Exp-
(2-0 to 2.3)T.

As the number of stages n increases, the δ slope l of nth (charging rate 100χ)
The time tn for which tn increases. Normally, the pulse width ip of the drive voltage in a binary display needs to be based on the completion of charging to the farthest point element (nth), so by setting tp≧tn, the charging rate to all elements is set to 10Oχ and the data is The EL display element on the electrode is driven in such a way that no luminance gradient occurs.

Problems to be Solved by the Invention When considering gradation display on a matrix display panel, the driving method is frequency modulation (hereinafter referred to as group) for controlling the number of times of application of the driving pulse voltage and pulse of the driving pulse voltage. There are two control methods: pulse width modulation (hereinafter referred to as P) to control the width and amplitude modulation (hereinafter referred to as AM) to control the applied voltage of the drive pulse voltage. 4A control and AM control require a dedicated driver with built-in control circuits for these, and a PWM control driver with a simple circuit configuration is cheaper.

When a capacitive element such as a thin-film EL panel is displayed in gradations using the Phenomenon control method, each display element has a different charging time constant, which causes a brightness gradient due to uneven charging voltage, making it difficult to see gradation differences. In particular, when the charging time constant difference is large or when displaying multiple gradations, it becomes impossible to display gradations partially. Therefore, a closed or AM control method is generally used in which the driving pulse width tp is set to satisfy tp≧tn.

Incidentally, the driving pulse width tp is inevitably determined by the charging time constant of the element, the number of scanning electrodes, the number of frames, and the like. In particular, in panels designed for high resolution and large area, the FM control method has a limited number of gradations due to time constraints and is not suitable for multi-gradation display. Further, although the AM control method can be said to be the best driving method for capacitive load panels, the high-voltage, large-current type 4M control driver is still at the development level and has the problem of being extremely expensive.

In view of the problems of the prior art, the present invention provides an inexpensive gradation display control drive device for a capacitive matrix display panel that eliminates brightness gradient and enables multi-gradation display by compensating the four-way control of the PWM control driver. The purpose is to

Means for Solving the Problems The present invention provides a capacitive matrix display panel, a data side driver having a PWMW control circuit connected to a data electrode, a scan side driver connected to a scan electrode, and a scan side selection electrode. a first time constant compensation circuit that compensates the charging time constant in accordance with the number of display data in one scanning period; a second time constant compensation circuit that compensates the charging time constant in accordance with the number of display data in one scanning period;
The present invention is a gradation display control drive device for a matrix display panel, including a frequency variable circuit that controls the clock frequency of the P%JM control circuit in accordance with the output of the time constant compensation circuit.

Operation The present invention uses the above-described configuration to compensate for non-uniformity of charging voltage caused by charging time constant due to data electrode resistance and each display element capacitance when PWM control is performed by a data side driver incorporating a P%11M control circuit. Therefore, the change in the charging time constant for each display element from the nearest element to the farthest element from the data side driver is calculated by a first time constant compensation circuit that generates a compensation coefficient α corresponding to the scanning side selection electrode. Time constant compensation is performed based on the time constant of the far point element, and a second time constant compensation circuit generates a compensation coefficient β to compensate for changes in the charging time constant related to the number of display data in one scanning period. , the output signal of the frequency variable circuit controlled by the compensation coefficients α and β of the first and second time constant compensation circuits is used as the clock signal of the PWMW control circuit, and the PWMW is controlled in accordance with the scanning side selection electrode and the number of display data. By variably controlling the pulse width of the control output to be narrower than the standard value, the charging voltage for each element becomes uniform, and the brightness gradient along the data electrode line can be eliminated.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of a gradation display control drive device for a matrix display panel in a first embodiment of the present invention. In FIG. 1, 1 is an EL display panel with an x-■ matrix electrode configuration using EL as a display element, 2
3 is a scanning electrode of the EL display panel 1, 4 is a pulse width modulation control circuit 5 (hereinafter, pulse width modulation control is referred to as PWMW control), and a push-pull type driver 6. 7 is a scanning side driver, 8 is a write pulse generation circuit for supplying write pulses to the display element via the scanning side driver 7, and 9 is a clock frequency for controlling the P%11M control circuit 5. It is a variable circuit. Incidentally, the PWMW control circuit 5 of the data side driver 4 receives the clock signal C as shown in FIG.
a shift register circuit 16 for transferring data signals at KI;
A latch circuit 17, P that stores the output for one scanning period
It is comprised of a pulse counter circuit 18 that counts the clock signal CK2 for WMW control, and a pulse width selector circuit 19 that selects the output of the pulse counter circuit 18 in accordance with the data signal content. For example, to display 16 gradations, 4 bits from DO to mouth 3 are used as the data signal.
And 4 bits of pulse counter circuit output are required.

The operation of this embodiment configured as described above will be explained based on FIGS. 3 and 4.

The output of the data side driver 4 is connected to the 1 to m data electrodes 2, and the output of the scan side driver 7 is connected to the 1 to n scan electrodes 3.
It is connected to the. An EL display element capacitor -Emn is present at the intersection of each electrode. Normally, the modulation voltage V- supplied to the data side driver 4 and the write voltage -Vw supplied to the write pulse generation circuit 8 are simultaneously applied to the EL display element, and after line sequential scanning is completed, the write voltage -V
The scanning side driver 7 applies the refresh voltage V with the opposite polarity to w.
By applying more than 100 volts of light, light is emitted twice per frame.

This driving method is called simultaneous inversion refresh driving.

As shown in FIGS. 7 and 8, the charging voltage to the E1 display element is the closest point display element Ex to the data side driver 4.
The farthest point display element E from t (x: l = m)
Since the charging time constant increases as it moves toward As a result, a brightness gradient occurs in the data electrode line direction.

In order to solve this problem, in this embodiment, the clock signal C that determines the pulse width in PWM control of the data side driver 4 is used.
Regarding K2, by using a signal variably controlled by the clock frequency variable circuit 9 using a charging time constant compensation value corresponding to each display element as the clock signal CK2, the modulation voltage to each display element for the same gradation display level can be adjusted. By changing the supply time of Vm, the charging voltage is kept constant and the brightness is made uniform. Note that the scanning order here is such that the nearest point of the data side driver 4 is 1.
It is assumed that line sequential scanning is performed with the farthest point being the nth point.

FIG. 3 shows a block diagram of the variable clock frequency circuit 9. In this circuit, for each display element, (1) a first time constant compensation circuit 20 that compensates for the charging time constant determined by the data electrode resistance r and the display element capacitance c corresponding to the scanning side selection electrode;
2) Compensation is performed by two systems of time constant compensation circuits, the second time constant compensation circuit 21, which compensates the charging time constant in accordance with the number of display data in one scanning period.

The first time constant compensation circuit 20 includes a counter circuit IO and a ROM.
11, a counter circuit 10 counts a scanning side shift signal CKS for performing line sequential scanning, and uses a count output synchronized with a selection electrode as an address signal.
Send to 1. The ROM 11 outputs a preset compensation coefficient α corresponding to the address signal. The compensation coefficient α of the ROM 11 has a maximum value at the first selected electrode and a minimum value at the nth selected electrode with respect to the scanning line shown by the solid line in FIG. 4(a). If the above δ(n, t)
It takes the value of the inter-exponential number as shown by the inverse property of .

The second time constant compensation circuit 21 includes a counter circuit 12 and a ROM.
13, a transfer data signal O1 of display information data
The counter circuit 12 counts the number of display (light emitting or non-light emitting) data during one scanning period while associating the data clock signal CKD with the data clock signal CKD, and sends the output to the ROM 13 which uses it as an address signal.

The ROM 13 outputs a preset compensation coefficient β corresponding to the display ratio obtained from the address signal. To briefly describe the influence of the charging time constant on the display ratio, the display ratio is increased because a charging loop is formed between the selected electrode and the non-selected electrode of the data electrode 2 on the scanning side selected electrode line due to the capacitively coupled matrix electrode configuration. The value of the linear function is taken as the minimum value at 0.100χ and the maximum value (twice the minimum value) at 50χ. Therefore, the compensation coefficient β of the second time constant compensation circuit 13 has a display ratio of 0.100 as shown in FIG. 4(b).
This is the value of a linear function with inverse characteristics, with the maximum value at χ and the minimum value at 50χ. Since these compensation coefficients α and β can be determined from the panel specifications, they may be stored in a memory in advance.

The output of the compensation coefficients α and β from the ROM1113 is sent to the adder 1.
4, the D/A conversion circuit 22 is operated as a control voltage for the voltage controlled oscillation circuit (VCO) 15.

The vCO output is then supplied as 2 to the clock signal C of the pulse counter circuit 18 in the P%l1M control circuit 5. It is assumed that the oscillation frequency of the voltage controlled oscillation circuit 15 changes in proportion to the control voltage. Therefore, the larger the compensation coefficient, the higher the frequency, and the smaller the compensation coefficient, the lower the frequency. Incidentally, the outputs of the compensation coefficients α and β from the ROMs 11 and 13 change every scanning period, as can be seen from the above-described operation.

On the other hand, since the counter circuit 18 outputs the clock signal C by counting 2, its output pulse width is equal to the clock signal C.
It is inversely proportional to the frequency of 2, and the larger the compensation coefficient is, the narrower it is, and the smaller the compensation coefficient is, the wider it is. As for the standard frequency of the clock signal CK2, the compensation coefficients α and β are set to the minimum values (the scanning side selection electrode is n-th and the display ratio is 50I). With this setting, the frequency of the clock signal CK2 is increased by each compensation of the compensation coefficient α for the 1st to n-1st scanning side selection electrodes and the compensation coefficient β for the display ratio ≠50X,
The output pulse width of the pulse counter circuit 18 becomes narrower.

With such control, the scanning side electrode at the standard frequency as described above is the nth electrode and the display ratio is 50.
Normalized to % state. This allows display elements with a small charging time constant to use a modulation voltage Vm with a narrower pulse width than the standard one.
is applied, and as a result, each display element is uniformly charged with the modulation voltage VJI+' corresponding to the designated gradation level, regardless of the magnitude of the charging time constant, and it is possible to eliminate the brightness gradient.

FIG. 5 is another configuration block diagram of the variable clock frequency circuit 9. In FIG. The difference from FIG. 3 is the configuration of the variable frequency oscillation circuit used as clock signal C of the pulse counter circuit 18. Here, the oscillation output signal of the excavation circuit 23 is input to the counter circuit 24, and the output of the adder 14 is input to the counter circuit 24. By controlling the count number for the oscillation output signal of the counter circuit 240, the pulse output interval of the counter circuit 24 is changed, and the clock signal C of the pulse counter circuit 18 is set to 2. With this configuration, the D/A conversion circuit 22 shown in FIG. 3 is not required because it can be controlled by digital signal processing. Incidentally, if the data clock signal CKD has a frequency sufficiently higher than the one scanning period frequency, the excavation circuit 2
It may be used instead of the oscillation output signal of No. 3.

FIG. 6 is a block diagram of a gradation display control device for a matrix display panel showing a second embodiment of the present invention, in which the data electrode 2 is divided into upper and lower halves of an odd data electrode 2a and an even data electrode 2b. This is the case of the EL display panel 1. In this figure, the scanning side driver 7 connected to the scanning electrode 3
, write pulse generation circuit 8, etc. are omitted. An odd-numbered electrode data-side driver 4a is connected to the odd-numbered data electrode 2a, and an even-numbered electrode data-side driver 4b is connected to the even-numbered data electrode 21. The scanning order of the scanning electrodes 3 is such that the odd-numbered electrode data side driver 4a side is first, and the even-numbered electrode data side driver 4h side is the nth.

In such a configuration, the compensation coefficient β of the charging time constant corresponding to the display ratio of the scanning side selection electrode is the same as in the first embodiment, but the time constant in the data electrode direction with respect to the scanning side selection electrode is Odd number data electrode 2a and even number data electrode 2b bordering on the n/2nd selection electrode (center)
It has the opposite characteristics. Therefore, the compensation coefficient α for compensating the charging time constant in the data electrode direction is the same as above for the odd electrode data side driver 2a and the even electrode data side driver 2b, as shown in FIG. 4(a). It is necessary to make the compensation characteristics αa (solid line) and αb (broken line) line symmetrical.

Therefore, for the odd electrode data side driver 4a, the compensation coefficient αa output from the first time constant compensation circuit 20a and the compensation coefficient β output from the second time constant compensation circuit 21 are combined via the adder 14a. The output of the controlled voltage controlled oscillation circuit 15a is set as the clock signal C 2a, and for the even electrode data side driver, the compensation coefficient αb outputted from the first time constant compensation circuit 20b and the second time constant compensation circuit 21 are output. By controlling two systems of variable clock frequency circuits that use the output of the voltage controlled oscillation circuit 15b, which controls the compensation coefficient β via the adder 14b, as the clock signal CK2b, the brightness slope is displayed as in the first embodiment. The entire panel is compensated.

As described above, with the compensation coefficient α of the charging time constant of the data electrode corresponding to the scanning side selection electrode of the display element and the compensation coefficient β of the charging time constant corresponding to the number of display data in one scanning period, P%I!
By controlling the PWM control clock frequency of the data side driver for M control, the brightness gradient caused by the charging time constant can be eliminated and multi-gradation display can be achieved. Compensation coefficient α
-β is not limited to the characteristics shown in FIGS. 4(a) and 4(b), but may need to have an inverse characteristic depending on the characteristics of the variable frequency circuit. Furthermore, although the simultaneous inversion refresh driving method has been described as a driving method for the thin film E1 display panel, the present invention is not limited to this, and other driving methods such as the frame inversion driving method may be used. In this embodiment, a thin film E display panel has been described, but it goes without saying that any matrix display panel including a capacitive load, such as a PDP, is effective.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when driving a capacitive matrix display panel, the clock frequency of the Pli1M control circuit is controlled by a compensation circuit using a data side driver having a built-in PWM control circuit. By eliminating the brightness gradient and applying a voltage to the display element that is apparently the same as that of the H-M control method, multi-gradation display can be easily realized at low cost, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a gradation display control driving device for a matrix display panel according to a first embodiment of the present invention, and FIG. 2 is a block diagram of a data side driver incorporating a P%l1M control circuit in the same embodiment. , FIG. 3 is a block diagram of a clock frequency variable circuit that controls the clock frequency of the PWM control circuit in the same embodiment, and FIG. 4 is a block diagram of the compensation coefficients α and β of the time constant compensation circuit of the clock frequency variable circuit in the same embodiment. 5 is a block diagram of another configuration of the clock frequency variable circuit in the same embodiment, FIG. 6 is a block diagram of the gradation display control device for the matrix display panel in the second embodiment, and FIG. 7 is a characteristic graph. N-stage continuous π-type circuit diagram, which is an equivalent circuit of a capacitive matrix display panel, No. 8
The figure is a transfer characteristic graph of an N-stage continuous π-type circuit. l...EL display panel, 4...data side driver,
5... Pulse width modulation control circuit, 9... Clock frequency variable circuit, 1O112... Counter circuit, 1113
...ROM, 15...Voltage control oscillation circuit, 20...
・First time constant compensation circuit, 21... Second time constant compensation circuit Name of agent: Patent attorney Shigetaka Awano Exit route display data ratio diagram diagram diagram diagram] diagram

Claims (5)

[Claims] (1) A matrix display panel consisting of a capacitive display element in which data electrodes and scanning electrodes are orthogonal to each other, a data-side driver having a pulse width modulation control circuit connected to the data electrodes that supplies a modulation voltage, and a data-side driver that supplies a write voltage. A scanning side driver connected to the scanning side electrode, a first time constant compensation circuit that compensates the charging time constant with a compensation coefficient α corresponding to the scanning side selection electrode, and a first time constant compensation circuit that compensates for the charging time constant with a compensation coefficient α, and charging according to the number of display data in one scanning period. a second time constant compensation circuit that compensates the time constant with a compensation coefficient β;
The gradation of a matrix display panel characterized by comprising a frequency variable circuit that controls the clock frequency of the pulse width modulation control circuit in accordance with the compensation coefficients α and β outputs of the first and second time constant compensation circuits. Display control drive device. (2) The compensation coefficient α of the first time constant compensation circuit is an exponential function with the first scan selection electrode as the maximum value (minimum value) and the last scan selection electrode as the minimum value (maximum value), and the second time constant compensation circuit The compensation coefficient β has a maximum value (minimum value) of 50% when the ratio of the number of luminescent display data to the total number of data in one scanning period is 0 and 100%.
2. The gradation display control drive device for a matrix display panel according to claim 1, wherein the linear function has a minimum value (maximum value) at . (3) The first time constant compensation circuit is composed of a counter circuit 10 which inputs a scanning shift signal, and a ROM 11 in which a compensation coefficient α whose output is an address signal is stored. It is composed of a counter circuit 12 which receives a signal and a data clock signal as input, a ROM 13 in which a compensation coefficient β whose output is used as an address signal is stored, and a variable frequency circuit is composed of a voltage control oscillator circuit (VCO) 15. A gradation display control drive device for a matrix display panel according to claim 1. (4) The first time constant compensation circuit consists of a counter circuit 10 which inputs a scanning shift signal, and a ROM 11 in which a compensation coefficient α whose output is used as an address signal is stored. The variable frequency circuit consists of a counter circuit 12 that receives a signal and a data clock signal as input, and a ROM 13 that stores a compensation coefficient β whose output is used as an address signal. 2. The gradation display control device for a matrix display panel according to claim 1, further comprising a counter circuit (23) using a circuit output as a control signal. (5) In a display panel in which the data electrodes are divided into upper and lower parts of an odd number group and an even number group, regarding the clock frequency control of the pulse width modulation control circuit of the odd number electrode data side driver and the even number electrode data side driver, the odd number electrode data 2. The gradation display control device for a matrix display panel according to claim 1, wherein the compensation coefficient α of the first time constant compensation circuit has an inverse characteristic relationship between the side driver and the even-numbered electrode data side driver.