JP3033392B2 - Luminance compensation method and luminance compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a luminance compensation method and a luminance compensation circuit, and more particularly to a luminance compensation method and a luminance compensation circuit for an AC memory type plasma display.

[0002]

2. Description of the Related Art Plasma display panels (PDPs)
Has many features such as a thin structure, no flicker, large display contrast ratio, relatively large screen, fast response speed, self-luminous type and multi-color light emission by using phosphor. In recent years, it has been widely used in the field of computer-related display devices and the field of color image display.

[0003] Depending on the operation method, this PDP has an AC discharge (AC) type in which electrodes are covered with a dielectric and indirectly operates in an AC discharge state, and a PDP in which electrodes are exposed to a discharge space and are directly in a DC discharge state. There is a direct current (DC) type to be operated. Further, the AC type driving is performed by applying an AC pulse because the discharge cell is a capacitive load, and there are a memory operation type using the memory of the discharge cell and a refresh operation type not using the memory as the driving type. The luminance is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage. In the refresh operation type, the brightness decreases as the display capacity increases,
Mainly used for panels with small display capacity.

One display cell 50 of an AC memory type PDP
Referring to FIG. 6 showing a cross-sectional structure of the PDP, this PDP is composed of two insulating substrates 39, 4 made of glass, front and rear.
0, a scan electrode 41 and a sustain electrode 42 formed on the insulating substrate 39, a data electrode 43 formed on the insulating substrate 40 at right angles to the scan electrode 41 and the sustain electrode 42,
Helium in the space between the first and second insulating substrates 39 and 40;
A discharge gas space 44 filled with a discharge gas composed of neon, xenon, or the like, or a mixture thereof, and a partition wall 45 for securing a discharge gas space and separating display cells.
A phosphor 46 for converting ultraviolet light emitted by the discharge of the discharge gas into visible light; a dielectric 47 made of a dielectric covering the scan electrode 41 and the sustain electrode 42;
7 is provided with a protective film 48 made of magnesium oxide or the like which protects the data electrode 7 from discharge, and a dielectric 49 which covers the data electrode 43.

Next, the discharge operation of the selected display cell 50 will be described. A pulse voltage exceeding a discharge threshold, that is, a data pulse, is applied between the scan electrode 41 and the data electrode 43 to start discharge. Positive and negative charges are applied to the dielectrics 47 and 49 on both sides in accordance with the polarity of the data pulse.
Is attracted to the surface of the substrate and charge accumulation occurs. Since the equivalent internal voltage, that is, the wall voltage due to the accumulation of the charges has the opposite polarity to the voltage of the data pulse, the effective voltage inside the cell decreases with the growth of the discharge, and the voltage of the data pulse becomes constant. , The discharge cannot be sustained and finally stops. Thereafter, when a sustain pulse having the same polarity as the wall voltage is applied between the adjacent scan electrode 41 and the sustain electrode 42, the wall voltage is superimposed as an effective voltage. Even if the voltage amplitude is lower than the voltage of the data pulse, it is possible to discharge beyond the discharge threshold. Therefore, the discharge can be maintained by continuously applying the sustain pulse between the scan electrode 41 and the sustain electrode 42. This function is the above-mentioned memory function. Further, the discharge can be stopped by applying an erasing pulse, which is a low-voltage pulse voltage having a magnitude and width that neutralizes the wall voltage, to the scan electrode 41 or the sustain electrode 42.

A PD for dot matrix display in which display cells 50 are arranged in a matrix of j × k rows and columns
Referring to FIG. 7 showing a configuration focusing on the electrode arrangement of P10, PDP 10 shown in FIG. 7 includes scanning electrodes Sc1, Sc2,...
u1, Su2,..., Suj, and data electrodes D1, D2,
, Dk.

Here, a PDP capable of color display can be obtained by applying the phosphors 46 in three colors of RGB.

FIG. 8 is a time chart showing an example of the drive voltage waveform of the PDP 10 described above.
, Su2,..., Suj, scan electrode drive pulses S1, S2, S3 respectively applied to scan electrodes Sc1, Sc2, Sc3, and data electrode Di (1 ≦ i ≦ k). ) Applied to the data pulse D
And The scan electrode drive pulses S1, S2, and S3 include, in addition to the common sustain pulse U1, the scan pulses C1, C2, and C3 and the erase pulse E, which are sequentially applied in the order of S1, S2, and S3 and have independent timings. Including. As a result, the erase pulse E is applied between the scan electrode and the sustain electrode, and is a narrow pulse having a timing slightly delayed from the sustain pulse U2 by about several hundred nS.
In order to turn on the first i-th display cell 50 (hereinafter, display cell 501i), the data pulse Di is made coincident with the timing of the scan pulse C1 so that this scan pulse C1
A discharge is generated between the corresponding scan electrode Sc1 and the data electrode Di. When the display cell 501i is not turned on, the data pulse Di is not applied. As described above, the display cell 50 once lit by the application of the data pulse Di.
In 1i, the discharge is repeated between the scan electrode Sc1 and the sustain electrode Su1 by the sustain pulses U1 and U2 after this timing, and the lighting is continued. Erasing pulse E is applied to the scanning electrode Sc1.
Is applied, the discharge stops and the light goes off.

Referring to FIG. 9, which is a time chart showing sustain periods of all scan lines corresponding to all scan pulses C1,..., Cj in the two-gradation display of PDP 10, the repetition period t1 of the sustain period and each scan Pulse Cn (1 ≦
(n ≦ j) to the erase pulse E, which is a sustain period t2 per scan line, and the start timing of each of these scan pulses Cn, that is, the sustain period t2 is determined by the data clock corresponding to the set pixel. It is shifted every cycle.

Since the sustain pulses U1 and U2 are common to all the scanning lines, generally, the sustain pulses U1 and U2 collectively correspond to a plurality of scanning lines.
Generated by two sustain pulse generation circuits. Unless the PDP is relatively small and the load of the sustain pulses U1 and U2 is small, the display area of the PDP is usually divided into several parts, and one sustain pulse is generated for each of the divided areas. The circuit is assigned.

Sustain pulse driving circuits 14A to 14D for dividing the display area of the PDP into four and supplying sustain pulses U1A to U1D corresponding to the respective areas, and sustain pulses U2A to U2
Referring to FIG. 10 showing an example of a basic PDP drive circuit including sustain pulse drive circuits 15A to 15D for supplying 2D, the basic PDP drive circuit shown in FIG. 10 includes sustain pulse drive circuits 14A to 14D, 15A to 15D. 15D, the PDP 10, data drivers 11 and 12 for applying data pulses Di to respective data electrodes respectively corresponding to odd and even scan lines of the PDP 10, and display data D input by the data clock CK in odd numbers. And data DO and DE divided for an even number of scan lines
And a data distributor 22 for supplying the scan signal C to the data drivers 11 and 12, respectively.
A sustain signal generator 23 that generates sustain signals V1 and V2 corresponding to U1 and U2 and supplies the sustain signals to sustain pulse drive circuits 14A to 14D and 15A to 15D, respectively, a field signal F, a scan signal C, an erase signal E, and a sustain pulse. U1A to U1
A scanning driver 38 that receives the supply of D and generates and supplies a scanning electrode driving pulse Si.

In operation, the start of scanning is set by the field signal F, and the corresponding scanning electrodes are sequentially driven at each timing of the scanning signal C. The display data D is divided into data DO and DE by the data distributor 22 and supplied to the data drivers 11 and 12, respectively. The data drivers 11 and 12 apply the data pulses Di to the data electrodes respectively corresponding to the odd and even scan lines shared by them. Sustain pulse drive circuit 14A
Sustain pulses U1A to U1D supplied by .about.14D are combined with scan pulse Cn and erase pulse E in scan driver 38 and supplied to corresponding scan electrodes as scan electrode pulses Sn.

Here, when the number of lighting of the display cells in a certain area, for example, the area shared by the sustain pulse driving circuits 14A and 15A changes according to the display contents of the PDP, the sustain pulse is generated by the output impedance of the sustain pulse driving circuits 14A and 15A. The waveform amplitudes of U1A and U2A change, and the light emission output per display cell in the above-mentioned area, that is, the luminance changes.
That is, when the number of lights is small, the brightness is large, and when the number of lights is large, the brightness is small.

In order to improve the luminance change caused by the change in the number of lighting of the display cells, a conventional luminance compensation method for counting the number of display data and adjusting a blanking time according to the counted value is disclosed in Japanese Patent Application Laid-Open No. Sho 61 (1986). -98389.

Referring to FIG. 11, a PDP driving circuit including the conventional luminance compensation method includes a PDP 100, a RAM 101 for storing display data, a parallel / serial conversion circuit 102 for parallel / serial conversion of data from the RAM 101, and a PDP.
Control driver 10 for driving the X-side electrode of
3, a Y-side control driver 104 for driving the Y-side electrode, a PDP timing generator 105 for generating and supplying each timing signal, a clock generator 106 for generating and supplying a clock, a refresh counter 107, and overall control Controller 108 that performs
And a display data counter 109 for counting display data.

Referring to FIG. 12 showing a timing chart of a timing signal from the PDP timing generator 105, this timing signal is applied to each of the Y electrodes Y1 to Yn.
, And drives the PDP 100 via the Y-side control driver 104. The PDP discharge period, that is, the display period is determined by the pulse width T of the timing signal, and the remaining time is a blanking time BL. The display data is stored in the RAM 101, and the number of the display data for one line of each of the Y electrodes read out from the RAM 101 by the control signal is counted by the display data counter 109.
And the blanking time BL is controlled to increase or decrease in accordance with the counted value, that is, the number of lit display cells.

[0017]

The above-described conventional luminance compensation method uses a common sustain pulse driving circuit for a plurality of scanning lines as in a normal PDP driving circuit.
There is a drawback that the count value of the display data for each scanning line does not match the number of lighting of the display cells, which is the load of the sustain pulse driving circuit, that is, the number of lighting of the load. Further, in a general PDP drive circuit having the entire display area divided into a plurality of blocks and including a plurality of sustain pulse drive circuits corresponding to the respective blocks, the above-described sustain pulse drive circuit of each of the sustain pulse drive circuits depends on the content of a display pattern. There is a disadvantage that the difference in the number of lighted loads causes a luminance difference for each of the blocks. Further, if the sustain period of each scanning line is different, the number of lighting of the load of each of the sustain pulse driving circuits at an arbitrary time fluctuates, so that there is a drawback that temporal luminance fluctuation occurs even in the same sustain period. is there.

It is an object of the present invention to solve the above-mentioned drawbacks and to provide a luminance compensation method for reducing the above-mentioned luminance fluctuation and luminance difference between blocks.

[0019]

According to the present invention, there is provided a brightness compensation method comprising: a scan electrode group comprising a first number of scan electrodes corresponding to a scan line of a display cell formed on the same plane; A sustain electrode group consisting of the first number of sustain electrodes and a data electrode group consisting of a plurality of data electrodes for data display which are orthogonal to the scan electrode group and the sustain electrode group and are driven by supply of display data. And an AC discharge memory type plasma display panel comprising a rare gas filled in a space between the scan electrode group and the sustain electrode group and the data electrode group. In a luminance compensation method for a driving circuit including N sustain pulse driving circuits for supplying sustain pulses which are collectively driven for each of the scan electrodes or the sustain electrodes, the N sustain pulse driving For each of the circuits, the number of the display data in a predetermined display area driven by the sustain pulse driving circuit is counted, and the count value of the number of display data is compared with a preset reference data number to erase pulse. Is characterized by controlling the timing of occurrence of.

The brightness compensation circuit according to the present invention comprises a scan electrode group consisting of a first number of scan electrodes corresponding to the scan lines of the display cells formed on the same plane, and the first number for maintaining the discharge of the display cells. A sustain electrode group consisting of a plurality of sustain electrodes, a scan electrode group, and a data electrode group consisting of a plurality of data electrodes for data display which are orthogonal to the sustain electrode group and are driven by supply of display data. A second number of the scan electrodes or a second number obtained by dividing the first number by N into a group and an AC discharge memory type plasma display panel formed by filling a space between the sustain electrode group and the data electrode group with a rare gas; Brightness for compensating for brightness variation due to variation in the number of discharges of the display cells in a drive circuit including N sustain pulse drive circuits for supplying sustain pulses, which are collectively driven for each of the sustain electrodes. A first counter which receives the supply of the first division signal and the display data, counts the number of the display data, and outputs a display data count value, the first counter being reset by the first division signal; A comparator for comparing the count value with preset reference data and outputting a difference signal between the display data count value and the reference data; and N for sharing the display data with each of the N sustain pulse driving circuits. A second counter for supplying first, second, and third division signals generated by counting scan signals corresponding to the scan lines for each field signal in order to divide the display area into a plurality of display areas; A selector for supplying N number of area difference signals in which said differential signals are selected corresponding to said N display areas in response to the supply of said divided signals, and for supplying said erase signal and said third divided signal. A distributor for supplying N number of area erasure signals corresponding to the N display areas; receiving a supply of each of the N number of area erasure signals and each of the N area difference signals; And N delay circuits for delaying each of the area erasure signals by the time designated by the area difference signal.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1 which shows a block diagram of a circuit of a first embodiment of a brightness compensation circuit for realizing the brightness compensation method of the present invention, a brightness compensation circuit 18 of the present embodiment has a display device shared by respective sustain pulse driving circuits. A counter 1 for counting the number of display data D supplied for each of the areas (blocks) A to D and outputting a count value DC; comparing the count value DC with a preset reference data R; Difference signal DF
And a scanning signal C for each field signal F for dividing the display data D into blocks and supplying signals CC, CS and CE to a counter 1, a selector 4 and a distributor 5, respectively. A selector 3 for supplying signals DFA to DFD, which select the differential signal DF corresponding to the blocks A to D in response to the supply of the signal CS, to one of the delay circuits 6A to 6D; A signal EUA corresponding to the blocks A to D in response to the supply of the signal CE.
5 for distributing / supplying EUD to each of delay circuits 6A to 6D, and signals EUA to EUD and signal DFA, respectively.
To DFD, the signals EUA to EUD are delayed by the time designated by the signals DFA to DFD, and the erase signal EA is delayed.
To ED, respectively.

PD provided with luminance compensation circuit 18 of the present embodiment
Referring to FIG. 2 showing the configuration of the P drive circuit by blocks,
PDP 10 similar to the basic PDP drive circuit shown in FIG.
, The data drivers 11 and 12, and the display area of the PDP 10 are divided into four, and each area, that is, blocks A to D
In addition to sustain pulse drive circuits 14A to 14D and 15A to 15D for supplying corresponding sustain pulses U1A to U1D, data distributor 22, and sustain signal generator 23, instead of luminance compensation circuit 18 and scan driver 38 The field signal F, the scanning signal C, and the erasing signal E from the luminance compensation circuit 18
A scan driver 13 receives supply of A to ED and sustain pulses U1A to U1D, and generates and supplies scan electrode drive pulses Si.

The operation will be described with reference to FIGS. 1 and 2 and FIG. 3 showing a driving time chart of the driving circuit of the present embodiment. The counter 1 is reset in response to the supply of the signal CC and each of the sustain pulse driving circuits is reset. 14A to 14D, 15
Display data D supplied for each of the shared blocks A to 15D
The number is counted and a count value DC is output. Since the display area of the PDP 10 is divided into four blocks A to D as described above, the sustain pulse driving circuits 14A to 14D and 15A are used.
The number of scanning lines corresponding to the shared blocks of each pair of .about.15D, that is, the number of block lines is 1/4 of the total number of scanning lines. The counter 3 counts the scanning signal C and outputs a block division signal CC for dividing the block signal into the above-mentioned block line numbers.
, The signal CS is supplied to the selector 4, and the signal CE is supplied to the distributor 5. The count value DC is compared with a reference data number R which is a standard lighting number for each block by the comparator 2, and the comparison result is supplied to the selector 4 as a difference signal DF. The selector 4 selects the difference signal DF in response to the signal CS, and supplies it as output signals DFA to DFD corresponding to the blocks A to D to the corresponding delay circuits 6A to 6D. Meanwhile, the distributor 5
Generates erase signals EUA to EUD for setting a start timing of an erase pulse when there is no luminance compensation corresponding to each of blocks A to D in response to supply of signal CE and erase signal E, and generates corresponding delay circuits 6A to EUD, respectively. 6D. Each of delay circuits 6A to 6D provides a corresponding one of signals EUA to EUA.
UD and the signals DFA to DFD are supplied, and the signal EU is supplied.
For each of A to EUD, the corresponding signal DFA to DFD outputs an erasing signal EA to ED delayed by a designated delay amount, and supplies the signal to the scanning driver 13.

Referring to FIG. 3, the basic P shown in FIG.
The repetition period t1 of the sustain period in the time chart of the DP driving circuit and each scanning pulse Cn (1 ≦ n ≦
1 which is the time from the timing of j) to the erase pulse E
In addition to sustain period t2 per scan line, scan ranges DA to DD indicating the drive range of sustain pulses U1 and V1 corresponding to blocks A to D, and sustain pulses U1 and V1 corresponding to scan ranges DA to DD, respectively. The extended periods tA to tD corresponding to the erase signals EA to ED are shown, respectively. The luminance increases in proportion to the extension periods tA to tD. These extended periods tA to tD are independent values because they are calculated for each of the blocks A to D. Therefore, luminance compensation is performed independently for each of these blocks A to D.

Next, a second embodiment of the present invention will be described. Referring to FIG. 4, which is a block diagram showing a circuit of a second embodiment of a brightness compensation circuit for realizing the brightness compensation method of the present invention, a brightness compensation circuit 19 of this embodiment includes a counter 24 for counting addresses, a display data 15 for storing
A counter 26 for counting the number of display data; a memory 27 for storing the count value of the counter 26; an adder 28 for adding the count value from the memory 27 for each scan to output additional data; , A memory 30 for storing erasure delay data, an arithmetic unit 31 for multiplying the addition data by a compensation coefficient to perform an erasure delay operation, and an erasure timing operation for erasing data DE. An arithmetic unit 32 for calculating, a read generator 33 for generating a read signal for reading the erase data DE from the memory 34, and a memory 34 for storing the erase data DE are provided.

PD provided with luminance compensation circuit 19 of this embodiment
Referring to FIG. 5, which shows the configuration of the P drive circuit by blocks,
A PDP 10 similar to the PDP drive circuit of the first embodiment,
Data drivers 11 and 12 and sustain pulse drive circuit 14
A to 14D, 15A to 15D, a data distributor 22,
In addition to the sustain signal generator 23, the luminance compensating circuit 19 in place of the luminance compensating circuit 18 and the sustain pulses U1A to U1D, the erase data clock EK and the erase data DE in response to the supply of the erase data clock in place of the scan driver 13. A shift register 37 for shifting the erase data DE by EK;
The shift register 3 responds to the erase data latch signal ER.
7, a data latch 36 for latching the erase data supplied from the scan driver 7, a scan driver 35 receiving the supply of the field signal F, the scan signal C, and the erase data from the data latch 36, and generating and supplying the scan electrode drive pulse Si. Is provided.

The operation will be described with reference to FIGS. 4 and 5. First, the field signal F is stored and delayed in the counter 24 to supply the delayed field signal AF in order to start the erasing operation after the arithmetic processing described later. Display data D
Supplies delayed display data AD which is stored and delayed in the memory 25 by the address A supplied from the address counter 24. The display data D is counted by the counter 26 for each scanning line, and the count value DL is stored in the memory 27. The adder 28 is a memory 27 corresponding to all scan lines whose sustain periods overlap each other for each scan of the blocks A to D.
Is added to the number DLR of display data to be read. Adder 28
Is the sum of the above-mentioned read display data numbers DLR and indicates a load variation state. The arithmetic unit 31 receives the addition result, multiplies the compensation result by the compensation coefficient corresponding to the load variation state indicated by the addition result, converts the result into an erasure delay time which is a delay amount of the generation timing of the erasure pulse, and stores it in the memory 30. I do. On the other hand, the memory 29 stores the generation timing of the erasing pulse for each scanning line when the load fluctuation is not compensated, that is, basic timing map data which is basic erasing data. The arithmetic unit 32 has a plurality of registers, reads out the basic erasure data corresponding to the scan line to be selected from the memory 29 for each scan, and reads one of the registers.
At the same time, the erase delay time of the scan line is read out from the memory 30 and counted. The basic erase data is held in the register during the counting of the erase delay time. Similarly, the basic erase data and the erase delay time corresponding to the next and subsequent scan lines are read out, the basic erase data is sequentially stored and held in other registers of the register, and the erase delay time is counted. The count value corresponding to all the scanning lines is stored at the current address of the memory 34 as erase data DE in synchronization with the scanning timing. The read generator 33 controls the reading of the erase data DE so as to be synchronized with the scanning timing, and at the same time, supplies the erase data clock EK and the erase data latch signal ER.

The operations of the data drivers 11 and 12, the sustain pulse driving circuits 14A to 14D and 15A to 15D, the data distributor 22 and the sustain signal generator 23 are the same as those of the first embodiment, and the description is redundant. Omitted to avoid The shift register 37 stores erase data DE corresponding to all scan lines read out for each scan in the erase data clock E.
Transferred by K. During the transfer, the data latch 36
Stores the erase data DE of the previous scan line, and the operation is selected. When the erase data DE of the next scan line is stored in all the registers of the shift register 37, the erase data latch signal ER is supplied to the data latch 36 in synchronization with the scan signal C, and the data held in the data latch 36 is input. Replace. The held data is combined with the sustain pulses U1A to U1D by the scan driver 35 supplied with the delay field signal AF and the scan signal C, and output as the scan electrode drive pulse Si.

In this embodiment, the above-described arithmetic processing enables independent luminance compensation for each scanning line.

In the above description, the two-gradation driving of the PDP has been described as an example. One field is divided into a plurality of subfields, and the number of lighting is weighted for each subfield.
It goes without saying that multi-tone display can be applied without departing from the gist of the present invention.

[0031]

As described above, the luminance compensation method and the luminance compensation circuit of the present invention count the number of display data in the display area to be driven for each of the plurality of sustain pulse driving circuits, and calculate the counted value. And the reference data number to control the generation timing of the erase pulse, so that even if the sustain pulse drive circuit is shared for a plurality of scan lines, the luminance can be compensated in accordance with the number of load lights in the above-mentioned region. Therefore, there is an effect that the luminance fluctuation can be reduced. In addition, even if the number of lighting of the load of each of the sustain pulse driving circuits is different depending on the content of the display pattern, the difference in luminance between each of the blocks can be reduced, and the entire display screen can be displayed with uniform luminance. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a luminance compensation circuit according to the present invention.

FIG. 2 is a block diagram of a PDP drive circuit including a luminance compensation circuit according to the present embodiment.

FIG. 3 is a time chart illustrating an example of an operation in the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the luminance compensation circuit of the present invention.

FIG. 5 is a block diagram of a PDP drive circuit including the luminance compensation circuit according to the present embodiment.

FIG. 6 is a cross-sectional view showing a configuration of one display cell of an AC memory type PDP.

FIG. 7 is a plan view showing an electrode arrangement of an AC memory type PDP.

FIG. 8 is a time chart showing an example of a drive voltage waveform of an AC memory type PDP.

FIG. 9 is a time chart showing a sustain period of a scanning line in two-gradation display of an AC memory type PDP.

FIG. 10 is a block diagram illustrating an example of a drive circuit of an AC memory type PDP.

FIG. 11 is a block diagram illustrating an example of a conventional luminance compensation circuit.

FIG. 12 is a time chart showing an example of a drive voltage waveform of a conventional luminance compensation circuit.

[Explanation of symbols]

1,3,24,26 counter 2 comparator 4 selector 5 distributor 6A-6D delay circuit 10,100 PDP 11,12 data driver 13,35,38 scan driver 14A-14D, 15A-15D sustain pulse drive circuit 18, Reference Signs List 19 luminance compensation circuit 22 data distributor 23 sustain signal generator 25, 27, 29, 30, 34 memory 28 adder 31, 32 arithmetic unit 36 data latch 37 shift register 39, 40 insulating substrate 41 scan electrode 42 sustain electrode 43 data Electrode 44 Discharge gas space 45 Partition wall 46 Phosphor 47, 49 Dielectric 48 Protective film 50 Display cell Sc1, Sc2, ..., Scj Scan electrode Su1, Su2, ..., Suj Sustain electrode D1, D2, ..., Dk Data electrode 101 RAM 102 Series-parallel conversion circuit 103 X-side controller driver Bas 104 Y-side controller driver 105 PDP timing generator 106 clock generator 107 the refresh counter 108 controller 109 displays data counter

Claims (4)

(57) [Claims] 1. A scan electrode group consisting of a first number of scan electrodes corresponding to a scan line of a display cell formed on the same plane and a sustain electrode consisting of the first number of sustain electrodes for sustaining discharge of the display cell. An electrode group and a data electrode group consisting of a plurality of data electrodes for data display, which are orthogonal to the scan electrode group and the sustain electrode group and are driven by supply of display data, the scan electrode group and the sustain electrode group. An AC discharge memory type plasma display panel comprising a rare gas filled in a space between the first electrode and the data electrode group.
A luminance compensation method for a driving circuit including N sustain pulse driving circuits for supplying a sustain pulse, which is collectively driven for each of the second number of the divided scanning electrodes or the sustain electrodes, wherein Count the number of the display data in a predetermined display area driven by the sustain pulse driving circuit for each of the pulse driving circuits, and compare the count value of the display data number with a preset reference data number. A brightness compensation method comprising controlling the generation timing of an erase pulse. 2. A scan electrode group comprising a first number of scan electrodes corresponding to a scan line of a display cell formed on the same plane, and a sustain electrode comprising said first number of sustain electrodes for sustaining discharge of said display cell. An electrode group and a data electrode group consisting of a plurality of data electrodes for data display, which are orthogonal to the scan electrode group and the sustain electrode group and are driven by supply of display data, the scan electrode group and the sustain electrode group. An AC discharge memory type plasma display panel comprising a rare gas filled in a space between the first electrode and the data electrode group.
The N divided sustain pulse driving circuits for supplying sustain pulses, which are collectively driven for each of the second number of the scan electrodes or the sustain electrodes, and scan data corresponding to each of the scan electrodes at one hour. A driving electrode including a scan electrode driving circuit including a register for storing, wherein a count of the number of the display data for each of the scan lines is counted, and an overlap of a sustain period which is a period of the discharge sustain for each of the scan lines is performed. The erase pulse data is generated by calculating the erase pulse delay time for each scan line by multiplying a predetermined coefficient corresponding to the scan pulse, and the erase pulse data is stored in all the registers corresponding to the scan lines for each scan cycle. A luminance compensation method. 3. A scan electrode group consisting of a first number of scan electrodes corresponding to scan lines of a display cell formed on the same plane, and a sustain electrode consisting of the first number of sustain electrodes for sustaining discharge of the display cell. An electrode group and a data electrode group consisting of a plurality of data electrodes for data display, which are orthogonal to the scan electrode group and the sustain electrode group and are driven by supply of display data, the scan electrode group and the sustain electrode group. An AC discharge memory type plasma display panel comprising a rare gas filled in a space between the first electrode and the data electrode group.
The N number of sustain pulse driving circuits for supplying sustain pulses that are collectively driven in common for each of the second number of the divided scan electrodes or the sustain electrodes; A luminance compensating circuit for compensating luminance fluctuations caused by the first divided signal and the display data;
A first counter which is reset by the division signal of (a) and counts the number of the display data and outputs a display data count value; and compares the display data count value with predetermined reference data to compare the display data count value and the reference data. And a comparator for outputting a difference signal from the scan line corresponding to the scan line for each field signal in order to divide the display data into N display regions shared by the N sustain pulse driving circuits. A second counter for supplying first, second, and third divided signals generated by counting signals; and a differential signal corresponding to the N display areas in response to the supply of the second divided signal. A selector for supplying the selected N region difference signals; and an N region corresponding to the N display regions in response to the supply of the erase signal for stopping the discharge and the third division signal. A distributor for supplying an erasing signal; a time for receiving each of the N area erasing signals and each of the N area difference signals and specifying each of the N area erasing signals as the area difference signal; And N delay circuits each of which delays by a corresponding amount. 4. A scan electrode group comprising a first number of scan electrodes corresponding to scan lines of a display cell formed on the same plane, and a sustain electrode comprising said first number of sustain electrodes for sustaining discharge of said display cell. An electrode group and a data electrode group consisting of a plurality of data electrodes for data display, which are orthogonal to the scan electrode group and the sustain electrode group and are driven by supply of display data, the scan electrode group and the sustain electrode group. An AC discharge memory type plasma display panel comprising a rare gas filled in a space between the first electrode and the data electrode group.
N sustain pulse driving circuits for supplying a sustain pulse, which are collectively driven for each of the second number of the divided scan electrodes or the sustain electrodes, and scan data corresponding to each of the scan electrodes are stored. In a luminance compensation circuit of a driving circuit including a scan electrode driving circuit including a register, a first counter for delaying a field signal, a first memory for storing the display data, and counting and counting the number of the display data The second to output numerical values
A second memory for storing the count value, an adder for adding the count value read from the second memory for each scan and outputting addition data, and a device for stopping the discharge. A third memory storing basic timing map data of an erasing pulse, a first computing unit for multiplying the added data by a predetermined luminance compensation coefficient to perform an erasing delay operation to calculate erasing delay data, A fourth memory for storing data, a second calculator for calculating erase data by calculating an erase timing which is a timing for receiving the supply of the basic timing map data and the erase delay data and stopping the discharge, and A fifth memory for storing the erase data, and a read generator for generating a read signal for reading the erase data from the fifth memory. Luminance compensation circuit, characterized in that it comprises a motor.