JPH0260224B2 - - Google Patents
Info
- Publication number
- JPH0260224B2 JPH0260224B2 JP61254180A JP25418086A JPH0260224B2 JP H0260224 B2 JPH0260224 B2 JP H0260224B2 JP 61254180 A JP61254180 A JP 61254180A JP 25418086 A JP25418086 A JP 25418086A JP H0260224 B2 JPH0260224 B2 JP H0260224B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- inp
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 20
- 230000005669 field effect Effects 0.000 claims description 17
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 16
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 21
- 239000013078 crystal Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 101100026178 Caenorhabditis elegans egl-3 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910008812 WSi Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- -1 aluminum-indium-arsenic Chemical compound 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、高周波増幅回路、高速集積回路、光
電子集積回路等に応用される電界効果トランジス
タに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor applied to high frequency amplifier circuits, high speed integrated circuits, optoelectronic integrated circuits, and the like.
［従来の技術］
ヘテロ接合界面に形成される２次元電子を用い
たトランジスタとしては、従来から、いくつかの
ものが提案されている。たとえば、特公昭59−
53714、特開昭56−45079およびジヤパニーズ・ジ
ヤーナル・オブ・アプライド・フイジツクス
（Japanese Journal of Applied Physics）第19
巻、1980年、L225頁などに記載されており、基
板としてはガリウム・砒素が用いられている。基
板としてガリウム・砒素を用いた場合、室温での
２次元電子の移動度は8000cm2／Ｖ・sec程度であ
る。これに対して、インジウム・リン（以下InP
と記す）を基板として用いた場合には、室温での
２次元電子の移動度は12000cm2／Ｖ・secとなり、
高周波特性や増幅率の優れた電界効果トランジス
タが実現できる。InPを基板とする２次元電子ト
ランジスタとしては、IEEE・エレクトロン・デ
バイス・レターズ（Electron Device Letters）
Ｃ・Ｙ・Chen等、EGL−３巻、1982年、152頁に
記載されたものが知られている。[Prior Art] Several transistors have been proposed in the past that use two-dimensional electrons formed at a heterojunction interface. For example, the
53714, Japanese Patent Publication No. 56-45079 and Japanese Journal of Applied Physics No. 19
Vol., 1980, page L225, etc., and gallium arsenic is used as the substrate. When gallium/arsenic is used as the substrate, the two-dimensional electron mobility at room temperature is about 8000 cm 2 /V·sec. In contrast, indium phosphide (hereinafter referred to as InP)
) is used as a substrate, the two-dimensional electron mobility at room temperature is 12000cm 2 /V・sec,
A field effect transistor with excellent high frequency characteristics and amplification factor can be realized. For two-dimensional electronic transistors using InP as a substrate, see IEEE Electron Device Letters.
The one described in C. Y. Chen et al., EGL-3, 1982, p. 152 is known.
第２図に、InPを基板とした従来の２次元電子
トランジスタの構成を断面図で示す。第２図にお
いて、InP基板２１上には、不純物無添加のアル
ミニウム・インジウム・砒素混晶半導体層（以下
AlInAs層と記す）２２、ガリウム・インジウ
ム・砒素混晶半導体層（以下GaInAs層と記す）
２３、ｎ型不純物が添加されたAlInAs層２４が
順次形成されている。AlInAs層２４上には、制
御電極２６が設けられており、該制御電極２６の
両側にはソース電極２７およびドレイン電極２８
が設けられている。GaInAs層２３とｎ型の
AlInAs層２４の界面には、２次元電子層２５が
形成されており、この２次元電子層２５を用いて
電界効果トランジスタが構成されている。 FIG. 2 shows a cross-sectional view of the structure of a conventional two-dimensional electronic transistor using InP as a substrate. In FIG. 2, an impurity-free aluminum-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as
22, gallium-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as GaInAs layer)
23. AlInAs layers 24 doped with n-type impurities are successively formed. A control electrode 26 is provided on the AlInAs layer 24, and a source electrode 27 and a drain electrode 28 are provided on both sides of the control electrode 26.
is provided. GaInAs layer 23 and n-type
A two-dimensional electronic layer 25 is formed at the interface of the AlInAs layer 24, and a field effect transistor is constructed using this two-dimensional electronic layer 25.
［発明が解決しようとする問題点］
しかしながら、以上説明した従来の電界効果ト
ランジスタでは、InP基板２１中の不純物が
AlInAs層２２中に拡散し、このため電界効果ト
ランジスタの特性として、良好なピンチオフ特性
が得られにくいという問題点があつた。また、電
界効果トランジスタの特性が、基板による影響を
受けやすく、基板のロツトによるばらつきを生じ
やすいという問題点もあつた。[Problems to be Solved by the Invention] However, in the conventional field effect transistor described above, impurities in the InP substrate 21
It diffuses into the AlInAs layer 22, and as a result, there is a problem in that it is difficult to obtain good pinch-off characteristics as a characteristic of a field effect transistor. Another problem was that the characteristics of the field effect transistor were easily influenced by the substrate and were likely to vary depending on the substrate lot.
それゆえに、本発明の目的は、ピンチオフ特性
の良好な、かつ基板のロツトごとによるばらつき
の少ない電界効果トランジスタを提供することに
ある。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a field effect transistor with good pinch-off characteristics and with less variation from one substrate lot to another.
［問題点を解決するための手段］
本発明の電界効果トランジスタでは、InP基板
上に、ｎ型不純物が添加されたInP層を形成し、
該InP層上に不純物が添加されていないGaInAs
層を形成し、該GaInAs層上にAlInAs層を形成し
て、該AlInAs層上に制御電極を設け、該制御電
極の両側にGaInAs層に対して抵抗性接触となる
ソース電極およびドレイン電極を設けている。[Means for solving the problems] In the field effect transistor of the present invention, an InP layer doped with an n-type impurity is formed on an InP substrate,
GaInAs with no impurities added on the InP layer
forming an AlInAs layer on the GaInAs layer, providing a control electrode on the AlInAs layer, and providing a source electrode and a drain electrode on both sides of the control electrode to be in resistive contact with the GaInAs layer. ing.
［作用］
本発明の電界効果トランジスタでは、ｎ型InP
層とGaInAs層との界面に、２次元電子層が形成
される。この２次元電子層の電子密度を制御する
ため、制御電極を設けなければならないが、この
制御電極は整流性接触であることが必要である。
整流性接触としては、一般にシヨツトキー接触が
用いられているが、GaInAs層に対してシヨツト
キー接触を形成することは一般に困難である。そ
こで、本発明では、GaInAs層に対して直接にシ
ヨツトキー接触を形成して整流性接触を得るので
はなく、整流性接触の得やすいAlInAs層を
GaInAs層上に形成した後、制御電極を形成して
いる。ここで、AlInAs層は、不純物無添加、ｐ
型またはｎ型のいずれであつてもよく、所要特性
によつて伝導型が選択される。たとえば、電界効
果トランジスタの制御電極への入力電圧耐圧を向
上させたいときには、不純物無添加が良く、しき
い値電圧を正にしたいときにはｐ型が選ばれる。
また、ドレイン電流として大きな値を得たいとき
はｎ型が選ばれる。[Function] In the field effect transistor of the present invention, n-type InP
A two-dimensional electronic layer is formed at the interface between the GaInAs layer and the GaInAs layer. In order to control the electron density of this two-dimensional electron layer, a control electrode must be provided, and this control electrode needs to be a rectifying contact.
A shot key contact is generally used as a rectifying contact, but it is generally difficult to form a shot key contact with a GaInAs layer. Therefore, in the present invention, instead of directly forming a shot key contact with the GaInAs layer to obtain a rectifying contact, we use an AlInAs layer that is easy to obtain a rectifying contact.
After forming on the GaInAs layer, a control electrode is formed. Here, the AlInAs layer is free of impurities and p
The conductivity type may be either type or n-type, and the conductivity type is selected depending on the required characteristics. For example, when it is desired to improve the input voltage withstand voltage to the control electrode of a field effect transistor, no impurity is added, and when it is desired to make the threshold voltage positive, p-type is selected.
Furthermore, when a large value of drain current is desired, n-type is selected.
本発明では、InP基板上にｎ型InP層が形成さ
れているため、InP基板から拡散する不純物の影
響を少なくすることができる。一般に、InP基板
から拡散する不純物密度は、1016cm-3程度であ
り、拡散深さは300Å程度である。したがつて、
それ以上の層の厚みおよびｎ型不純物密度とする
ことにより、基板から拡散する不純物の影響を少
なくすることができる。 In the present invention, since the n-type InP layer is formed on the InP substrate, the influence of impurities diffused from the InP substrate can be reduced. Generally, the impurity density diffused from the InP substrate is about 10 16 cm -3 and the diffusion depth is about 300 Å. Therefore,
By making the layer thicker and the n-type impurity density larger than this, the influence of impurities diffused from the substrate can be reduced.
［実施例］
第１図は、本発明の一実施例を説明するための
断面図である。半絶縁性InP基板１上に、有機金
属気相成長法あるいはガスソースMBE
（Molecular−beam epitaxy）法により、基板温
度600℃〜650℃において、Si、Ｓ、Seなどのｎ
型不純物を添加したInP層２を形成する。ここ
で、ｎ型不純物の密度は１×1017cm-3〜５×1018
cm-3程度とし、層の厚みは500Å〜2000Å範囲と
する。次に、不純物無添加のGaInAs層３を200
Å〜2000Å程度の厚さで形成し、AlInAs層４を
200Å〜2000Åの範囲の厚さで形成する。[Example] FIG. 1 is a sectional view for explaining an example of the present invention. Metal organic vapor phase epitaxy or gas source MBE is applied on the semi-insulating InP substrate 1.
Using the (Molecular-beam epitaxy) method, the substrate temperature is 600°C to 650°C.
An InP layer 2 doped with type impurities is formed. Here, the density of n-type impurity is 1×10 17 cm -3 to 5×10 18
cm -3 and the layer thickness is in the range of 500 Å to 2000 Å. Next, the impurity-free GaInAs layer 3 is
The AlInAs layer 4 is formed with a thickness of about 2,000 Å to 2,000 Å.
It is formed with a thickness in the range of 200 Å to 2000 Å.
AlInAs層４をｐ型にする際には、不純物とし
てMn、Mg、Znが用いられ、ｎ型にする際には
Si、Ｓ、Seなどが用いられる。ｐ型およびｎ型
のいずれの場合でも、不純物密度としては、1016
cm-3〜1018cm-3程度にされる。 When making the AlInAs layer 4 p-type, Mn, Mg, and Zn are used as impurities, and when making it n-type, Mn, Mg, and Zn are used as impurities.
Si, S, Se, etc. are used. In both p-type and n-type cases, the impurity density is 10 16
cm -3 to 10 18 cm -3 .
GaInAs層３およびAlInAs層４の混晶組成は、
InP基板との格子不整が0.1％以下になるようにす
る。 The mixed crystal composition of the GaInAs layer 3 and the AlInAs layer 4 is
Ensure that the lattice mismatch with the InP substrate is 0.1% or less.
さらに、AuGe合金よりなる抵抗性接触金属を
蒸着し、たとえば4000℃で合金化することによ
り、ソース電極７およびドレイン電極８を形成す
る。最後に、たとえばAl、Pt、Au、Ｗ、WSiな
どから選ばれた制御電極６を、蒸着法などにより
形成して完成させる。 Further, a resistive contact metal made of an AuGe alloy is deposited and alloyed at, for example, 4000° C., thereby forming a source electrode 7 and a drain electrode 8. Finally, a control electrode 6 selected from, for example, Al, Pt, Au, W, WSi, etc. is formed by vapor deposition or the like to complete the process.
［発明の効果］
本発明の電界効果トランジスタでは、InP基板
上にｎ型InP層が形成されているため、InP基板
から拡散する不純物の影響を少なくすることがで
きる。したがつて、この発明によれば、再現性良
く、高周波特性・増幅特性の優れた電界効果トラ
ンジスタとすることができる。[Effects of the Invention] In the field effect transistor of the present invention, since the n-type InP layer is formed on the InP substrate, the influence of impurities diffused from the InP substrate can be reduced. Therefore, according to the present invention, a field effect transistor with good reproducibility and excellent high frequency characteristics and amplification characteristics can be obtained.
第１図は、本発明の一実施例を説明するための
断面図である。第２図は、従来の電界効果トラン
ジスタを示す断面図である。
図において、１はInP基板、２はｎ型InP層、
３はGaInAs層、４はAlInAs層、５は２次元電子
層、６は制御電極、７はソース電極、８はドレイ
ン電極を示す。
FIG. 1 is a sectional view for explaining one embodiment of the present invention. FIG. 2 is a sectional view showing a conventional field effect transistor. In the figure, 1 is an InP substrate, 2 is an n-type InP layer,
3 is a GaInAs layer, 4 is an AlInAs layer, 5 is a two-dimensional electron layer, 6 is a control electrode, 7 is a source electrode, and 8 is a drain electrode.
Claims (1)
層を形成し、該InP層上に不純物が添加されてい
ないGaInAs層を形成し、該GaInAs層上に
AlInAs層を形成して、該AlInAs層上に制御電極
を設け、該制御電極の両側に前記GaInAs層に対
して抵抗性接触となるソース電極およびドレイン
電極を設けたことを特徴とする、電界効果トラン
ジスタ。 ２ 前記AlInAs層に不純物が添加されていない
ことを特徴とする、特許請求の範囲第１項記載の
電界効果トランジスタ。 ３ 前記AlInAs層の伝導型がｐ型であることを
特徴とする、特許請求の範囲第１項記載の電界効
果トランジスタ。 ４ 前記AlInAs層の伝導型がｎ型であることを
特徴とする、特許請求の範囲第１項記載の電界効
果トランジスタ。[Claims] 1. InP doped with n-type impurities on an InP substrate
a GaInAs layer to which no impurity is added is formed on the InP layer, and a GaInAs layer to which no impurities are added is formed on the InP layer;
A field effect device characterized in that an AlInAs layer is formed, a control electrode is provided on the AlInAs layer, and a source electrode and a drain electrode that are in resistive contact with the GaInAs layer are provided on both sides of the control electrode. transistor. 2. The field effect transistor according to claim 1, wherein no impurity is added to the AlInAs layer. 3. The field effect transistor according to claim 1, wherein the conductivity type of the AlInAs layer is p-type. 4. The field effect transistor according to claim 1, wherein the conductivity type of the AlInAs layer is n-type.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61254180A JPS63107172A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
| EP87115444A EP0264932A1 (en) | 1986-10-24 | 1987-10-21 | Field effect transistor |
| CA000550121A CA1261977A (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
| KR1019870011772A KR900008154B1 (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61254180A JPS63107172A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107172A JPS63107172A (en) | 1988-05-12 |
| JPH0260224B2 true JPH0260224B2 (en) | 1990-12-14 |
Family
ID=17261341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61254180A Granted JPS63107172A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107172A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2965358B2 (en) * | 1995-11-09 | 1999-10-18 | 松下電子工業株式会社 | Field-effect transistor |
-
1986
- 1986-10-24 JP JP61254180A patent/JPS63107172A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63107172A (en) | 1988-05-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |