JPH0260138A - Board for semiconductor element mounting use - Google Patents
Board for semiconductor element mounting useInfo
- Publication number
- JPH0260138A JPH0260138A JP21043388A JP21043388A JPH0260138A JP H0260138 A JPH0260138 A JP H0260138A JP 21043388 A JP21043388 A JP 21043388A JP 21043388 A JP21043388 A JP 21043388A JP H0260138 A JPH0260138 A JP H0260138A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- film
- insulating layer
- semiconductor element
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229920006015 heat resistant resin Polymers 0.000 claims abstract description 17
- 239000000126 substance Substances 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 abstract description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 abstract description 4
- 239000011889 copper foil Substances 0.000 abstract description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010292 electrical insulation Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000000053 physical method Methods 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000011344 liquid material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003980 solgel method Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000004693 Polybenzimidazole Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 229920002480 polybenzimidazole Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体素子実装用基板に関するものであり、と
くに、接着剤を不要とする構造の半導体素子実装用基板
に好適な耐熱性の樹脂フィルムおよびそれを使用した半
導体素子の実装用基板に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a substrate for mounting semiconductor elements, and in particular to a heat-resistant resin film suitable for a substrate for mounting semiconductor elements having a structure that does not require an adhesive, and a heat-resistant resin film using the same. The present invention relates to a substrate for mounting semiconductor elements used.
近年、半導体素子を基板に実装する技術の進歩は急激で
ある。特にテープ自動配線接続（ＴａｐｅＡｕｔｏｍａ
ｔｅｄ Ｂｏｎｄｉｎｇ 、以下ＴＡＢと略称する）は
集積回路を形成された半導体素子（以下ＩＣチップと略
称する）を半導体素子実装用の回路基板にワイヤボンデ
ィングなしで、接続する技術であり、５００〜６００個
と云う多数の外部接続配線数を有するＩＣチップの配線
接続を一度に可能にするため、高密度の実装技術が必要
とされている現在、研究開発が活発に進められている。In recent years, there has been rapid progress in technology for mounting semiconductor elements on substrates. Especially tape automatic wiring connection (TapeAutoma)
ted Bonding (hereinafter abbreviated as TAB) is a technology that connects semiconductor elements formed with integrated circuits (hereinafter abbreviated as IC chips) to a circuit board for mounting semiconductor elements without wire bonding. Currently, research and development are actively progressing as high-density packaging technology is required to enable wiring connections for IC chips having such a large number of external connection wirings at once.
ＴＡＢに用いる基板の方式には二層構造と三層構造があ
るが、いずれの構造においても第３図ａ（二層構造）お
よび第３図ｂ（三層構造）に示されるように、ＩＣチッ
プが実装される位置において樹脂フィルム３は穴あけ加
工を施さねばならない、これは、耐熱性の樹脂フィルム
といえども、ＩＣチップ実装時の温度に耐えることが困
難であるからである。There are two types of substrates used for TAB: two-layer structure and three-layer structure, but in both structures, the IC The resin film 3 must be perforated at the location where the chip is to be mounted. This is because even a heat-resistant resin film has difficulty withstanding the temperature at which the IC chip is mounted.
しかして、穴あけ加工は、二層構造と三層構造において
、それぞれ異なる方式で行われている。Therefore, drilling is performed using different methods for the two-layer structure and the three-layer structure.
二層構造のＴＡＢにおいては、樹脂フィルムは工ッチン
グ加工により穴あけ加工が行われている。In the TAB having a two-layer structure, holes are formed in the resin film by etching.
しかしながら、耐熱性の樹脂フィルムの場合、このエツ
チングは困難である。一般的にＴＡＢに利用される耐熱
性の樹脂フィルムは耐薬品性にもすぐれているからであ
る。これに対して、三層構造のＴＡＢにおいては、あら
かじめ型抜きやパンチング等により穴あけ加工を行うこ
とができるので、従来技術においては、もっばら、この
三層構造のＴＡＢが半導体の実装用に用いられてきた。However, in the case of heat-resistant resin films, this etching is difficult. This is because the heat-resistant resin film generally used for TAB also has excellent chemical resistance. On the other hand, in the case of a TAB with a three-layer structure, holes can be formed in advance by die-cutting, punching, etc., so in the conventional technology, this TAB with a three-layer structure is mainly used for mounting semiconductors. I've been exposed to it.
しかしながら、この三層構造のＴＡＢは、−船釣に銅箔
と耐熱性の樹脂フィルムを接着剤で貼り合わせたもので
あり、耐熱性の低い接着剤を用いているために、ＴＡＢ
としての耐熱性は樹脂フィルムの耐熱性よりも低下する
という大きい問題点を有している。このために、接着剤
を不要にする構造のＴＡＢによる実装技術の開発が望ま
れており、従来は、接着剤が不要である三層構造におい
て、耐熱性の樹脂フィルムのエツチング技術が盛んに検
討されてきた。However, this three-layer structure TAB is made by bonding copper foil and heat-resistant resin film with adhesive, and because it uses an adhesive with low heat resistance, TAB
A major problem is that the heat resistance of the resin film is lower than that of the resin film. For this reason, it is desired to develop mounting technology using TAB with a structure that eliminates the need for adhesives, and conventionally, for three-layer structures that do not require adhesives, etching technology for heat-resistant resin films has been actively studied. It has been.
本発明者等は、エツチング技術そのものを不要にする技
術を開発すべく、ＴＡＢの実装工程を鋭意検討した結果
、ＩＣチップの実装において、必要とされる熱負荷に耐
えるには、５００°Ｃにおいて、約１秒の耐熱性を有す
れば、実質的に充分であり、該耐熱性は特定の絶縁層を
形成することにより与えられることを見出した０本発明
はかかる知見に基づきなされるに到ったものである。In order to develop a technology that eliminates the need for etching technology itself, the inventors of the present invention have carefully studied the TAB mounting process. It has been found that a heat resistance of about 1 second is substantially sufficient, and that this heat resistance can be provided by forming a specific insulating layer.The present invention was made based on this knowledge. This is what happened.
すなわち、本発明は、
耐熱性の樹脂フィルム上に、無機物質からなる絶縁層を
形成したことを特徴とする半導体素子の実装用の基板に
好適なフィルム、であり、また、耐熱性の樹脂フィルム
上に、無機物質からなる絶縁層を形成し、さらに該絶縁
層の上に導電性薄膜を形成してなることを特徴とする半
導体素子の実装用の基板、である。That is, the present invention is a film suitable for a substrate for mounting a semiconductor element, characterized in that an insulating layer made of an inorganic substance is formed on a heat-resistant resin film, and also a heat-resistant resin film. This is a substrate for mounting a semiconductor element, characterized in that an insulating layer made of an inorganic substance is formed thereon, and a conductive thin film is further formed on the insulating layer.
本発明は、第１図に示したように、耐熱性の樹脂フィル
ム１上に、無機物質からなる絶縁層２を形成した半導体
素子の実装用の基板に好適なフィルム、であり、また、
耐熱性の樹脂フィルム２上に、無機物質からなる絶縁層
２を形成し、さらに該絶縁層の上に導電性薄膜３を形成
してなる半導体素子の実装用の基板、である。As shown in FIG. 1, the present invention is a film suitable for a substrate for mounting semiconductor elements, in which an insulating layer 2 made of an inorganic substance is formed on a heat-resistant resin film 1, and
This is a substrate for mounting a semiconductor element, which is formed by forming an insulating layer 2 made of an inorganic material on a heat-resistant resin film 2, and further forming a conductive thin film 3 on the insulating layer.
本発明において、耐熱性Ｏ樹脂フィルム１としては、ポ
リイミド、ポリイミドアミド、ポリエチレンテレフタレ
ート、ポリエチレンナフタレート、ポリパラバン酸、ポ
リヒダントイン、ポリベンゾイミダゾール等の樹脂フィ
ルムを有効に用いることができる。In the present invention, as the heat-resistant O resin film 1, resin films such as polyimide, polyimide amide, polyethylene terephthalate, polyethylene naphthalate, polyparabanic acid, polyhydantoin, polybenzimidazole, etc. can be effectively used.
本発明の無機物質からなる絶縁層２の形成に用いること
のできる材料は酸化物、窒化物、炭化物等であり、具体
的には、酸化珪素、酸化アルミ、酸化チタン、酸化タン
タル、窒化珪素、窒化アルミ、炭化珪素等の電気絶縁性
の材料を有効に用いることができる。絶縁層を耐熱フィ
ルム上に形成するには、物理的な手法、化学的な手法の
いずれでもよい、物理的な手法としては、スパッタリン
グや蒸着があり、化学的な手法としては、化学気相堆積
法（ＣＶＤ法）、プラズマ化学気相堆積法（ＰＣＶＤ法
）のような気相成長、ゾルゲル法、浸漬法のように液状
の材料からの薄膜形成等の手法を有効に用いることがで
きる。好ましくは、低温での薄膜形成を可能にするスパ
ッタリングや蒸着、化学気相堆積法、プラズマ化学気相
堆積法等の形成法をもちいる。該絶縁層はＴＡＢプロセ
スにおける熱負荷に耐える性質好ましくは、上記したご
と＜５００°Ｃにおいて１秒間の耐熱性を付与するもの
であり、このために、絶縁層の厚みは０．０１〜２０μ
国、好ましくは、０．１〜１５μｍである。Materials that can be used to form the insulating layer 2 made of an inorganic substance of the present invention include oxides, nitrides, carbides, etc. Specifically, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, silicon nitride, Electrically insulating materials such as aluminum nitride and silicon carbide can be effectively used. To form an insulating layer on a heat-resistant film, either physical or chemical methods can be used. Physical methods include sputtering and vapor deposition, and chemical methods include chemical vapor deposition. Techniques such as vapor phase growth such as (CVD method), plasma chemical vapor deposition method (PCVD method), sol-gel method, and thin film formation from a liquid material such as immersion method can be effectively used. Preferably, a formation method such as sputtering, vapor deposition, chemical vapor deposition, plasma chemical vapor deposition, or the like is used that enables thin film formation at low temperatures. The insulating layer has the property of being able to withstand the heat load in the TAB process, preferably providing heat resistance for 1 second at <500°C as described above, and for this purpose, the thickness of the insulating layer is 0.01 to 20 μm.
The diameter is preferably 0.1 to 15 μm.
本発明の一つは、以上説明したように、耐熱性フィルム
上にこのような絶縁層を形成した半導体素子の実装用の
基板に好適なフィルム、である。As explained above, one aspect of the present invention is a film suitable for a substrate for mounting semiconductor elements, in which such an insulating layer is formed on a heat-resistant film.
本発明の他のひとつは、当該無機物質からなる絶縁層の
上に電気回路用の導電性の薄膜を形成したものである。Another aspect of the present invention is that a conductive thin film for an electric circuit is formed on the insulating layer made of the inorganic substance.
この回路形成用の導電性薄膜の材料としては、銅、ニッ
ケル、銀、アルミニウム、クロム等の金属やこれらの合
金を有効に用いることができる。当該金属や合金を薄膜
にする場合、当然のことながら、二種類以上の導電性薄
膜を積雇して用いることもできる。薄膜の形成法として
は、物理的な手法、化学的な手法のいずれでもよい、物
理的な手法としては、スパッタリングや蒸着等があり、
化学的な手法としては、化学気相堆積法（ＣＶＤ法）、
プラズマ化学気相堆積法（ＰＣＶＤ法）のような気相成
長、ゾルゲル法、無電解メツキ法、電気メツキ法、浸漬
法のように液状の材料からの薄膜形成等の手法を有効に
用いることができる。好ましくは、低温での薄膜形成を
可能にするスパッタリングや蒸着、化学気相堆積法、プ
ラズマ化学気相堆積法、無電解メツキ法、電気メツキ法
等の形成法をもちいる。また、これらの形成法を複合し
て用いることもできる。たとえば、スパッタリング法で
薄膜を形成したあとで、メツキ法により膜厚を数十倍に
厚（することもできる、導電性薄膜の厚みは特に限定さ
れる条件ではない、なお、電気回路としては、基本的に
は、０．１μ−程度の膜厚で充分であるが、ＩＣチップ
実装用として、ＴＡＢに用いるために、好ましくは、０
．５〜３５μ糟程度 である、導電性薄膜の膜厚が薄く
なれば、電気回路のパターンを微細にできることは、当
業者が容易に理解できることである。As the material for the conductive thin film for forming the circuit, metals such as copper, nickel, silver, aluminum, chromium, and alloys thereof can be effectively used. When forming a thin film from the metal or alloy, it is of course possible to use two or more types of conductive thin films stacked together. The method for forming a thin film may be either a physical method or a chemical method. Physical methods include sputtering, vapor deposition, etc.
Chemical methods include chemical vapor deposition method (CVD method),
Methods such as vapor phase growth such as plasma chemical vapor deposition (PCVD), sol-gel method, electroless plating method, electroplating method, and thin film formation from liquid materials such as immersion method can be effectively used. can. Preferably, a formation method such as sputtering, vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, electroless plating, or electroplating is used that enables thin film formation at low temperatures. Further, a combination of these formation methods can also be used. For example, after forming a thin film using the sputtering method, the film thickness can be made several tens of times thicker using the plating method.The thickness of the conductive thin film is not particularly limited.However, as an electric circuit, Basically, a film thickness of about 0.1μ is sufficient, but for IC chip mounting and TAB use, it is preferably 0.1μ.
．． Those skilled in the art can easily understand that if the thickness of the conductive thin film is reduced, which is about 5 to 35 μm, the pattern of the electric circuit can be made finer.
本発明の好ましい実施態様を第２図において説明する。A preferred embodiment of the invention is illustrated in FIG.
第２図ａは、第１図と同様耐熱性の樹脂フィルムｌ上に
、無機物質からなる絶縁層２および導電性薄膜３を形成
した半導体素子の実装用の基板であり、これが本発明の
一つである。さらに、第２図すは、ＩＣチップを実装で
きるように銅箔３の不必要な部分を常法により、除去し
たところの断面図を示すものである。第２図ＣはＩＣチ
ップ４を実装した時の断面図であり、本発明の適用例で
ある。第１図ならびに第２図において、縦、横のサイズ
は任意に選択されており、とくに断面図においては、説
明を容易にするために、材料の厚みを拡大強調している
ことが注意されるべきである。FIG. 2a shows a substrate for mounting a semiconductor element, in which an insulating layer 2 made of an inorganic substance and a conductive thin film 3 are formed on a heat-resistant resin film l, similar to that shown in FIG. 1. It is one. Further, FIG. 2 shows a cross-sectional view of the copper foil 3 in which unnecessary portions have been removed by a conventional method so that an IC chip can be mounted thereon. FIG. 2C is a sectional view when the IC chip 4 is mounted, and is an application example of the present invention. In Figures 1 and 2, the vertical and horizontal sizes are arbitrarily selected, and it should be noted that in cross-sectional views in particular, the thickness of the material is enlarged and emphasized for ease of explanation. Should.
以下、実施例により、本発明の実施の態様をさらに詳細
に説明する。Hereinafter, embodiments of the present invention will be explained in more detail with reference to Examples.
〔実施例１〕
１２５μｍのポリイミドフィルム上に、酸化珪素をスパ
ッタリングにより膜厚０．２μｍ形成し本発明の半導体
素子の実装用の基板に好適なフィルムを得た。この上か
ら、ニッケルをスパッタリングにより、１．０μｍの膜
厚に形成した。ついで、銅を無電解メツキによりニッケ
ル上に１０μｍ形成し本発明の半導体素子の実装用の基
板を得た。銅およびニッケルを塩化第二鉄を用いてエツ
チング除去して、回路を形成した。この回路に、ＩＣチ
ップを実装するかわりに、５００°Ｃに加熱した銅の棒
を１秒間接触させて、耐熱性をテストした。テスト後、
耐熱性フィルムには外観ならびに電気的な性質の劣化は
全く観察されず、ＩＣチップの実装に充分耐える耐熱性
を有していることが明らかとなった。[Example 1] Silicon oxide was formed to a thickness of 0.2 μm on a 125 μm polyimide film by sputtering to obtain a film suitable for a substrate for mounting a semiconductor element of the present invention. On top of this, nickel was formed by sputtering to a thickness of 1.0 μm. Next, copper was formed on the nickel to a thickness of 10 μm by electroless plating to obtain a substrate for mounting the semiconductor element of the present invention. The copper and nickel were etched away using ferric chloride to form the circuit. Instead of mounting an IC chip on this circuit, a copper rod heated to 500°C was brought into contact with the circuit for 1 second to test its heat resistance. After the test,
No deterioration in appearance or electrical properties was observed in the heat-resistant film, and it was revealed that the film had heat resistance sufficient to withstand mounting of IC chips.
〔実施例２〕
７５μｍのポリイミドフィルム上に、ジシランおよび二
酸化炭素を原料としてプラズマ化学堆積法により、ポリ
イミドフィルムの温度を２００℃として、酸化珪素薄膜
を２μｍ形成し、本発明の半導体素子の実装用の基板に
好適なフィルムを得た。酸化珪素薄膜形成後、銅をスパ
ッタリングにより膜厚０．５μｍ形成し、さらに、当該
銅薄膜上に銅を無電解メツキにより４．０μｍ形成し本
発明の半導体素子の実装用の基板を得た。ついで、当該
ｗ４ｍ膜をエツチング除去して、回路を形成した。実施
例１と同じ耐熱性のテストを実施し、同様の結果を得た
ことにより、プラズマ化学堆積法により形成される酸化
珪素も本発明において、有効であることが確認された。[Example 2] A 2 μm silicon oxide thin film was formed on a 75 μm polyimide film using disilane and carbon dioxide as raw materials by plasma chemical deposition at a temperature of 200° C., and was used for mounting the semiconductor element of the present invention. A film suitable for the substrate was obtained. After the silicon oxide thin film was formed, copper was formed to a thickness of 0.5 μm by sputtering, and then copper was further formed to a thickness of 4.0 μm by electroless plating on the copper thin film to obtain a substrate for mounting the semiconductor element of the present invention. Then, the w4m film was removed by etching to form a circuit. The same heat resistance test as in Example 1 was conducted and similar results were obtained, confirming that silicon oxide formed by plasma chemical deposition is also effective in the present invention.
以上の実施例から明らかなように、本発明は接着剤を不
要にする構造の基板を提供するものであり、従来のＴＡ
Ｂ技術において、困難であった耐熱性の樹脂フィルムの
エツチングを不要とするものであるから、今後のＴＡＢ
技術を大幅に進展させ、高密度実装技術にきわめて、貢
献するものである。すなわち、その産業上の利用可能性
はきわめて大きいものであると言わざるを得ない。As is clear from the above embodiments, the present invention provides a substrate with a structure that eliminates the need for adhesives, and
Since this technology eliminates the need for etching the heat-resistant resin film, which was difficult in technology B, future TAB
This will significantly advance the technology and greatly contribute to high-density packaging technology. In other words, it must be said that its industrial applicability is extremely large.
第１図は本発明の実施の態様を示す断面図である。第２
図ａ〜第２図Ｃは本発明をＴＡＢに使用するときの実施
の態様を示す断面図である。第３図ａおよび第３図すは
従来技術によるＴＡＢ用の基板の例を示す断面図である
０図中、１・・・・・・・・・−・耐熱性の樹脂フィル
ム、２ 無機物質の絶縁層、３ ｗ４箔、４
ＩＣチップ、５接着剤、を示す。
第１図
第２図FIG. 1 is a sectional view showing an embodiment of the present invention. Second
Figures a to 2C are cross-sectional views showing embodiments of the present invention when used in a TAB. Figures 3a and 3 are cross-sectional views showing examples of TAB substrates according to the prior art. Insulating layer, 3 W4 foil, 4
An IC chip and 5 adhesives are shown. Figure 1 Figure 2
Claims (2)
縁層を形成したことを特徴とする半導体素子の実装用の
基板に好適なフィルム。(1) A film suitable for a substrate for mounting semiconductor elements, characterized in that an insulating layer made of an inorganic substance is formed on a heat-resistant resin film.
縁層を形成し、さらに該絶縁層の上に導電性薄膜を形成
してなることを特徴とする半導体素子の実装用の基板。(2) A substrate for mounting a semiconductor element, characterized in that an insulating layer made of an inorganic substance is formed on a heat-resistant resin film, and a conductive thin film is further formed on the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21043388A JPH0260138A (en) | 1988-08-26 | 1988-08-26 | Board for semiconductor element mounting use |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21043388A JPH0260138A (en) | 1988-08-26 | 1988-08-26 | Board for semiconductor element mounting use |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260138A true JPH0260138A (en) | 1990-02-28 |
Family
ID=16589243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21043388A Pending JPH0260138A (en) | 1988-08-26 | 1988-08-26 | Board for semiconductor element mounting use |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260138A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260137A (en) * | 1988-08-26 | 1990-02-28 | Mitsui Toatsu Chem Inc | Board for semiconductor element mounting use |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848954A (en) * | 1981-09-18 | 1983-03-23 | Sumitomo Electric Ind Ltd | Substrate for tape carrier type integrated circuit |
| JPH01133729A (en) * | 1987-11-19 | 1989-05-25 | Nitto Denko Corp | Conductive laminated film |
| JPH0260137A (en) * | 1988-08-26 | 1990-02-28 | Mitsui Toatsu Chem Inc | Board for semiconductor element mounting use |
-
1988
- 1988-08-26 JP JP21043388A patent/JPH0260138A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848954A (en) * | 1981-09-18 | 1983-03-23 | Sumitomo Electric Ind Ltd | Substrate for tape carrier type integrated circuit |
| JPH01133729A (en) * | 1987-11-19 | 1989-05-25 | Nitto Denko Corp | Conductive laminated film |
| JPH0260137A (en) * | 1988-08-26 | 1990-02-28 | Mitsui Toatsu Chem Inc | Board for semiconductor element mounting use |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260137A (en) * | 1988-08-26 | 1990-02-28 | Mitsui Toatsu Chem Inc | Board for semiconductor element mounting use |
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