JPH0360184A - Manufacture of ceramic substrate with copper wiring - Google Patents

Manufacture of ceramic substrate with copper wiring

Info

Publication number
JPH0360184A
JPH0360184A JP19567089A JP19567089A JPH0360184A JP H0360184 A JPH0360184 A JP H0360184A JP 19567089 A JP19567089 A JP 19567089A JP 19567089 A JP19567089 A JP 19567089A JP H0360184 A JPH0360184 A JP H0360184A
Authority
JP
Japan
Prior art keywords
copper
oxygen
sulfur
vapor deposition
abnormal growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19567089A
Other languages
Japanese (ja)
Other versions
JP2715578B2 (en
Inventor
Tomio Iizuka
飯塚 富雄
Sadahiko Sanki
参木 貞彦
Mamoru Onda
護 御田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP19567089A priority Critical patent/JP2715578B2/en
Publication of JPH0360184A publication Critical patent/JPH0360184A/en
Application granted granted Critical
Publication of JP2715578B2 publication Critical patent/JP2715578B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the local abnormal growth of a plated section produced when plating of a metal, such as nickel, etc., other than copper is performed by an electroplating method so as to improve the reliability of the title substrate by using copper which is less in oxygen or sulfur content for copper to be used as the source of vapor deposition. CONSTITUTION:When a copper layer 3 is formed on a ceramic substrate 1 by vapor deposition, a kind of copper which is >=99.99% in purity and <=2ppm in oxygen content or another kind of copper which is 99.99% in purity and <=0.7ppm in the sum of oxygen and sulfur contents when the copper contains both oxygen and sulfur is used as the source of vapor deposition. The reason why the upper limit of the sum of oxygen and sulfur contents is suppressed is considered to be that, when oxygen and sulfur coexist, the copper is easily gasified due to the sulfur dioxide gas produced from the oxygen and sulfur. When a kind of copper which is >2ppm in oxygen content is used, whisker- or fin-like abnormal growth of a plated section occurs at the time of nickel plating. When the oxygen content is <=2ppm, such abnormal growth hardly occurs and, even when it occurs, the length of the abnormal section is short. Such abnormal growth can be eliminated completely, when the oxygen content is reduced to <=0.3ppm.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は銅配線基板、特に最終的に電気めっきにより銅
以外の金属の被膜を施した銅配線セラミック基板の製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a copper wiring board, particularly a copper wiring ceramic board which is finally coated with a metal other than copper by electroplating.

〔従来の技術〕[Conventional technology]

高密度実装が可能なICパッケージとして、PGA(ピ
ングリッドアレイ)基板がある。高信頼性を必要とする
用途のPGA基板には、セラミックを基板とし配線層が
アルミニウムのものが多く用いられていた。しかし最近
、電子回路の高速化に対応するため、アルミニウムに代
わり電気抵抗の小さい銅が用いられるようになった。銅
は高温では勿論常温でも酸化しやすく、そのままではワ
イヤボンディングに通しないため、通常、銅配線層には
ニッケルメッキまたはニッケルを下地とする金メツキが
施される。例えば第2図に示すように、セラミック基板
1の上にチタン1i2および銅導電N3を通常蒸着法に
より形成し、フォトエツチングにより回路パターンを形
e、(バターニングと呼ばれる)した後、電気めっき法
によりニッケル等の銅以外の金属の被膜7、例えばニッ
ケルを下地5として金めつき被膜6が施される。
A PGA (pin grid array) substrate is an IC package that can be mounted at high density. PGA substrates for applications requiring high reliability have often been made of ceramic and have aluminum wiring layers. Recently, however, copper, which has low electrical resistance, has been used in place of aluminum to accommodate the increasing speed of electronic circuits. Copper is easily oxidized not only at high temperatures but also at room temperature, and cannot be passed through wire bonding as it is, so copper wiring layers are usually plated with nickel or gold with a nickel base. For example, as shown in FIG. 2, titanium 1i2 and conductive copper N3 are formed on a ceramic substrate 1 by a normal vapor deposition method, a circuit pattern is formed by photoetching (called buttering), and then electroplating is performed. As a result, a gold plating film 6 is applied using a film 7 of a metal other than copper such as nickel, for example, nickel as the base 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし従来の銅配線セラくツク基板製造方法によると、
セラミック基板の上に銅導電層を蒸着法により形成し、
フォトエツチングにより回路パターンを形成(パターニ
ングと呼ばれる)した後、電気めっき法によりニッケル
等の銅以外の金属の被膜またはニッケル等を下地として
金等の貴金属の被膜を施す際に、ニッケル等のめっき層
が局部的に、第3図a)に示すようにホイスカ状に、ま
たは第3図b)に示すように水平方向にひれ状に、異常
成長することがしばしば起きた。第2図にはホイスカ状
の異常成長を5aで示した。甚だしい場合には本来電気
的に独立でなければならないリード部8同士が短絡した
り、短絡寸前の状態になる。具体例を示すと、平均めっ
き厚さが1μmの場合に異常成長の長さが10μm以上
、場合により40μmにも及ぶ(これは、異常成長部分
では平均めっき速度の10ないし40倍にも及ぶ速度で
電析が起きていることを意味する)。このようなめっき
部の異常成長により、製造された銅配線基板の信頼性が
甚だしく損なわれる。
However, according to the conventional copper wiring ceramic board manufacturing method,
A copper conductive layer is formed on a ceramic substrate by vapor deposition,
After forming a circuit pattern by photoetching (called patterning), when applying a coating of a metal other than copper such as nickel or a coating of a noble metal such as gold using nickel as a base by electroplating, a plating layer of nickel etc. Abnormal growth often occurred locally in the form of whiskers as shown in Figure 3a) or horizontally in the form of fins as shown in Figure 3b). In FIG. 2, whisker-like abnormal growth is indicated by 5a. In extreme cases, the lead parts 8, which should originally be electrically independent, may be short-circuited or almost short-circuited. To give a specific example, when the average plating thickness is 1 μm, the length of abnormal growth is 10 μm or more, and in some cases even reaches 40 μm (this means that the abnormal growth rate is 10 to 40 times the average plating speed). (means that electrodeposition is occurring). Such abnormal growth of the plating portion seriously impairs the reliability of the manufactured copper wiring board.

それ数本発明の目的は、蒸着法により形成した消電導層
に回路パターン形成後、電気めっき法によるニッケル等
銅以外の金属のめっきを施す際に生ずるめっき部の局部
的な異常成長を防止した、信頼性の高い銅配線セラミッ
ク基板の製造方法を提供することである。
The object of the present invention is to prevent local abnormal growth of the plated portion that occurs when plating a metal other than copper such as nickel by electroplating after forming a circuit pattern on a dissipating conductive layer formed by vapor deposition. An object of the present invention is to provide a method for manufacturing a highly reliable copper wiring ceramic substrate.

〔課題を解決するための手段〕[Means to solve the problem]

本発明では上記目的を達成するために、銅蒸着層を形成
する際蒸着源として、純度が99.99%以上で酸素含
有量が2ppm以下である銅を用いるか、または純度が
99.99%以上で硫黄含有量が4ppm以下である銅
を用いるようにした。
In order to achieve the above object, in the present invention, copper having a purity of 99.99% or more and an oxygen content of 2 ppm or less is used as a vapor deposition source when forming a copper vapor deposition layer, or copper with a purity of 99.99% or more is used as a vapor deposition source. In the above, copper having a sulfur content of 4 ppm or less was used.

ただし純度が99.99%以上の銅に酸素と硫黄が共存
する場合には、酸素含有量と硫黄含有量の和が0.lp
pm以下となるようにした。酸素と硫黄の合計含有量の
上限が小さくなる理由は、酸素と硫黄が共存すると二酸
化硫黄の生成によりガス化が生じ易(なるためと思われ
る。
However, if oxygen and sulfur coexist in copper with a purity of 99.99% or higher, the sum of the oxygen content and sulfur content is 0. lp
pm or less. The reason why the upper limit of the total content of oxygen and sulfur is small is thought to be that when oxygen and sulfur coexist, gasification tends to occur due to the production of sulfur dioxide.

本発明における銅蒸着層には、真空蒸着法のほかイオン
ブレーティング、クラスタイオンビーム法、スパッタリ
ング法等の物理的蒸着法(PVD)により形成された銅
層を包含する。
The copper vapor deposited layer in the present invention includes a copper layer formed by physical vapor deposition (PVD) such as ion blating, cluster ion beam method, sputtering method, etc. in addition to vacuum evaporation method.

本発明の方法は下記工程から威る。The method of the present invention consists of the following steps.

(1)セラミック基板に銅層を蒸着する工程基板として
用いるセラミックは、アルミナ、ムライト、マグネシア
、窒化アルミニウム、ジルコニア、炭化珪素等のいずれ
でもよい。
(1) Step of depositing a copper layer on a ceramic substrate The ceramic used as the substrate may be any of alumina, mullite, magnesia, aluminum nitride, zirconia, silicon carbide, etc.

本発明はセラミック基板に!PI層を蒸着する工程で蒸
着源として99.99%以上の純度でしかも酸素含有量
が2ppm以下である銅を用いるか、99.99%以上
の純度でしかも硫黄含有量が4ppm以下である銅を用
いることを特徴とする。
This invention applies to ceramic substrates! In the process of vapor depositing the PI layer, copper with a purity of 99.99% or more and an oxygen content of 2 ppm or less is used as a vapor deposition source, or copper with a purity of 99.99% or more and a sulfur content of 4 ppm or less is used. It is characterized by using

好ましくは、酸素含有量が0.3ppm以下の銅または
硫黄含有量がlppm以下の銅を用いる。
Preferably, copper with an oxygen content of 0.3 ppm or less or copper with a sulfur content of 1 ppm or less is used.

酸素含有量が2ppmを超える銅を用いると、ニッケル
めっき等の際に前記のようなホイスカ状、ひれ状等の異
常な成長が起きる。酸素含有量が2ppm以下であれば
めっき部の異常成長が極めて少なく、あってもその長さ
が短い。0.3ppm以下であれば異常成長は皆無とな
る。
If copper with an oxygen content of more than 2 ppm is used, abnormal growth such as whisker-like or fin-like shapes as described above will occur during nickel plating. If the oxygen content is 2 ppm or less, there will be very little abnormal growth in the plated area, and even if there is abnormal growth, the length will be short. If it is 0.3 ppm or less, there will be no abnormal growth.

純度99.99%以上で酸素含有量2ppm以下の銅を
得るには、特開昭60−244054号等に記載された
方法を用いることができる。
To obtain copper with a purity of 99.99% or more and an oxygen content of 2 ppm or less, the method described in JP-A-60-244054 and the like can be used.

同じように、硫黄含有量が4ppmを超える銅を用いる
と、めっき部の異常成長が起きる。硫黄含有14ppm
以下であれば、めっき部の異常成長が極めて少なく、あ
ってもその長さが短い。硫黄金有量をippm以下とす
れば異常成長は皆無となる。
Similarly, when copper with a sulfur content exceeding 4 ppm is used, abnormal growth of the plated portion occurs. Sulfur content 14ppm
If it is below, there will be very little abnormal growth in the plated area, and even if there is abnormal growth, the length will be short. If the sulfur gold content is kept below ippm, there will be no abnormal growth.

純度99.99%以上で硫黄含有量4ppm以下の銅を
得るには、特開昭57−16187号、同57−161
88号、特開昭61−84389号等に記載された方法
を用いることができる。
To obtain copper with a purity of 99.99% or more and a sulfur content of 4 ppm or less, Japanese Patent Application Laid-open Nos. 57-16187 and 57-161
88, JP-A No. 61-84389, etc. can be used.

銅を蒸着する前にセラごツタ基板上に予め下地として銅
以外の金属の層1例えばアルミニウム、チタン、ジルコ
ニウム、クロム、モリブデン、タングステン、ニッケル
等の1種または2種以上を蒸着により形成させてもよい
Before depositing copper, a layer 1 of a metal other than copper, such as one or more of aluminum, titanium, zirconium, chromium, molybdenum, tungsten, nickel, etc., is formed by vapor deposition as a base on the ceramic substrate. Good too.

蒸着する厚さは普通1μmから20μm程度であり、3
μmから10μmとすることが多い。
The thickness to be deposited is usually about 1 μm to 20 μm, and 3
It is often set to 10 μm.

(2)フォトエツチングによる回路パターン形成上記工
程(1)で得られた銅蒸着層に、通常のフォトエツチン
グの方法により回路パターンを形成させる。
(2) Formation of circuit pattern by photoetching A circuit pattern is formed on the copper vapor deposited layer obtained in the above step (1) by a conventional photoetching method.

(3)銅配線層の上に銅以外の金属をめっきする工程 上記工程(2)で得られた銅配線層に、電気めっき法に
よりニッケル等の銅以外の金属のめっき、またはニッケ
ル等を下地としてさらに貴金属めっきを施す。めっきの
ために用いる金属はニッケル、コバルト、クロム、モリ
ブデン、タングステン等から選ぶことができるが、ニッ
ケル、コバルト、クロムのようにめっき時に樹枝状成長
を生じ易い金属の場合本発明の効果が顕著である。
(3) Process of plating a metal other than copper on the copper wiring layer The copper wiring layer obtained in step (2) above is plated with a metal other than copper, such as nickel, or with a base layer of nickel, etc., using an electroplating method. Furthermore, precious metal plating is applied. The metal used for plating can be selected from nickel, cobalt, chromium, molybdenum, tungsten, etc., but the effect of the present invention is remarkable in the case of metals that tend to cause dendritic growth during plating, such as nickel, cobalt, and chromium. be.

必要に応じ、上記の銅以外の金属のめっきの上に別の金
属、特に金等の貴金属をさらにめっきしてもよい。
If necessary, another metal, particularly a noble metal such as gold, may be further plated on the above metal plating other than copper.

めっきの方法、条件等に特に制限はなく、通常の通りで
よい。ニッケル等の銅以外の金属のめっきの厚さは0.
 1ないし5μm程度、ニッケル等を下地としてめっき
した上に施す金等のめっきの厚さは0. 1ないし2μ
m程度である。
There are no particular restrictions on the plating method, conditions, etc., and the usual methods may be used. The thickness of plating of metals other than copper such as nickel is 0.
The thickness of gold or other plating applied on top of nickel or other base plating is approximately 1 to 5μm. 1 to 2μ
It is about m.

〔作用〕[Effect]

本発明の方法に従い、蒸着源として99.99%以上の
純度でしかも酸素含有量が2ppm以下である銅を用い
るか、99.99%以上の純度でしかも硫黄含有量が4
ppm以下である銅を用いてセラミック基板に銅導電層
を蒸着し、形成した銅導電層に回路パターン形成後、電
気めっき法によりニッケル等銅以外の金属のめっきまた
はニッケル等を下地とする金等の貴金属めっきを施すこ
とにより、めっき部の局所的な異常成長を伴わないでめ
っきができ、銅配線セラミック基板を製造することがで
きる。
According to the method of the present invention, copper with a purity of 99.99% or more and an oxygen content of 2 ppm or less is used as a deposition source, or copper with a purity of 99.99% or more and a sulfur content of 4 ppm or less is used.
A copper conductive layer is deposited on a ceramic substrate using copper of ppm or less, and after forming a circuit pattern on the formed copper conductive layer, plating with a metal other than copper such as nickel or gold etc. with nickel as a base is performed by electroplating. By performing noble metal plating, plating can be performed without local abnormal growth of the plated portion, and a copper wiring ceramic substrate can be manufactured.

銅蒸着膜中の酸素または硫黄の含有量が小さいとエツチ
ングの際に銅蒸着層の表面の結晶粒子の欠落が少なくな
るため、エツチングされた面が平滑になる。エツチング
された面が平滑になると、めっきの際の電流分布が比較
的均一になるので、異常成長の発生を防ぐことができる
If the content of oxygen or sulfur in the copper deposited film is small, fewer crystal grains will be lost on the surface of the copper deposited layer during etching, resulting in a smoother etched surface. When the etched surface becomes smooth, the current distribution during plating becomes relatively uniform, thereby preventing the occurrence of abnormal growth.

以下、本発明の方法を実施例により詳細に説明する。Hereinafter, the method of the present invention will be explained in detail with reference to Examples.

〔実施例〕〔Example〕

第1図に示すように、厚さ2mmのアルミナ基板l上に
、チタンを厚さ0.03μmに真空蒸着してチタン層2
を形成した後、純度99.99%で第1表に示すように
酸素および硫黄含有量の異なる11種の銅蒸着材料を、
基板温度300 ’C5真空度3X10−bTorrで
、厚さ66 m L真空蒸着して銅蒸着層3を形成した
。通常のフォトエツチング法により塩化銅溶液を用いて
金属層4(銅/チタンr*>をエッチし、線幅40μm
、線間40μm、長さ20mmの直線状の配線パターン
(リード部)1000本を互いに平行に形成した。こう
して得られたアルミナ基板上の銅配線パターンに、通常
の電気めっき法によりニッケルを0.5μmの厚さに下
地めっきしニッケル被膜5を形成した後、金を0.5μ
mの厚さに電気めっきし金被膜6を形成した。めっき条
件は、ニッケルめっきについては標準ワット浴を用い、
湯度60°C1電流密度2.0A/dm”とし、金めつ
きについてはシアン代金カリウム浴を用い、温度50°
C,電流密度1.0A/dm”とした。これによりセラ
藁ツク基板1の上に配線リード部8が形成された。
As shown in Fig. 1, a titanium layer 2 is formed by vacuum-depositing titanium to a thickness of 0.03 μm on an alumina substrate l with a thickness of 2 mm.
After forming 11 types of copper vapor deposition materials with a purity of 99.99% and different oxygen and sulfur contents as shown in Table 1,
A copper deposition layer 3 was formed by vacuum deposition to a thickness of 66 mL at a substrate temperature of 300'C5 and a vacuum degree of 3X10-bTorr. The metal layer 4 (copper/titanium r*>) was etched using a copper chloride solution using a normal photoetching method, and the line width was 40 μm.
, 1000 linear wiring patterns (lead parts) with a line spacing of 40 μm and a length of 20 mm were formed in parallel to each other. The thus obtained copper wiring pattern on the alumina substrate is plated with nickel to a thickness of 0.5 μm using a normal electroplating method to form a nickel film 5, and then gold is coated with 0.5 μm of gold.
An electroplated gold film 6 was formed to a thickness of m. The plating conditions were as follows: For nickel plating, a standard Watt bath was used;
The hot water temperature was 60°C, the current density was 2.0A/dm", and for gold plating, a cyanogen potassium bath was used, and the temperature was 50°C.
C, and the current density was 1.0 A/dm''.Thus, the wiring lead portion 8 was formed on the ceramic straw substrate 1.

第1図で4は蒸着で形成された層(蒸着N)を、7はめ
っき層を示す。
In FIG. 1, 4 indicates a layer formed by vapor deposition (vapor deposition N), and 7 indicates a plating layer.

ニッケルめっき終了時および金めつきまで終了した配線
パターンの表面を観察した。その結果を第1表に示す。
The surface of the wiring pattern was observed after nickel plating and after gold plating. The results are shown in Table 1.

第1表中酸素含有t4ppm(試験番号1)、硫黄含有
量7ppm(試験番号5)、酸素0.5ppm、硫黄1
.0ppm(試験番号9)の欄は本発明の範囲外の比較
例に相当する。
In Table 1, oxygen content t4ppm (test number 1), sulfur content 7ppm (test number 5), oxygen 0.5ppm, sulfur 1
.. The column of 0 ppm (Test No. 9) corresponds to a comparative example outside the scope of the present invention.

第1表で異常成長発生率は、リード部1000本につい
て異常成長が発生した本数の百分率を示し、短絡の発生
数はリード部1000本のうち隣接するリード部間で短
絡の発生した本数を示す。
In Table 1, the abnormal growth occurrence rate indicates the percentage of the number of leads in which abnormal growth has occurred out of 1000 leads, and the number of short circuits indicates the number of leads in which short circuits have occurred between adjacent leads out of 1000 leads. .

第1表 第1表から明らかなように、 本発明に従い純度 が99.99%で硫黄を検出せず酸素含有量2ppm以
下の銅(試験番号2,3,4Lまたは純度が99.99
%で酸素を検出せず硫黄含有量4ppm以下(試験番号
6,7.8)の銅を用いて蒸着した場合には、異常成長
による線間の短縮は生じなかった。酸素含有fi1.8
ppmまたは硫黄含有量3.5ppmの場合には、異常
成長が約10%強の率で発生したが、短絡は生じていな
い。酸素含有量が0.2ppmまたは硫黄含有量0.8
ppmの場合(試験番号4および8)には、異常成長は
皆無となった。これに対し純度99゜99%でも酸素含
有量が2ppmを超える銅または硫黄含有量が4ppm
を超える銅を用いて蒸着した場合(試験番号lおよび5
)には、異常成長が高い割合で発生し、線間の短絡が生
じた。
Table 1 As is clear from Table 1, according to the present invention, copper with a purity of 99.99%, no detectable sulfur, and an oxygen content of 2 ppm or less (test number 2, 3, 4L or with a purity of 99.99%)
%, no oxygen was detected and copper with a sulfur content of 4 ppm or less (test numbers 6 and 7.8) was used for vapor deposition, no shortening of the line distance due to abnormal growth occurred. Oxygen content fi1.8
ppm or 3.5 ppm sulfur content, overgrowth occurred at a rate of just over 10%, but no shorting occurred. Oxygen content is 0.2 ppm or sulfur content is 0.8
In the case of ppm (test numbers 4 and 8), there was no abnormal growth. On the other hand, even if the purity is 99°99%, the oxygen content exceeds 2 ppm or the sulfur content is 4 ppm.
(Test Nos. 1 and 5)
) had a high rate of abnormal growth and short circuits between lines.

他方、0.5ppmの酸素とippmの硫黄とを含む純
度99.99%の銅を用いた場合には、異常成長発生率
は低いにも関わらず、線間の短絡が生じた。しかしQ、
3ppmの酸素と0.3ppmの硫黄(酸素と硫黄の和
は0.6ppm)とを含む純度99.99%の銅を用い
た場合には異常成長は発生せず、線間の短絡も生じなか
った。
On the other hand, when 99.99% pure copper containing 0.5 ppm oxygen and ippm sulfur was used, short circuits between wires occurred although the incidence of abnormal growth was low. However, Q.
When using 99.99% pure copper containing 3 ppm oxygen and 0.3 ppm sulfur (the sum of oxygen and sulfur is 0.6 ppm), no abnormal growth occurred and no short circuit between wires occurred. Ta.

〔発明の効果〕〔Effect of the invention〕

本発明の方法によると、セラミック基板上に蒸験番号1
)、硫黄含有量7ppm(試験番号5)、酸素0.5p
pm、硫黄1.0ppm(試験番号9)の欄は本発明の
範囲外の比較例に相当する。
According to the method of the present invention, steaming number 1 is placed on a ceramic substrate.
), sulfur content 7 ppm (test number 5), oxygen 0.5 p
pm, sulfur 1.0 ppm (Test No. 9) column corresponds to a comparative example outside the scope of the present invention.

第1表で異常成長発生率は、リード部1000本につい
て異常成長が発生した本数の百分率を示し、にホイスカ
状等に異常成長する現象が生じなくなり、電気的に独立
でなければならないリード同士の短絡または短絡寸前の
状態になることが防がれる。本発明の方法は特にセラミ
ック基板上に銅導電層を蒸着する場合に有効である。
In Table 1, the abnormal growth occurrence rate indicates the percentage of the number of leads in which abnormal growth occurs out of 1,000 leads, and indicates that the phenomenon of abnormal growth such as whiskers does not occur, and the leads that must be electrically independent. A short circuit or near-short circuit condition is prevented. The method of the present invention is particularly useful for depositing copper conductive layers on ceramic substrates.

本発明において、蒸着源とする銅に酸素含有量または硫
黄含有量の低い銅を用いると、その後のめっき工程での
めっき層の異常成長が生じない理由は、前述した通り、
酸素または硫黄の含有量が小さいとエツチングの際に銅
蒸着層の表面の結晶粒子の欠落が生ぜず、エツチング後
の表面の凹凸が少ないため、めっきの際の電流分布が比
較的均一になるためである。
In the present invention, when copper with a low oxygen content or sulfur content is used as the vapor deposition source, abnormal growth of the plating layer does not occur in the subsequent plating process, as described above.
If the content of oxygen or sulfur is small, crystal grains on the surface of the copper vapor deposited layer will not be missing during etching, and the surface after etching will have less unevenness, so the current distribution during plating will be relatively uniform. It is.

本発明の方法によると、銅蒸着層に銅以外の金属のめっ
きを施す際に異常成長がないだけでなく、メツキ後の回
路パターンのエツジの凹凸が少なくなり、鮮鋭な回路パ
ターンが得られる。その結果パターンを微細にすること
が可能となる。
According to the method of the present invention, there is not only no abnormal growth when plating a metal other than copper on a copper vapor deposited layer, but also the unevenness of the edges of the circuit pattern after plating is reduced, resulting in a sharp circuit pattern. As a result, it becomes possible to make the pattern finer.

本発明の方法によると、セラミック基板上に蒸着した銅
配線層に、前記のようなめっき層の異常成長を生ずるこ
となくニッケル等の銅以外の金属をめっきすることが可
能になるから、導電層に電気抵抗の小さい銅を用いたワ
イヤボンディングに適するセラミック配線基板を作るこ
とができ、電子回路の例えば演算速度の高速化に対応す
ることができる。本発明の方法は、例えばPGACピン
グリッドアレイ)や、TAB (テープオートメーテツ
ドボンディング)、FPC(フレキシブルプリント基板
)等に適用できる。
According to the method of the present invention, it is possible to plate a metal other than copper, such as nickel, on a copper wiring layer deposited on a ceramic substrate without causing abnormal growth of the plating layer as described above. It is possible to create a ceramic wiring board suitable for wire bonding using copper with low electrical resistance, and it can be used to increase the calculation speed of electronic circuits, for example. The method of the present invention can be applied to, for example, PGAC pin grid array), TAB (tape automated bonding), FPC (flexible printed circuit board), and the like.

本発明の方法はセラミック基板上に銅を直接蒸着する場
合のみならず、セラくツク基板上に蒸着等により設けた
他の金属の下地層を介して銅を蒸着する場合にも、有用
である。
The method of the present invention is useful not only when depositing copper directly onto a ceramic substrate, but also when depositing copper through a base layer of another metal provided by vapor deposition or the like on a ceramic substrate. .

また本発明の方法は、回路パターンを形成した消電導層
にニッケル等の銅板外の金属のめっきを施した後、この
層を下地としてさらに金、銀等の貴金属をめっきする場
合にも有用である。
The method of the present invention is also useful when plating a metal other than the copper plate, such as nickel, on a power-dissipating conductive layer on which a circuit pattern is formed, and then plating a noble metal such as gold or silver using this layer as a base. be.

本発明の方法によると、電流密度を高くして電気めっき
の速度を増大させることが可能になり、生産効率を高め
ることができる。
According to the method of the present invention, it is possible to increase the current density and the speed of electroplating, thereby increasing production efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例で得られたセラミック基板上の
配線層の拡大断面図、第2図は従来の方法で製造された
セラミック基板上の配線層の異常成長の部分における拡
大断面図、第3図はセラミック基板上の蒸着銅配線層に
ニッケル等を電気めっきした際に生ずるホイスカ状(第
3図a))およびひれ状(第3図b))の異常成長の状
態を示す説明図である。 符号の説明 1−−−−−−一・・・・セラミック基板 2−・・−
・・−・チタン蒸着層3−・−・・・−銅蒸着層   
 4・−・−・・−・・蒸着層5−・−一−−−−・ニ
ッケルめっき層5a−・−・−ニッケルめっき層の異常
戊長部6−・・・−・−金めつき層
FIG. 1 is an enlarged cross-sectional view of a wiring layer on a ceramic substrate obtained in an example of the present invention, and FIG. 2 is an enlarged cross-sectional view of an abnormally grown portion of a wiring layer on a ceramic substrate manufactured by a conventional method. , Fig. 3 is an explanation showing the abnormal growth of whiskers (Fig. 3a)) and fins (Fig. 3b)) that occur when nickel or the like is electroplated on a vapor-deposited copper wiring layer on a ceramic substrate. It is a diagram. Explanation of symbols 1------1...Ceramic substrate 2--...-
--- Titanium vapor deposition layer 3 --- Copper deposition layer
4・−・−・・−・・Vapour-deposited layer 5−・−1−−−・Nickel plating layer 5a−・−・−Abnormally elongated portion of nickel plating layer 6−・・・・−・−Gold plating layer

Claims (4)

【特許請求の範囲】[Claims] (1)セラミック基板の上に蒸着法により銅導電層を形
成し、該銅導電層に回路パターン形成後、電気めっき法
により銅以外の金属の被膜を施す銅配線セラミック基板
の製造方法において、銅蒸着層を形成するための蒸着源
として純度が99.99%以上、かつ酸素含有量が2p
pm以下であり、硫黄を含む場合には酸素含有量と硫黄
含有量の和が0.7ppm以下である銅を用いることを
特徴とする銅配線セラミック基板の製造方法。
(1) In a method for manufacturing a copper wiring ceramic substrate, in which a copper conductive layer is formed on a ceramic substrate by a vapor deposition method, a circuit pattern is formed on the copper conductive layer, a coating of a metal other than copper is applied by an electroplating method. As a vapor deposition source for forming a vapor deposition layer, a purity of 99.99% or more and an oxygen content of 2p
pm or less, and when containing sulfur, the sum of oxygen content and sulfur content is 0.7 ppm or less.
(2)前記銅以外の金属がニッケル、コバルト、クロム
のうちから選ばれる請求項第1項の銅配線セラミック基
板の製造方法。
(2) The method for manufacturing a copper wiring ceramic substrate according to claim 1, wherein the metal other than copper is selected from nickel, cobalt, and chromium.
(3)セラミック基板の上に蒸着法により銅導電層を形
成し、該銅導電層に回路パターン形成後、電気めっき法
により銅以外の金属の被膜を施す銅配線セラミック基板
の製造方法において、銅蒸着層を形成するための蒸着源
として純度が99.99%以上、かつ硫黄含有量が4p
pm以下であり、酸素を含む場合には酸素含有量と硫黄
含有量の和が0.7ppm以下である銅を用いることを
特徴とする銅配線セラミック基板の製造方法。
(3) A method for manufacturing a copper wiring ceramic substrate, in which a copper conductive layer is formed on a ceramic substrate by vapor deposition, a circuit pattern is formed on the copper conductive layer, and then a coating of a metal other than copper is applied by electroplating. A vapor deposition source for forming a vapor deposition layer with a purity of 99.99% or more and a sulfur content of 4p
pm or less, and when containing oxygen, the sum of the oxygen content and sulfur content is 0.7 ppm or less.
(4)前記銅以外の金属がニッケル、コバルト、クロム
のうちから選ばれる請求項第1項の銅配線セラミック基
板の製造方法。
(4) The method for manufacturing a copper wiring ceramic substrate according to claim 1, wherein the metal other than copper is selected from nickel, cobalt, and chromium.
JP19567089A 1989-07-28 1989-07-28 Manufacturing method of copper wiring ceramic substrate Expired - Fee Related JP2715578B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19567089A JP2715578B2 (en) 1989-07-28 1989-07-28 Manufacturing method of copper wiring ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19567089A JP2715578B2 (en) 1989-07-28 1989-07-28 Manufacturing method of copper wiring ceramic substrate

Publications (2)

Publication Number Publication Date
JPH0360184A true JPH0360184A (en) 1991-03-15
JP2715578B2 JP2715578B2 (en) 1998-02-18

Family

ID=16345045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19567089A Expired - Fee Related JP2715578B2 (en) 1989-07-28 1989-07-28 Manufacturing method of copper wiring ceramic substrate

Country Status (1)

Country Link
JP (1) JP2715578B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013024813A1 (en) * 2011-08-12 2013-02-21 三菱マテリアル株式会社 Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013024813A1 (en) * 2011-08-12 2013-02-21 三菱マテリアル株式会社 Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module
US9066433B2 (en) 2011-08-12 2015-06-23 Mitsubishi Materials Corporation Power module substrate, power module substrate with heat sink, power module, and method of manufacturing power module substrate

Also Published As

Publication number Publication date
JP2715578B2 (en) 1998-02-18

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