JPH0259400A - Production of semiconductor device for ic card - Google Patents
Production of semiconductor device for ic cardInfo
- Publication number
- JPH0259400A JPH0259400A JP63209539A JP20953988A JPH0259400A JP H0259400 A JPH0259400 A JP H0259400A JP 63209539 A JP63209539 A JP 63209539A JP 20953988 A JP20953988 A JP 20953988A JP H0259400 A JPH0259400 A JP H0259400A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- die
- bonding material
- hardening
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 239000003566 sealing material Substances 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Credit Cards Or The Like (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はＩＣカード用の半導体装置のｌ遣方法に係り、
更に詳しくは、カード搭載用のＣｈｉｐ ｏｎＢｏａｒ
ｄ型ＩＣモジュ型用Ｃモジュールチップのダイボンディ
ング方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of using a semiconductor device for an IC card,
For more information, see Chip onBoar for mounting cards.
The present invention relates to a die bonding method for a C module chip for a d-type IC module type.
［従来の技術］
ＩＣカードは、コンパクトでありながら記憶容量が大き
く情報の読みさぎができることから、近時急速に悴及し
つつある。[Prior Art] IC cards are becoming rapidly popular in recent years because they are compact but have a large storage capacity and can read information.
第７図〜第１０図は従来のＩＣカードに係り、第７図並
びに第８図示のように、例えば塩化ビニールなどのプラ
スチック製のカード１の収納凹部内に、ＩＣカード用の
ＩＣチップを樹脂で封止してなるＩＣモジュール３を内
蔵・搭載して接着剤２で固着し、該ＩＣモジュール３に
形成した外部接続用の端子部４をカード１の表面と路面
−に露呈させた構成を採っている。そして、ＩＣカード
をカードリーダライタに装着した際には、上記端子部４
を介して情報の読み書きが行なわれるようになっている
。Figures 7 to 10 relate to conventional IC cards, and as shown in Figures 7 and 8, an IC chip for an IC card is placed in a resin storage recess of a card 1 made of plastic such as vinyl chloride. The IC module 3 is sealed with a built-in and mounted IC module 3, which is fixed with an adhesive 2, and a terminal part 4 for external connection formed on the IC module 3 is exposed on the surface of the card 1 and the road surface. I'm picking it up. When the IC card is installed in the card reader/writer, the terminal section 4
Information is read and written through the .
第９図は前記ＩＣモジュール３を示している。FIG. 9 shows the IC module 3.
同図において、５はモジュール用の基板で、該基板５の
一面上にはＩＣチップ接続用の導体パターン６並びに金
属製のダイパッド７が形成されており、また、基板５の
他面には上記導体パターン６とスルーホール８を介して
接続された端子部４が形成されている。１０はＩＣチッ
プで、上記平坦なダイパッド７上に例えば熱硬化型のエ
ポキシ系樹脂よりなるダイボンド材１１を加熱硬化させ
ることによってダイボンディングされており、また、Ｉ
Ｃチップ１０の接続端子部は、Ａｕ線１２によって１涌
記導体パターン６とワイヤボンディングによって電気的
に接続されている。１３は封止材で、例えば熱硬化型の
エポキシ系樹脂よりなっており。In the figure, reference numeral 5 denotes a module board, and on one side of the board 5, a conductive pattern 6 for connecting an IC chip and a metal die pad 7 are formed, and on the other side of the board 5, the above-mentioned die pad 7 is formed. A terminal portion 4 is formed which is connected to the conductive pattern 6 via a through hole 8. Reference numeral 10 denotes an IC chip, which is die-bonded onto the flat die pad 7 by heating and curing a die-bonding material 11 made of, for example, a thermosetting epoxy resin.
The connection terminal portion of the C chip 10 is electrically connected to one conductor pattern 6 by an Au wire 12 by wire bonding. 13 is a sealing material made of, for example, thermosetting epoxy resin.
ボッティグもしくはトランスファモールドで形成されて
前記ＩＣチップ１ｏを封入・保護するようになっている
。It is formed by Bottig or transfer molding to encapsulate and protect the IC chip 1o.
［発明が解決しようとするａＭ］
ところで、上述した従来のＩＣカード用のＩＣモジュー
ル３にあっては、前記ダイボンド材１１の収縮応力によ
って、ＩＣチップ１０の表面側には第１０図に示すよう
に大きな引張応力Ｆ（Ｔ）が発生する。このＩＣチップ
１０の引張残留応力は、時としてＩＣチップ１０の破壊
限界値（引張応力で１００ＭＰａ程度）近傍に達するこ
ともあり、組立て工程時におけるＩＣチップクラックの
発生や、カード化した後のＩＣチップ破壊限界値の低下
などを招来し、製造歩留り並びに製品の信頼性を著しく
劣化させるという開運があった。[AM to be Solved by the Invention] Incidentally, in the above-described conventional IC module 3 for an IC card, shrinkage stress of the die-bonding material 11 causes damage to the front surface of the IC chip 10 as shown in FIG. A large tensile stress F(T) is generated. This tensile residual stress of the IC chip 10 sometimes reaches near the fracture limit value of the IC chip 10 (approximately 100 MPa in terms of tensile stress), which may cause IC chip cracks to occur during the assembly process or to the IC chip after being made into a card. Unfortunately, this led to a decrease in the chip failure limit value, significantly deteriorating manufacturing yield and product reliability.
従って、本発明の解決すべき技術的課題は上述した従来
技術のもつ問題点を解消することにあり、その目的とす
るところは、ＩＣチップの残留応力を軽減し、以って製
造歩留りが向上でき、信頼性の高いＩＣカード用の半導
体装置（ＩＣモジュール）を堤供することにある。Therefore, the technical problem to be solved by the present invention is to solve the above-mentioned problems of the conventional technology, and its purpose is to reduce the residual stress of IC chips, thereby improving manufacturing yield. Our objective is to provide a highly reliable semiconductor device (IC module) for IC cards.
［課題を解決するための手段］
本発明の上記した目的は、基板上にＩＣチップをダイボ
ンディングすると共に、基板上の導体パターンとＩＣチ
ップとをワイヤボンデイグし、さらにＩＣチップを封止
材で封止してなるＩＣモジュールを、カードに搭載する
ようにしたＩＣカード用の半導体装置の製造方法におい
て、前記ＩＣチップ用のダイボンド材を、特定箇所を硬
化の起点として該起点から遠ざかる方向に順次硬化を進
行させることによって達成される。[Means for Solving the Problems] The above-mentioned object of the present invention is to die-bond an IC chip onto a substrate, perform wire bonding between a conductive pattern on the substrate and the IC chip, and further seal the IC chip with a sealing material. In the method of manufacturing a semiconductor device for an IC card, the die-bonding material for the IC chip is sequentially cured in a direction away from the starting point, with a specific location as a starting point for curing. This is achieved by progressing.
［作用］
本発明は上述の如く、前記ダイボンド材の硬化の起点と
硬化進行方向を制御しているので、従来のようにダイボ
ンド材全体が急激に加熱硬化されるものに比して、ダイ
ボンド材の硬化収縮応力が緩和され、従ってＩＣチップ
の表面側の引張残留応力は大幅に軽減される。[Function] As described above, the present invention controls the starting point and direction of curing of the die bonding material, so the die bonding material The curing shrinkage stress of the IC chip is alleviated, and therefore the tensile residual stress on the surface side of the IC chip is significantly reduced.
［実施例コ 以下本発明を図示した実施例によって説明する。[Example code] The present invention will be explained below with reference to illustrated embodiments.
第１図は本発明の第１実施例に係るＩＣカード用の半導
体装置たるＩＣモジュールを示す図で、同図において前
記第９図示の従来構成と同一の部材には同一符号を付し
である。FIG. 1 is a diagram showing an IC module, which is a semiconductor device for an IC card, according to a first embodiment of the present invention. In the figure, the same members as those in the conventional configuration shown in FIG. 9 are given the same reference numerals. .
この本発明の第１実施例に係るＩＣモジュール３Ａは、
封止材１３Ａをトランスファモールドによって形成しで
ある。第１図に示すモジュール用の基板５Ａの一面には
、前記導体パターン６並びに後記する形状のダイパッド
１４が形成されていると共に、該基板５Ａの他面には前
記スルーホール８を介して導体パターン６と接続された
前記端子部４が形成されている。そして、前記ＩＣチッ
プ１０が、ダイボンド材１１によってダイボンディング
された後、前記Ａｕ線１２によってＩＣチップｌＯと導
体パターン６とがワイヤボンディングされ、然る後、封
止材１３Ａをトランスファモールド法で形成することに
よって、ＩＣモジュール３Ａが完成されるようになって
いる。The IC module 3A according to the first embodiment of the present invention includes:
The sealing material 13A is formed by transfer molding. On one surface of the module substrate 5A shown in FIG. The terminal portion 4 connected to the terminal 6 is formed. After the IC chip 10 is die-bonded with the die-bonding material 11, the IC chip 10 and the conductor pattern 6 are wire-bonded with the Au wire 12, and then the sealing material 13A is formed by transfer molding. By doing so, the IC module 3A is completed.
前記金属製のダイパッド１４は、該実施例においては第
２図に示すように、その中央部分に平坦な突出頂部１４
ａと、該突出頂部１４ａから四辺に向って高さが漸次減
じられた傾斜部１４ｂとをもつ、頂部が切落された偏平
な四角錐形状を呈している。そして、ダイパッド１４は
その平坦な下面側を前記基板５Ａ上に適宜手段で密着固
定されるようになっている。In this embodiment, the metal die pad 14 has a flat protruding top portion 14 at its central portion, as shown in FIG.
a and sloped portions 14b whose heights are gradually reduced toward the four sides from the protruding top portion 14a. The die pad 14 has its flat lower surface side tightly fixed onto the substrate 5A by appropriate means.
ＩＣチップ１０のダイボンディングに際しては、前記ダ
イパッド１４の上面側（上記突出頂部１４ａと傾斜部１
４ｂ）に、例えばエポキシ系樹脂などの熱硬化型樹脂よ
りなる前記ダイボンド材１１を塗布した後、前記ＩＣチ
ップ１０が載置され、図示せぬ加熱手段によってダイボ
ンド材１１が加熱硬化される。この際、第３図に示した
ようにＩＣチップ１０の下面中央部分の下のダイボンド
材１１の量は他の部位よりも少ないため、この部分（即
ち突出頂部１４ａ上）で先ず硬化が先行して始まり、突
出頂・部１４ａ上がダイボンド材１１の硬化の起点とな
る。また、突出頂部１４ａの周囲には前記傾斜部１４ｂ
が存在しているため、ダイボンド材１１はＩＣチップ１
０の外縁に向ってその量が増加している。このためＩＣ
チップ１０の外縁に向うほどダイボンド材１１の硬化に
遅延を生じ、硬化はＩＣチップ１０の中央から外周側に
放射状に進行する。このように、グーＣボンド材１１の
硬化が、硬化起点から遠ざかる方向に遅延して進行する
ことによって、ダイボンド材１１の収縮量、即ち収縮応
力を低減でき、よってＩＣチップ１０の表面側の引張応
力が従来に較べて大幅に軽減できる。従って１組立て工
程時におけるＩＣチップクラックの発生の虞れや、カー
ド化した後のＩＣチップ破壊限界値の低下などの悪影響
を排除でき、製造歩留り並びに製品の信頼性が大きく向
上する。When die bonding the IC chip 10, the upper surface side of the die pad 14 (the protruding top portion 14a and the inclined portion 1
4b), the die bonding material 11 made of a thermosetting resin such as an epoxy resin is applied, the IC chip 10 is placed thereon, and the die bonding material 11 is heated and hardened by a heating means (not shown). At this time, as shown in FIG. 3, since the amount of die-bonding material 11 under the central part of the lower surface of the IC chip 10 is smaller than other parts, curing occurs first in this part (i.e., above the protruding top part 14a). The hardening of the die-bonding material 11 begins on the protruding top portion 14a. Further, the inclined portion 14b is provided around the protruding top portion 14a.
exists, the die bonding material 11 is attached to the IC chip 1.
The amount increases toward the outer edge of 0. For this reason, IC
The curing of the die-bonding material 11 is delayed toward the outer edge of the chip 10, and the curing progresses radially from the center of the IC chip 10 toward the outer periphery. In this way, the curing of the goo C bond material 11 progresses with a delay in the direction away from the curing origin, thereby reducing the amount of shrinkage of the die bond material 11, that is, the shrinkage stress, and thus reducing the tensile stress on the surface side of the IC chip 10. Stress can be significantly reduced compared to conventional methods. Therefore, it is possible to eliminate adverse effects such as the risk of IC chip cracking during one assembly process and a decrease in the IC chip breakdown limit after it is made into a card, and the manufacturing yield and product reliability are greatly improved.
第４図は本発明の第２実施例に係るＩＣカード用の半導
体装置たるＩＣモジュール３Ｂを示す図で、該実施例は
ダイパッドの形状を除き前記した第９図の従来例と同等
構成をとっており、第９図の構成と同等の部材には同一
符号を付してあり。FIG. 4 is a diagram showing an IC module 3B which is a semiconductor device for an IC card according to a second embodiment of the present invention, and this embodiment has the same configuration as the conventional example shown in FIG. 9 described above except for the shape of the die pad. Components equivalent to those in the configuration shown in FIG. 9 are given the same reference numerals.
その説明は重複を避けるため制電する。The explanation will be static to avoid duplication.
第４図において１５は金属型のダイパッドで、第５図に
詳細を示すように、該ダイパッド１５は、その中央部分
に平坦な突出頂部１５ａと、該突出頂部１５ａから四辺
に向って高さが漸次減じられた略偏平円錐面状の傾斜部
１５ｂとをもつものとなっている。該実施例におけるダ
イパッド１５も前記第１実施例と同様に、前記ダイボン
ド材１１の硬化を、突出頂部１５ａ上を起点としてＩＣ
チップ１０の外縁に向って放射状に遅延して進行させる
ように機能し、前記実施例と同等の効果を奏することが
できる。In FIG. 4, reference numeral 15 denotes a metal die pad, and as shown in detail in FIG. The inclined portion 15b has a substantially flat conical surface shape which is gradually reduced. Similarly to the first embodiment, the die pad 15 in this embodiment also cures the die bonding material 11 by starting from the top of the protrusion 15a.
It functions to advance radially with a delay toward the outer edge of the chip 10, and can achieve the same effect as the embodiment described above.
第６図は本発明の第３実施例を示しており、該実施例に
おける金属型のダイパッド１６は、その中心から偏った
隅部近傍に平坦な突出頂部１６ａが形成されていると共
に、該突出頂部１６ａから遠ざかるに従って高さが漸次
減じられた傾斜部１６ｂが形成されている。この実施例
においては。FIG. 6 shows a third embodiment of the present invention, in which a metal die pad 16 has a flat protruding top 16a formed near a corner offset from the center, and A sloped portion 16b is formed whose height gradually decreases as it moves away from the top portion 16a. In this example.
前記ダイボンド材１１の硬化は、ＩＣチップ１０の下面
隅部の突出頂部１６ａ上を硬化起点として、図示矢印の
如く硬化起点から遠ざかる方向に放射状に進行し、この
場合も、前記各実施例と同様にダイボンド材１１の硬化
収縮応力が小さくなって、ＩＣチップ１０の表面側の引
張残留応力を大幅に軽減できる。The hardening of the die bonding material 11 starts from the top of the protruding top 16a at the corner of the lower surface of the IC chip 10, and progresses radially in the direction away from the hardening start point as shown by the arrow in the figure. In addition, the curing shrinkage stress of the die-bonding material 11 is reduced, and the tensile residual stress on the surface side of the IC chip 10 can be significantly reduced.
以上本発明を図示した実施例によって説明したが、当業
者には本発明の精神を逸脱しない範囲で種々の変形が可
能で、例えば、ダイボンディング工程時のＩＣチップの
位置決めを工夫することによって、ダイパッドの形状を
切頭錐体形状ではなく、頂部が尖った偏平錐体形状とす
ることも可能であり、場合によってはモジュール用の基
板自体にダイパッドに見合う形状を一体形成するように
しても良い。Although the present invention has been described above with reference to the illustrated embodiments, those skilled in the art can make various modifications without departing from the spirit of the present invention. For example, by devising the positioning of the IC chip during the die bonding process, The shape of the die pad can be made into an oblate pyramid shape with a pointed top instead of a truncated pyramid shape, and in some cases, a shape suitable for the die pad may be integrally formed on the module substrate itself. .
［５Ｉ！明の効果コ
以上のように、本発明のＩＣカード用の半導体装置（Ｉ
Ｃモジュール）の製造方法によれば、ＩＣチップの残留
応力を軽減でき、製造歩留り並びにＩＣチップの信頼性
が向上しうるＩＣカード用の半導体装置（ＩＣモジュー
ル）を提供でき、その産業的価値は高い。[5I! As described above, the semiconductor device (I) for IC cards of the present invention
According to the manufacturing method of C module), it is possible to provide a semiconductor device (IC module) for an IC card that can reduce the residual stress of the IC chip and improve the manufacturing yield and the reliability of the IC chip, and its industrial value is expensive.
第１図〜第３図は本発明の第１実施例によるＩＣカード
用のＩＣモジュールに係り、第１図はＩＣモジュールの
断面図、第２図（ａ）はダイパッドの１例を示す平面図
、第２図（ｂ）は第２図（ａ）のＡ−Ａ線断面図、第３
図はダイボンド材の硬化進行方向を示す説明図、第４図
及び第５図は本発明の第２実施例によるＩＣカード用の
ＩＣモジュールに係り、第４図はＩＣモジュールの断面
図、第５図（、）はダイパッドの１例を示す平面図、第
５図（ｂ）は第５図（ａ）のＢ−Ｂ線断面図、第６図は
本発明の第３実施例を示す説明図、第７図〜第１０図は
従来例に係り、第７図はＩＣカードの平面図、第８図は
ＩＣカードの要部断面図、第９図はＩＣモジュールの断
面図、第１０図はＩＣチップにおける応力発生を示すた
めの模式化した説明図である。
１・・・・・・カード、２・・・・・・接着剤、３．３
Ａ、３Ｂ・・・・・・ＩＣモジュール、４・・・・・・
端子部、５，５Ａ・・・・・・モジュール用の基板、６
・・・・・・導体パターン、７・・・・・・ダイパッド
、８・・・・・・スルーホール、１０・・・・・・ＩＣ
チップ、１１・・・・・・ダイボンド材、１２・・・・
・・Ａｕ ＃１．ｌ ３ 、 １３ Ａ−−封止材、１
４，１５．１６・・・・・・ダイパッド、１４ａ、１５
ａ、１６ａ・・・・・・突出頂部、１４ｂ、１５ｂ、１
６ｂ・・・・・・傾斜部。
第７図
第１０図
の」お1 to 3 relate to an IC module for an IC card according to a first embodiment of the present invention, FIG. 1 is a sectional view of the IC module, and FIG. 2(a) is a plan view showing an example of a die pad. , FIG. 2(b) is a sectional view taken along the line A-A in FIG. 2(a), and FIG.
The figure is an explanatory view showing the direction in which the die-bonding material hardens. Figures 4 and 5 relate to an IC module for an IC card according to the second embodiment of the present invention. Figure 4 is a sectional view of the IC module. Figure 5(a) is a plan view showing one example of a die pad, Figure 5(b) is a sectional view taken along the line B-B of Figure 5(a), and Figure 6 is an explanatory diagram showing a third embodiment of the present invention. , FIG. 7 to FIG. 10 relate to conventional examples, FIG. 7 is a plan view of an IC card, FIG. 8 is a sectional view of the main parts of the IC card, FIG. 9 is a sectional view of the IC module, and FIG. 10 is a plan view of the IC card. FIG. 2 is a schematic explanatory diagram showing stress generation in an IC chip. 1... Card, 2... Adhesive, 3.3
A, 3B...IC module, 4...
Terminal part, 5,5A... Board for module, 6
...Conductor pattern, 7...Die pad, 8...Through hole, 10...IC
Chip, 11...Die bond material, 12...
...Au #1. l3, 13 A--Sealing material, 1
4,15.16...Die pad, 14a, 15
a, 16a...Protruding top, 14b, 15b, 1
6b... Slanted part. Figure 7 Figure 10
Claims (2)
に、基板上の導体パターンとＩＣチップとをワイヤボン
デイグし、さらにＩＣチップを封止材で封止してなるＩ
Ｃモジュールを、カードに搭載するようにしたＩＣカー
ド用の半導体装置の製造方法において、前記ＩＣチップ
用のダイボンド材を、特定箇所を硬化の起点として該起
点から遠ざかる方向に順次硬化を進行させるようにした
ことを特徴とするＩＣカード用の半導体装置の製造方法
。(1) An IC formed by die-bonding an IC chip onto a substrate, wire-bonding the conductive pattern on the substrate and the IC chip, and then sealing the IC chip with a sealing material.
In a method of manufacturing a semiconductor device for an IC card, in which a C module is mounted on a card, the die-bonding material for the IC chip is cured sequentially in a direction away from a specific point as a starting point. A method of manufacturing a semiconductor device for an IC card, characterized in that:
記基板上に設けられたダイパッドにダイボンディングさ
れ、前記ダイボンド材は、上記ダイパッドの突出頂部を
硬化の起点として硬化が進行するようにされたことを特
徴とするＩＣカード用の半導体装置の製造方法。(2) In claim (1), the IC chip is die-bonded to a die pad provided on the substrate, and the die-bonding material is cured using a protruding top portion of the die pad as a starting point. A method for manufacturing a semiconductor device for an IC card, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63209539A JPH0259400A (en) | 1988-08-25 | 1988-08-25 | Production of semiconductor device for ic card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63209539A JPH0259400A (en) | 1988-08-25 | 1988-08-25 | Production of semiconductor device for ic card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0259400A true JPH0259400A (en) | 1990-02-28 |
Family
ID=16574484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63209539A Pending JPH0259400A (en) | 1988-08-25 | 1988-08-25 | Production of semiconductor device for ic card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0259400A (en) |
-
1988
- 1988-08-25 JP JP63209539A patent/JPH0259400A/en active Pending
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