JPH0260793A - Semiconductor device for ic card - Google Patents

Semiconductor device for ic card

Info

Publication number
JPH0260793A
JPH0260793A JP63210682A JP21068288A JPH0260793A JP H0260793 A JPH0260793 A JP H0260793A JP 63210682 A JP63210682 A JP 63210682A JP 21068288 A JP21068288 A JP 21068288A JP H0260793 A JPH0260793 A JP H0260793A
Authority
JP
Japan
Prior art keywords
chip
die
modulus
young
sealing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63210682A
Other languages
Japanese (ja)
Inventor
Sunao Fukutake
素直 福武
Yoshito Tanaka
義人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP63210682A priority Critical patent/JPH0260793A/en
Publication of JPH0260793A publication Critical patent/JPH0260793A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device for IC card with a high IC mechanical strength and operational reliability by a method wherein an IC chip is die- bonded on a substrate with a die bonding material having a Young's modulus less than a specific value, a conductor pattern on the substrate is wire-bonded to the IC chip, and the IC chip is sealed with a sealing material having a Young' s modulus less than a specific value. CONSTITUTION:As a die-bonding material 11A for die-bonding an IC chip 10 on a die pad 7, a resin having a Young's modulus of 50-kgf/mm<2> or less, such as a thermoset silicone resin, is used. By thermally setting the die-bonding material 11A, the IC chip 10 is bonded on a substrate 5 through the die pad 7. After an Au wire 12 is wire-bonded, a sealing material 13A, such as a photo- setting acrylic resin having a young's modulus of 200kgf/mm<2> or less is loaded by potting. In this manner, an IC module 3A is completed.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はＩＣカード用の半導体装置に係り、更に詳しく
は、カード搭載用のＣｈｉｐ　ｏｎ　Ｂｏａｒｄ型ＩＣ
モジュールに関する− ［従来の技術］ ＩＣカードは、コンパクトでありながら記憶容量が大き
く情報の読み書きができることから、近時急速に普及し
つつある。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device for an IC card, and more specifically, a chip on board type IC for mounting on a card.
Regarding Modules - [Prior Art] IC cards are becoming rapidly popular in recent years because they are compact, have a large storage capacity, and can read and write information.

第４図〜第】１図は従来のＩＣカードに係り、第４図並
びに第５図示のように、例えば塩化ビニールなどのプラ
スチック製のカード１の収納凹部内に、ＩＣカード用の
ＩＣチップを樹脂で封止してなるＩＣモジュール３を内
蔵・搭載して接着剤２で固着し、該ＩＣモジュール３に
形成した外部接続用の端子部４をカード１の表面と路面
−に露呈させた構成を採っている。そして、ＩＣカード
をカードリーダライタに装着した際には、上記端子部４
を介して情報の読み書きが行なわれるようになっている
。FIGS. 4 to 1 relate to a conventional IC card, and as shown in FIGS. 4 and 5, an IC chip for the IC card is placed in a storage recess of a card 1 made of plastic such as vinyl chloride. A structure in which an IC module 3 sealed with resin is built-in and mounted and fixed with an adhesive 2, and a terminal part 4 for external connection formed on the IC module 3 is exposed on the surface of the card 1 and the road surface. are taken. When the IC card is installed in the card reader/writer, the terminal section 4
Information is read and written through the .

第６図は前記ＩＣモジュール３を示している。FIG. 6 shows the IC module 3. As shown in FIG.

同図において、５はモジュール用の基板で、該基板の一
面上にはＩＣチップ接続用の導体パターン６並びに金属
製のダイパッド７が形成されており、また、基板５の他
面には上記導体パターン６とスルーホール８を介して接
続された端子４が形成されている。１０はＩＣチップで
、上記ダイパツド７上に、例えば熱硬化型のエポキシ系
樹脂等よりなるダイボンド材１１を加熱硬化させること
によってダイボンディングされており、また、ＩＣチッ
プ１０の接続端子部は、Ａｕ線１２によって前記導体パ
ターン６とワイヤボンディングによって電気的に接続さ
れている。１３は封止材で、熱硬化型あるいは光硬化型
の封止用樹脂（通常は熱硬化型のエポキシ系樹脂）より
なっており、ボッティグもしくはトランスファモールド
で形成されて前記ＩＣチップ１０を封入・保護するよう
になっている。In the figure, reference numeral 5 denotes a module substrate, on one side of which a conductive pattern 6 for connecting an IC chip and a metal die pad 7 are formed, and on the other side of the substrate 5 are formed the above-mentioned conductor. A terminal 4 connected to the pattern 6 via a through hole 8 is formed. Reference numeral 10 denotes an IC chip, which is die-bonded onto the die pad 7 by heating and curing a die-bonding material 11 made of, for example, thermosetting epoxy resin, and the connecting terminal portion of the IC chip 10 is made of Au. The wire 12 is electrically connected to the conductor pattern 6 by wire bonding. A sealing material 13 is made of a thermosetting or photocuring sealing resin (usually a thermosetting epoxy resin), and is formed by Bottig or transfer molding to encapsulate and enclose the IC chip 10. It is meant to be protected.

第７図は前記ＩＣモジュール３の製造工程を示すブロッ
ク図である。同図に示すように、まず工程Ｓ１で前記Ｉ
Ｃチップ１０がエポキシ系熱硬化型樹脂等よりなる前記
ダイボンド材１１によって前記基板５のダイパッド７上
に固着される。次に、工程６２のワイヤボンディング工
程で、ＩＣチップ１０と基板５の前記導体パターン６と
が接続される。続いて工程Ｓ３のポツティング工程で、
ＩＣチップ１０が前記封止材１３で封止され、封止材１
３が熱硬化型樹脂である場合にはこれが硬化した後、封
止材１３が工程Ｓ４の研磨工程で所定厚みまで研磨され
てＩＣモジュール３が完成される。FIG. 7 is a block diagram showing the manufacturing process of the IC module 3. As shown in the figure, first, in step S1, the I
The C chip 10 is fixed onto the die pad 7 of the substrate 5 by the die bonding material 11 made of epoxy thermosetting resin or the like. Next, in a wire bonding step 62, the IC chip 10 and the conductive pattern 6 of the substrate 5 are connected. Next, in the potting process of step S3,
The IC chip 10 is sealed with the sealing material 13, and the sealing material 1
When 3 is a thermosetting resin, after it is cured, the sealing material 13 is polished to a predetermined thickness in a polishing step S4, and the IC module 3 is completed.

なお、前記封止材１３をトランスファモールドで形成す
る場合には、前記工程Ｓ２の次に、工程Ｓ５のトランス
ファモールド工程で封止材１−３を所定厚みに形成する
ことによって、工程は終了する。In addition, when forming the sealing material 13 by transfer molding, the process is completed by forming the sealing material 1-3 to a predetermined thickness in a transfer molding process of step S5 after the step S2. .

［発明が解決しようとする課題］ ところで、上述した従来のＩＣカード用のＩＣモジュー
ル３は、その製造過程において、まずダイボンド工程後
にはダイボンド材１１の収縮応力によって、ＩＣチップ
１０の表面側には第８図に示すような引張応力が発生す
る。この引張残留応力の大きさは、ダイボンド材１１の
ヤング率によって左右され、高ヤング率のダイボンド材
である程引張残留応力値は大きくなる。[Problems to be Solved by the Invention] In the manufacturing process of the above-described conventional IC module 3 for an IC card, first, after the die-bonding process, the front surface of the IC chip 10 is damaged due to shrinkage stress of the die-bonding material 11. A tensile stress as shown in FIG. 8 is generated. The magnitude of this tensile residual stress depends on the Young's modulus of the die-bonding material 11, and the higher the Young's modulus of the die-bonding material, the greater the tensile residual stress value.

このダイボンド工程後のＩＣチップ１０表面の引張応力
は、第９図に示すように１次のポツティング工程時の前
記封止材１３の収縮によって圧縮応力側へ緩和されるが
、この緩和の度合いは封止材１３のヤング率によって左
右される。即ち、封止材１３が高ヤング率であればＩＣ
チップ１０の表面側に大きな圧縮応力を及ぼすことにな
り、封止材１３による圧縮応力がダイボンド材１１の引
張応力に打勝てばＩＣチップ１０の表面側には圧縮残留
応力が生じ、また、ダイボンド材１１による引張応力が
封止材１３の圧縮応力に打勝てばＩＣチップ１０の表面
側には依然として引張応力が残留する。The tensile stress on the surface of the IC chip 10 after this die bonding process is alleviated to the compressive stress side by the contraction of the sealing material 13 during the first potting process, as shown in FIG. 9, but the degree of this relaxation is It depends on the Young's modulus of the sealing material 13. That is, if the sealant 13 has a high Young's modulus, the IC
A large compressive stress will be exerted on the surface side of the chip 10, and if the compressive stress due to the sealing material 13 overcomes the tensile stress of the die bond material 11, compressive residual stress will be generated on the surface side of the IC chip 10, and the die bond If the tensile stress caused by the material 11 overcomes the compressive stress of the sealing material 13, the tensile stress still remains on the surface side of the IC chip 10.

さらに封止材１３を、熱硬化型樹脂のポツティングで形
成する場合は、続く封止材１３の研磨工程によって、Ｉ
Ｃチップ１０の表面側に圧縮応力を及ぼしていた封止材
１３の一部が除去されるため、封止材１３による圧縮応
力は緩和される。なお、ＩＣカードは規格上その厚みを
０．７８ｍｍに規定されていて、ＩＣモジュール３の厚
みは最大０．６８ｍｍ以下に制約される。また、ＩＣチ
ップ１０の厚みが０．３ｍｍあり、他の要素要素の厚み
を勘案すると封止材１３の厚みはＩＣチップ１０の表面
上においては０．１８ｍｍ程度以下に制約される。（な
お、封止材１３をトランスファモールド法で形成する場
合は、当初からＩＣチップ１０上において封止材１３の
厚みは０．１８ｍｍ以下に制約されているので、研磨は
不要で研磨による残留応力変化はない。また、封止材１
３を光硬化型の樹脂とした時には、ボッティング後樹脂
上にガラス板を押付けて厚みを規制して、この状態で光
照射により樹脂を硬化させるので、この場合も封止工程
後は応力変化はない。）上述したようにＩＣモジュール
３完成後のＩＣチップ１０の残留応力は、前記したダイ
ボンド材１１のヤング率と、封止材１３のヤング率とに
よって大きく左右される。しかしながら、従来のＩＣモ
ジュール３においては、ダイボンド材１１並びに封止材
１３の各々のヤング率、並びにその組合わせについては
何等考慮がなされておらず、モジュール完成後、第１０
図示のようにＩＣチップ１０が上に凸にそったり、第１
１図示のように下に凸にそったりし、ＩＣチップ１０の
図示上面側もしくは下面側に大きな引張応力が残留しが
ちであった。このため、残留応力と同一方向の外力がＩ
Ｃチップに加わった場合、比較的たやす＜ＩＣチップ１
０の破損が生じるという問題が指摘されていた。Furthermore, when the sealant 13 is formed by potting thermosetting resin, the I
Since a portion of the sealing material 13 that was exerting compressive stress on the surface side of the C-chip 10 is removed, the compressive stress caused by the sealing material 13 is relaxed. Note that the thickness of the IC card is specified to be 0.78 mm according to the standard, and the thickness of the IC module 3 is restricted to a maximum of 0.68 mm or less. Further, the thickness of the IC chip 10 is 0.3 mm, and considering the thickness of other elements, the thickness of the sealing material 13 on the surface of the IC chip 10 is limited to about 0.18 mm or less. (In addition, when forming the encapsulant 13 by transfer molding, the thickness of the encapsulant 13 on the IC chip 10 is restricted from the beginning to 0.18 mm or less, so polishing is unnecessary and residual stress due to polishing There is no change.Also, sealing material 1
When 3 is a photo-curable resin, a glass plate is pressed onto the resin after botting to control the thickness, and the resin is cured by light irradiation in this state, so in this case as well, there is no stress change after the sealing process. There isn't. ) As described above, the residual stress of the IC chip 10 after the IC module 3 is completed is largely influenced by the Young's modulus of the die bonding material 11 and the Young's modulus of the sealing material 13 described above. However, in the conventional IC module 3, no consideration is given to the Young's modulus of each of the die bonding material 11 and the sealing material 13, and the combination thereof.
As shown in the figure, the IC chip 10 has a convex shape and the first
As shown in FIG. 1, the IC chip 10 was curved downward in a convex manner, and a large tensile stress tended to remain on the top or bottom side of the IC chip 10 in the drawing. Therefore, the external force in the same direction as the residual stress is I
When added to C chip, it is relatively easy <IC chip 1
It was pointed out that there was a problem that 0 damage occurred.

なお従前一般的には、高ヤング率のダイボンド材１１と
高ヤング率の封止材１３とを組合わせて用いることが多
く、例えば、ヤング率が３００〜４００Ｋｇｆ／ｍｍ２
程度の熱硬化型エポキシ樹脂系のダイボンド材１１と、
ヤング率が５００〜−６００Ｋｇｆ／ｍｍ”程度の熱硬
化型エポキシ系の樹脂封止材１３とがしばしば用いられ
ていた。Note that conventionally, a die bonding material 11 with a high Young's modulus and a sealing material 13 with a high Young's modulus are often used in combination, for example, a material with a Young's modulus of 300 to 400 kgf/mm
a thermosetting epoxy resin-based die bonding material 11 of
A thermosetting epoxy resin sealing material 13 having a Young's modulus of about 500 to -600 Kgf/mm'' has often been used.

この場合、ダイボンド１１のヤング率が例えば３３０Ｋ
ｇｆ／ｍｍ”、封止材１３のヤング率が５５０Ｋｇｆ／
ｍｍ”とされた時、第３図で特性線Ｃとして示すように
、ダイボンディング後にはＩＣチップ１０の表面側に（
＋）８５ＭＰａの引張応力が生じ、研磨工程後において
もＩＣチップ１０の表面には（＋）５０ＭＰａ強の引張
応力が生じている。因みに、ＩＣチップ１０の破壊限界
値は、引張応力で（＋）１００ＭＰａ、圧縮応力で（−
）５００ＭＰ　ａ程度であるため、上記したダイボンド
工程によって生じるＩＣチップ１０の引張応力は、組立
て工程時のＩＣチップクラックの発生や、カード化した
後のＩＣチップ破壊限界値の低下などを招来し、製造歩
留り並びに製品の信頼性を著しく劣化させるという問題
があった。さらに、高ヤング率同士のダイボンド材１１
と封止材１３とを組合わせた場合には、各材料ロット間
の材料定数のバラツキ、硬化工程のバラツキなどによっ
て、各材料に起因する応力の関係が大きく変化し易く、
モジュール完成時の残留応力のバラツキが大きく、残留
応力値制御が困難であるいという問題もあった。In this case, the Young's modulus of the die bond 11 is, for example, 330K.
gf/mm”, and the Young’s modulus of the sealing material 13 is 550 Kgf/
mm", as shown by characteristic line C in FIG. 3, after die bonding, there is a (
A tensile stress of +)85 MPa was generated, and even after the polishing process, a tensile stress of a little more than (+)50 MPa was generated on the surface of the IC chip 10. Incidentally, the fracture limit value of the IC chip 10 is (+) 100 MPa for tensile stress and (-) for compressive stress.
) 500 MPa, the tensile stress of the IC chip 10 caused by the above-mentioned die bonding process may cause cracks in the IC chip during the assembly process and a decrease in the breaking limit value of the IC chip after it is made into a card. There was a problem in that manufacturing yield and product reliability were significantly degraded. Furthermore, die bond material 11 with high Young's modulus
When the sealing material 13 is combined with the sealing material 13, the relationship between the stresses caused by each material tends to change greatly due to variations in material constants between each material lot, variations in the curing process, etc.
There was also the problem that the residual stress at the time of module completion varied widely, making it difficult to control the residual stress value.

従って５本発明の解決すべき技術的課題は上述した従来
技術のもつ問題点を解消することにあり、その目的とす
るところは、ＩＣチップの残留応力を軽減し、以って製
造歩留りが向上でき、信頼性の高いＩＣカード用の半導
体装［（ＩＣモジュール）を提供することにある。Therefore, the technical problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and its purpose is to reduce the residual stress of IC chips, thereby improving manufacturing yield. Our objective is to provide a highly reliable semiconductor device (IC module) for an IC card.

［課題を解決するための手段］ 本発明の上記した目的は、基板上にＩＣチップをダイボ
ンド材によってダイボンディングすると共に、基板上の
導体パターンとＩＣチップとをワイヤボンディングし、
さらにＩＣチップを封止材で封止してなるＩＣモジュー
ルを、カードに搭載するようにしたＩＣカード用の半導
体装置において、前記ダイボンド材のヤング率を５０Ｋ
ｇｆ／ｍｍ”以下、前記封止材のヤング率を２００Ｋｇ
ｆ／　ｍ　ｍ　”以下とすることによって達成される。[Means for Solving the Problems] The above-mentioned object of the present invention is to die-bond an IC chip onto a substrate using a die-bonding material, and to wire-bond a conductor pattern on the substrate and the IC chip,
Furthermore, in a semiconductor device for an IC card in which an IC module formed by sealing an IC chip with a sealing material is mounted on a card, the Young's modulus of the die bonding material is 50K.
gf/mm” or less, the Young’s modulus of the sealing material is 200 kg.
f/mm” or less.

［作用］ 本願発明者らは種々検討の結果、ヤング率が５０Ｋｇｆ
／ｍｍ”以下のダイボンド材と、ヤング率が２００　Ｋ
　ｇ　ｆ　／ｍｍ’以下の封止材とを組合わせて用いる
ことによって、ＩＣモジュール作製後のＩＣチップの残
留応力が著しく軽減できることを見出した。即ち実験に
よれば、比較的ヤング率の小さい（比較的軟らかい）ダ
イボンド材及び封止相同゛士を組合わせて用いることに
よって、ヤング率の大きいダイボンド材と封止材同士の
組合わせや、ヤング率の大きなダイボンド材とヤング率
の小さな封止材との組合わせ、あるいは、ヤング率の小
さなダイボンド材とヤング率の大きな封止材の組合わせ
に比して、ＩＣチップの残留応力が著しく軽減・改首さ
れることが確認できた。また、ＩＣモジュールをカード
に搭載してＩＣカード化した後に、ＩＣカードに外力が
加った際のＩＣチップの破壊限界値も向上できることが
確認された。[Function] As a result of various studies, the inventors of the present application found that the Young's modulus was 50 Kgf.
/mm” or less and Young’s modulus is 200 K.
It has been found that the residual stress of the IC chip after the IC module is fabricated can be significantly reduced by using it in combination with a sealing material of g f /mm' or less. In other words, experiments have shown that by using a combination of a die-bonding material with a relatively small (relatively soft) Young's modulus and a sealing material, it is possible to combine a die-bonding material and a sealing material with a large Young's modulus, and to The residual stress of the IC chip is significantly reduced compared to the combination of a die-bonding material with a large Young's modulus and a sealing material with a small Young's modulus, or a combination of a die-bonding material with a small Young's modulus and a sealing material with a large Young's modulus.・It has been confirmed that the head will be changed. Furthermore, it was confirmed that after an IC module is mounted on a card to form an IC card, the destruction limit value of the IC chip when an external force is applied to the IC card can be improved.

［実施例］ 以下本発明を図示した実施例によって説明する。[Example] The present invention will be explained below with reference to illustrated embodiments.

第１図は本発明の第１実施例に係るＩＣカード用の半導
体装置たるＩＣモジュールを示す図で、同図において前
記第６図示の従来構成と同一の部材には同一符号を付し
、その説明は重複を避けるため省略する。FIG. 1 is a diagram showing an IC module as a semiconductor device for an IC card according to a first embodiment of the present invention. In the figure, the same members as those in the conventional configuration shown in FIG. Explanations are omitted to avoid duplication.

該第１実施例のＩＣモジュール３Ａは、前記第６図の従
来例と同等構造をとり同一手法によって作製されている
も、前記ＩＣチップ１０を前記ダイパッド７にダイボン
ディングによって固着するだめのダイボンド材１１Ａと
して、ヤング率が、５０Ｋｇｆ／ｍｍ２以下の樹脂、例
えば熱硬化型シリコーンゴム系の樹脂（ゴム系ペースト
）などが用いられている。該ダイボンド材１１Ａの厚み
は約３０μｒｎに設定されており、ダイボンド材１１Ａ
を加熱硬化することによって、厚み約３００μｍのＩＣ
チップ１０が前記基板５上にダイパッド７を介して固着
される。The IC module 3A of the first embodiment has the same structure as the conventional example shown in FIG. As 11A, a resin having a Young's modulus of 50 kgf/mm 2 or less, such as a thermosetting silicone rubber resin (rubber paste), is used. The thickness of the die bonding material 11A is set to approximately 30μrn, and the thickness of the die bonding material 11A is set to approximately 30 μrn.
By heating and curing, an IC with a thickness of approximately 300 μm
A chip 10 is fixed onto the substrate 5 via a die pad 7.

そして、前述の如く前記Ａｕ線１２がワイヤボンディン
グされた後、封止材１３Ａがポツティングによって充填
され、然る後、所定厚みに規制されてＩＣモジュール３
Ａが完成される。この封止材１３Ａは、ヤング率が２０
０Ｋｇｆ／ｍｍ”以下の光硬化型のアクリル系樹脂や熱
硬化型のエポキシ系樹脂などが用いられており、光硬化
型の樹脂を用いた場合には、ボッティグ後ガラス板を押
付けて厚みを規制した状態で光を照射して樹脂を硬化し
て封止材１３Ａを形成し、また、熱硬化型の樹脂を用い
た場合には、樹脂を加熱硬化させた後所磨して封止材１
３Ａを形成する。そしてこのようにして、ＩＣチップ１
０の表面上における封止材１３の厚みは最大値で１８０
μｍ程度になるように設定される。After the Au wire 12 is wire-bonded as described above, the sealing material 13A is filled by potting, and then the IC module 3 is regulated to a predetermined thickness.
A is completed. This sealing material 13A has a Young's modulus of 20
Photo-curing acrylic resins and thermosetting epoxy resins with a tolerance of 0 Kgf/mm" or less are used. When using photo-curing resins, the thickness is regulated by pressing a glass plate after bottling. In this state, the resin is irradiated with light to harden to form the encapsulant 13A, and when a thermosetting resin is used, the resin is heated and cured and then polished to form the encapsulant 13A.
Form 3A. And in this way, IC chip 1
The maximum thickness of the sealing material 13 on the surface of 0 is 180 mm.
It is set to approximately μm.

第２図は本発明の第２実施例に係るＩＣカード用の半導
体装置たるＩＣモジュールを示す図で、該実施例におけ
るＩＣモジュール３Ｂは、封止材をトランスファモール
ドによって形成しである。FIG. 2 is a diagram showing an IC module which is a semiconductor device for an IC card according to a second embodiment of the present invention, and an IC module 3B in this embodiment has a sealing material formed by transfer molding.

同図に示す基板５Ａの一面には、前記導体パターン６並
びにダイパッド７が形成されていると共に、該基板５Ａ
の他面には前記スルーホール８を介して導体パターン６
と接続された前記端子部４が形成されている。そして、
前記ＩＣチップ１０が、第１実施例のダイボンド材１１
Ａと同一の材料。The conductor pattern 6 and die pad 7 are formed on one surface of the substrate 5A shown in the same figure, and the substrate 5A is
A conductive pattern 6 is formed on the other surface through the through hole 8.
The terminal portion 4 connected to the terminal portion 4 is formed. and,
The IC chip 10 is made of the die bonding material 11 of the first embodiment.
Same material as A.

ヤング率、厚みのダイボンド材１１Ａによってダイボン
ディングされた後、前記Ａｕ線１２によってＩＣチップ
１０と導体パターン６とがワイヤボンディングされ、然
る後、第１実施例の封止材１３Δと同一の材料、ヤング
率の封止材１３Ａ′をトランスファモールド法で形成す
ることによって、ＩＣモジュール３Ｂが完成されるよう
になっている。なお、ＩＣチップ１０の表面上における
封止材１３Ａ′の厚みは前記第１実施例と同様の厚みに
設定されている。After die bonding with the die bonding material 11A having a Young's modulus and thickness, the IC chip 10 and the conductor pattern 6 are wire bonded with the Au wire 12, and then the same material as the sealing material 13Δ of the first embodiment is used. , the IC module 3B is completed by forming the sealing material 13A' having a Young's modulus by a transfer molding method. The thickness of the sealing material 13A' on the surface of the IC chip 10 is set to the same thickness as in the first embodiment.

第３図は、上記した本発明によるＩＣモジュールにおけ
るＩＣチップ１０表面の残留応力と、本発明との対比の
ために示す参考例におけるＩＣモジュールのＩＣチップ
１０表面の残留応力とを、各プロセス（ダイボンディン
グ後、ポツティングによる封止後、モジュール完成後）
毎に示す残留応力特性図である。同図において、特性線
Δが、ダイボンド材のヤング率を０．２Ｋｇｆ／ｍｍ２
（熱硬化型シリコーンゴム系ダイボンド材）とし、封止
材のヤング率を２０Ｋｇｆ／ｍｍ２　（光硬化型アクリ
ル樹脂系封止材）とした本発明の実験例に係るデータを
示している。また、同図の特性線Ｂ（参考例１）が、ダ
イボンド材のヤング率を０．２Ｋｇｆ／ｍｍ”　　（熱
硬化型シリコーンゴム系ダイボンド材）とし、封止材の
ヤング率を５５０Ｋｇｆ／ｍｍ”　　（熱硬化型エポキ
シ樹脂系封止材）としたデータを、特性線Ｃ（参考例２
）が、ダイボンド材のヤング率を３３０Ｋｇｆ／ｍｍ２
　（熱硬化型エポキシ系ダイボンド材）とし、封止材の
ヤング率を５５０Ｋｇｆ／ｍｍ”　　（熱硬化型エポキ
シ樹脂系封止材）としたデータを、特性線Ｄ（参考例３
）が、ダイボンド材のヤング率を３３０Ｋｇｆ／ｍｍ２
　（熱硬化型エポキシ系ダイボンド材）とし、封止材の
ヤング率を２０　Ｋ　ｇ　ｆ　／＋ａｍ２（光硬化型ア
クリル樹脂系封止材）としたデータをそれぞれ示してい
る。なお、同図における残留応力値の（＋）側は引張応
力を、（−）側は圧縮応力をそれぞれ示しており、応力
測定はＩＣチップ１０の表面について行なった。FIG. 3 shows the residual stress on the surface of the IC chip 10 in the IC module according to the present invention described above, and the residual stress on the surface of the IC chip 10 in the IC module in the reference example shown for comparison with the present invention, for each process ( After die bonding, after potting sealing, after module completion)
It is a residual stress characteristic diagram shown in each case. In the same figure, the characteristic line Δ represents the Young's modulus of the die bonding material as 0.2Kgf/mm2.
(thermosetting silicone rubber die bonding material) and the Young's modulus of the sealing material was 20 Kgf/mm2 (photocuring acrylic resin sealing material). In addition, characteristic line B (Reference Example 1) in the same figure indicates that the Young's modulus of the die bonding material is 0.2 Kgf/mm" (thermosetting silicone rubber die bonding material) and the Young's modulus of the sealing material is 550 Kgf/mm". (Thermosetting epoxy resin encapsulant) data is changed to characteristic line C (Reference example 2)
), the Young's modulus of the die bonding material is 330Kgf/mm2
(thermosetting epoxy resin sealing material) and the Young's modulus of the sealing material was 550 Kgf/mm" (thermosetting epoxy resin sealing material), characteristic line D (Reference example 3)
), the Young's modulus of the die bonding material is 330Kgf/mm2
(thermosetting epoxy die-bonding material) and the Young's modulus of the sealing material is 20 K g f /+am2 (photocuring acrylic resin sealing material). Note that the (+) side of the residual stress value in the figure indicates tensile stress, and the (-) side indicates compressive stress, and the stress measurements were performed on the surface of the IC chip 10.

同図から明らかなように、本発明の実験例による特性線
Ａおいては、ダイボンディング後において残留応力が約
（＋）１２ＭＰａ、ポツティング・光照射による封止後
（モジュール完成後）における残留応力が約ＯＭＰ　ａ
となり、各参考例に比して残留応力が殆んどない極めて
良好な結果を示し、その残留応力軽減効果は顕著である
。このため、組立て工程時におけるＩＣチップＩＯの破
損やカ−ド化した後のＩＣチップ１０の破壊限界値の低
下を招来することなく、製造歩留り並びに製品の信頼べ
が大幅に向上できることが確認された。これに対し、参
考例として示した特性線Ｃ（高ヤング率のダイボンド材
と高ヤング率の封止材の組合わせ）や、特性線Ｄ（高ヤ
ング率のダイボンド材と低ヤング率の封止材の組合わせ
）では、モジュール完成後においてＩＣチップの表面側
に大きな引張応力が残留しており、ＩＣチップの破壊限
界値を低下させていることは明瞭である。また、参考例
として示した特性線Ｂ（低ヤング率のダイボンド材と高
ヤング率の封止材の組合わせ）は、モジュール完成後の
残留応力は比較的小さなものとなっているが、（）１５
ＭＰａ程度の残留応力が存在していることは否めず、且
つ研磨前の製造途上には大きな残留応力が生じており、
製造過程でのＩＣチップの損傷の虞れがある。As is clear from the figure, in the characteristic line A according to the experimental example of the present invention, the residual stress is approximately (+) 12 MPa after die bonding, and the residual stress after sealing by potting and light irradiation (after module completion). is approximately OMP a
Compared to each reference example, this shows an extremely good result with almost no residual stress, and the residual stress reducing effect is remarkable. Therefore, it has been confirmed that the manufacturing yield and product reliability can be significantly improved without causing damage to the IC chip IO during the assembly process or lowering the destruction threshold of the IC chip 10 after it is made into a card. Ta. In contrast, characteristic line C (a combination of a high Young's modulus die bond material and a high Young's modulus encapsulant material) shown as a reference example, and characteristic line D (a combination of a high Young's modulus die bond material and a low Young's modulus encapsulant material), It is clear that in the combination of materials (material combinations), a large tensile stress remains on the surface side of the IC chip after the module is completed, lowering the fracture limit of the IC chip. In addition, characteristic line B (a combination of a low Young's modulus die-bonding material and a high Young's modulus sealing material) shown as a reference example shows that the residual stress after the module is completed is relatively small; 15
It is undeniable that residual stress of about MPa exists, and large residual stress occurs during the manufacturing process before polishing.
There is a risk of damage to the IC chip during the manufacturing process.

次に示す表−１は、ダイボンド材と封止材のヤング率と
、モジュール化した後のＩＣチップの表面側の残留応力
との関係を実験によって求めた結果を示している。Table 1 shown below shows the results of experiments on the relationship between the Young's modulus of the die-bonding material and the sealing material and the residual stress on the surface side of the IC chip after modularization.

（表−１） 上記表−１から明らかなように、サンプルＮｏ。(Table-1) As is clear from Table 1 above, sample No.

５．６が残留応力が極めて少ない良好な結果を示してい
る。5.6 shows good results with extremely low residual stress.

なお、上記表−１には示していないが、実験によれば多
少のバラツキはあるも、ダイボンド材のヤング率を５０
　Ｋ　ｇ　ｆ　／ｍｍ”以下、封止材のヤング率を２０
０　Ｋ　ｇ　ｆ　７ｍｍ２以下の範囲内にしてこれを組
合わせれば、ＩＣモジュール化した後のＩＣチップの残
留応力は大幅に低減できることが確認され、この条件を
満たすヤング率であれば、ダイボンド材及び封止材は、
エポキシ系樹脂、シリコーン系樹脂、アクリル系樹脂、
フェノール系樹脂など任意の樹脂を用いることができ、
樹脂材料の種類は問われない。Although it is not shown in Table 1 above, according to experiments, although there is some variation, the Young's modulus of the die bonding material is 50.
K g f /mm" or less, the Young's modulus of the sealing material is 20
It has been confirmed that by combining these within the range of 0 K g f 7 mm2 or less, the residual stress of the IC chip after being made into an IC module can be significantly reduced.If the Young's modulus satisfies this condition, the die bonding material and The sealing material is
Epoxy resin, silicone resin, acrylic resin,
Any resin such as phenolic resin can be used,
The type of resin material does not matter.

［発明の効果コ 叙上のように本発明によれば、ＩＣチップの残留応力が
大幅に低減でき、製造歩留りが向上すると共に、ＩＣチ
ップの破壊限界値を引下げる虞れがないので、ＩＣの機
械的強度・動作信頼性の高いＩＣカード用の半導体装［
（ＩＣモジュール）を提供でき、その産業的価値は多大
である。[Effects of the Invention] As described above, according to the present invention, the residual stress of the IC chip can be significantly reduced, the manufacturing yield can be improved, and there is no risk of lowering the fracture limit value of the IC chip. Semiconductor device for IC cards with high mechanical strength and operational reliability [
(IC module), and its industrial value is enormous.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１実施例に係るＩＣカード用のＩＣ
モジュールの断面図、第２図は本発明の第２実施例に係
るＩＣカード用のＩＣモジュールの断面図、第３図は本
発明による実験例と参考例の各製造プロセス毎のＩＣチ
ップの残留応力を示す残留応力特性図、第４図〜第１１
図は従来例に係り、第４図はＩＣカードの平面図、第５
図はＩＣカードの要部断面図、第６図はＩＣモジュール
の断面図、第７図はＩＣモジュールの製造工程を示すブ
ロック図、第８図及び第９図はＩＣモジュールの製造過
程でＩＣチップに生じる応力を説明するための模式化し
た説明図、第１０図及び第１１図はＩＣチップのそりを
示す説明図である。 ■・・・・・・カード、２・・・・・・接着剤、３．３
Ａ、３Ｂ・・・・・ＩＣモジュール、４・・・・・・端
子部、５，５Ａ・・・・・・モジュール用の基板、６・
・・・・・導体パターン、７・・・・・・ダイパッド、
８・・・・・・スルーホール、１０・・・・・・ＩＣチ
ップ、１１．ＩＩＡ・・・・・・ダイボンド材、ｌ・・
・・・Ａｕ線、 １３゜ １３Ａ。 ３Ａ ′・・・・・・封止 材。 第１図 第２図 倦８図 第９図 １′ 第１０図 ノ 第 図FIG. 1 shows an IC for an IC card according to a first embodiment of the present invention.
2 is a cross-sectional view of an IC module for an IC card according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of an IC module for an IC card according to a second embodiment of the present invention. FIG. Residual stress characteristic diagrams showing stress, Figures 4 to 11
The figures relate to a conventional example; Fig. 4 is a plan view of an IC card; Fig. 5 is a plan view of an IC card;
The figure is a cross-sectional view of the main parts of an IC card, Figure 6 is a cross-sectional view of an IC module, Figure 7 is a block diagram showing the manufacturing process of an IC module, and Figures 8 and 9 are a cross-sectional view of the IC module. FIGS. 10 and 11 are schematic explanatory diagrams for explaining the stress generated in the IC chip, and are explanatory diagrams showing the warping of the IC chip. ■・・・Card, 2・・・Adhesive, 3.3
A, 3B...IC module, 4...Terminal section, 5, 5A...Module board, 6.
...Conductor pattern, 7...Die pad,
8...Through hole, 10...IC chip, 11. IIA・・・Die bond material, l...
...Au wire, 13°13A. 3A'...Sealing material. Figure 1 Figure 2 Figure 8 Figure 9 Figure 1' Figure 10 Figure 1

Claims (1)

【特許請求の範囲】[Claims] 　基板上にＩＣチップをダイボンド材によつてダイボン
デイングすると共に、基板上の導体パターンとＩＣチッ
プとをワイヤボンデイグし、さらにＩＣチップを封止材
で封止してなるＩＣモジユールを、カードに搭載するよ
うにしたＩＣカード用の半導体装置において、前記ダイ
ボンド材のヤング率を５０Ｋｇｆ／ｍｍ＾２以下、前記
封止材のヤング率を２００Ｋｇｆ／ｍｍ＾２以下とした
ことを特徴とするＩＣカード用の半導体装置。An IC module is mounted on a card by die-bonding an IC chip onto a substrate using a die-bonding material, performing wire bonding between a conductive pattern on the substrate and the IC chip, and further sealing the IC chip with a sealing material. In the semiconductor device for an IC card, the die-bonding material has a Young's modulus of 50 Kgf/mm^2 or less, and the sealing material has a Young's modulus of 200 Kgf/mm^2 or less. Semiconductor equipment.
JP63210682A 1988-08-26 1988-08-26 Semiconductor device for ic card Pending JPH0260793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63210682A JPH0260793A (en) 1988-08-26 1988-08-26 Semiconductor device for ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63210682A JPH0260793A (en) 1988-08-26 1988-08-26 Semiconductor device for ic card

Publications (1)

Publication Number Publication Date
JPH0260793A true JPH0260793A (en) 1990-03-01

Family

ID=16593364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63210682A Pending JPH0260793A (en) 1988-08-26 1988-08-26 Semiconductor device for ic card

Country Status (1)

Country Link
JP (1) JPH0260793A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63233834A (en) * 1987-03-24 1988-09-29 株式会社　明治ゴム化成 Urethane rubber roll and manufacture thereof
JPH02120840U (en) * 1989-03-15 1990-09-28
JP2000299553A (en) * 1999-04-13 2000-10-24 Ricoh Microelectronics Co Ltd Manufacture of electronic circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63233834A (en) * 1987-03-24 1988-09-29 株式会社　明治ゴム化成 Urethane rubber roll and manufacture thereof
JPH0669745B2 (en) * 1987-03-24 1994-09-07 株式会社明治ゴム化成 Urethane rubber roll and method for producing the same
JPH02120840U (en) * 1989-03-15 1990-09-28
JP2000299553A (en) * 1999-04-13 2000-10-24 Ricoh Microelectronics Co Ltd Manufacture of electronic circuit board

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