JPH0257630U - - Google Patents
Info
- Publication number
- JPH0257630U JPH0257630U JP13761588U JP13761588U JPH0257630U JP H0257630 U JPH0257630 U JP H0257630U JP 13761588 U JP13761588 U JP 13761588U JP 13761588 U JP13761588 U JP 13761588U JP H0257630 U JPH0257630 U JP H0257630U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- input terminal
- circuit
- flop circuit
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13761588U JPH0257630U (en, 2012) | 1988-10-21 | 1988-10-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13761588U JPH0257630U (en, 2012) | 1988-10-21 | 1988-10-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0257630U true JPH0257630U (en, 2012) | 1990-04-25 |
Family
ID=31399198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13761588U Pending JPH0257630U (en, 2012) | 1988-10-21 | 1988-10-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0257630U (en, 2012) |
-
1988
- 1988-10-21 JP JP13761588U patent/JPH0257630U/ja active Pending