JPH0256040B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous motor control device, and more particularly to a synchronous motor drive control device that takes into account instantaneous power outage countermeasures for a drive control circuit using a voltage source inverter.

Generally, when controlling a motor using an inverter circuit, it is an important issue how to take measures against instantaneous power outages. Particularly in drive control methods using stationary equipment, it is difficult to store energy, so if the power goes out even for a short time, the equipment will stop and the system will go down.

Generally, continued operation is guaranteed for a ``50% voltage drop for 1 second,'' but this means that measures must be taken to ensure that the control power supply can operate normally for at least 1 second.
In actual operation, it is intended to continue operation even when the power supply voltage fluctuates. Also, in terms of the main circuit
At 100% load, the holding time until the load motor loses synchronization is approximately 50ms. Therefore, it is necessary to guarantee even more instantaneous power outages. Therefore,
In order to meet even higher demands, if a momentary power outage occurs while the inverter is operating as a motor load, the inverter operation will be temporarily stopped in order to continue operation, and at the same time the magnitude, phase and frequency of the motor's back electromotive force will be detected. When the power is restored, it is necessary to turn on the inverter again, matching the phase of the motor, to resume operation smoothly.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to use a power conversion unit having a forward conversion circuit, a chopper circuit, and an inverter circuit to convert smoothing capacitors into smoothing capacitors when the power is turned on again when the power is restored. The purpose of this invention is to prevent inrush current from flowing into the motor, prevent commutation failure, and restart operation smoothly by accurately matching the voltage phase of the inverter circuit with the phase of the back electromotive force of the motor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A drive control device for a synchronous motor according to an embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, 1 is an AC power supply, 2 is an AC power supply 1
For example, a rectifier circuit 2 includes a diode 2a. A chopper circuit 3 adjusts the DC voltage rectified by the rectifier circuit 2, and includes a thyristor 19 and a feedback diode (not shown). 4 is an inverter circuit connected to the chopper circuit 3 via a DC reactor 5, and includes a thyristor 20 and a feedback diode 21. 7 is a first capacitor connected between the output side of the rectifier circuit 2 and the input side of the chopper circuit 3, and 8 is a second capacitor connected between the output side of the chopper circuit 3 and the input side of the inverter circuit 4. It is used to smooth the DC voltage. 9 is a load connected to the inverter circuit 4 via the switch 6, and is a permanent magnet type electric motor 9.
It has a to 9n.

10 is a first voltage setting device that sets the lower limit voltage of the first capacitor 7; 11 is a first voltage setting device;
A first transformer 12 is an isolation transformer that detects the voltage of the capacitor 7, and 12 is a first voltage setting device 1.
This is a first matching circuit which receives as input the voltage of the first transformer 11, which is the voltage VS1 of 0. Reference numeral 13 denotes a first amplifier circuit which receives the deviation output voltage of the first matching circuit 12 as an input, and has input/output characteristics as shown in the figure. 14 is a second voltage setter that outputs the voltage setting value of the second capacitor 8; 15 is a second transformer that is an isolation transformer that detects the voltage of the second capacitor 8; 16 is the first amplifier circuit 1
3, the output of the second voltage setter 14, and the output of the second transformer 15. 17 is this second matching circuit 1
A second amplifier circuit which inputs the deviation output voltage of No. 6 forms an automatic voltage adjustment amplifier. 18 is a phase control circuit which receives the amplified output voltage of the second amplifier circuit 17 as an input.

22 is a phase detection transformer as an induced voltage detection circuit that detects the phase of the induced voltage of the load 9; 23;
is a filter circuit for removing harmonic components of the voltage detected by this phase detection transformer 22, and resistor 2
4a, 24b and a T-shaped circuit consisting of a capacitor 25. 26 is a zero voltage detection circuit that detects a zero value of voltage. A third matching circuit 27 receives the output signal of the zero voltage detection circuit 26, and forms a part of the phase lock circuit 28. This phase lock circuit 28 is
It has a function of outputting a pulse signal having a pulse width corresponding to the phase difference of the pulse signals input to the third matching circuit 27. 29 is a low-pass filter which receives the output signal of the phase lock circuit 28, 30 is a fourth matching circuit, and 31 is this fourth matching circuit.
A third amplifier inputs the deviation output signal of the matching circuit 30, which inverts the polarity of the digital voltage signal from the low-pass filter 29 and amplifies it.
32 is a voltage-frequency conversion circuit that converts the output voltage signal of the third amplifier 31 into a frequency. 33 is a ring counter that operates by receiving the frequency signal from the voltage-frequency conversion circuit 32; 34 is a logic circuit that receives the signal from the ring counter 33;
35 is a gate circuit.

36 is a phase correction circuit in which the relationship between frequency and phase difference is defined and returns a phase correction signal corresponding to the output signal of the third amplifier 31 to the phase lock circuit 28; 37 is a power failure detection transformer; and 38 is a power failure detection circuit. , 39 is a fifth matching circuit.

FIG. 4 shows one phase of an inverter circuit, and this inverter circuit has thyristors 20a to 20d as thyristor switches 20. These thyristors 20a to 20d form a bridge circuit, and a parallel circuit consisting of a commutating capacitor 40 and a commutating resistor 41 is connected to the bridge side of this bridge circuit. The bridge circuit is a commutation reactor 42a
are connected to the positive electrode side through the commutation reactor 42b, and to the negative electrode side through the commutation reactor 42b. Also, one phase of AC power is output from the bridge side of the bridge circuit. Commutation diodes 21a to 21b are connected in parallel with the bridge circuit.
The cathode side of the series circuit is connected to the positive electrode and the anode side is connected to the negative electrode, and the connection point of the commutating diodes 21a and 21b and the bridge side of the bridge circuit are connected by a common line. Also, the thyristors 20a and 20 of the bridge circuit
A commutating auxiliary thyristor 4 is connected between the connection point b and the positive electrode side of the first capacitor (auxiliary charging capacitor) 7.
3 and reactor 44 are connected to form an auxiliary charging loop. The first capacitor 7 is connected between the positive potential side and the negative potential side on the input side of the chopper circuit 3, and the second capacitor 8 is connected between the positive potential side and the negative potential side between the DC input side of the inverter circuit 4 and the output side of the chopper circuit. Connected between the negative potential sides.

In the drive control device having the above configuration, when the power supply 1 is normal, the DC output voltage of the rectifier circuit 2 is adjusted to a predetermined value by the chopper circuit 3. At this time, the first and second capacitors 7 and 8 are charged to a predetermined voltage value. The DC voltage adjusted by the chopper circuit 3 is converted into an AC voltage of a predetermined frequency by the inverter circuit 4, and is supplied to the permanent magnet motors 9a to 9n through the switch 6.

Generally, in the second matching circuit 16, the second
The charging voltage of the capacitor 8 and the second voltage setting device 1
4 is amplified by the second amplification circuit 17,
This amplified voltage signal was input to the phase control circuit 18, thereby controlling the chopper circuit 3.

If a power outage occurs here, the first
Since the voltage of the capacitor 7 is higher than the voltage of the second capacitor 8, the voltage of the second capacitor 8 is maintained at the setting value of the second voltage setter 14 by the chopper circuit 3, but as time passes The voltage of the first capacitor 7 decreases due to discharge.
When the power is restored in this state, the voltage of the first capacitor 7 is rapidly raised to the output voltage of the rectifier circuit 2, so that the voltage of the first capacitor 7 is transferred from the first capacitor 7 to the chopper circuit 3.
There was a problem in that a large inrush current flows to the output side of the circuit, which may exceed the commutation withstand capacity of the chopper circuit 3.

Therefore, in this device, as shown in FIG. 1, the charging voltage VC1 of the first capacitor 7 is detected and compared with a set value. That is, the charging voltage VC1 of the first capacitor 7 is the same as that of the first transformer 11.
after being detected by the first matching circuit 12
is applied to In the first matching circuit 12, the output voltage of the first transformer and the set voltage VS1 of the first voltage setter 10 are matched, and from VC1 to VS
1 is subtracted. VS1 when power supply voltage is normal
<VC1, and since the input to the first amplifier circuit 13 is positive, the output signal becomes zero. When a power outage occurs, the charge in the first capacitor 7 is discharged and its charging voltage decreases, causing the voltage VC1 of the first capacitor 7 to decrease.
When becomes smaller than the lower limit set value VS1, the deviation of the first matching circuit 12 becomes negative, and the amplifier circuit 13 inverts and amplifies the negative input signal and then outputs a positive voltage signal.

In the second matching circuit 16, the positive voltage signal from the first amplifier circuit 13, the negative voltage signal from the second voltage setter 14, and the second capacitor 8
A positive voltage signal corresponding to the charging voltage is applied,
These deviation voltages are input to the second amplifier circuit 17. Therefore, the set value from the second voltage setter 14 is equivalently reduced by the voltage signal from the amplifier 13, and as a result, the chopper circuit 3 operates so that the voltage at the second capacitor 8 becomes smaller. In other words, the on-ratio of the chopper circuit 3 becomes smaller. The energy of the first capacitor 7 is
n via the feedback diode 21 and the diode 19a in the chopper circuit 3, but since the on-state ratio of the chopper circuit 3 becomes smaller, the amount of charge flowing into the second capacitor 8 through the thyristor 19 is reduced, so that the first The voltage drop of the capacitor 7 is suppressed. Therefore, the rush current flowing into the second capacitor 8 at the time of power restoration is suppressed.

However, even in the above-mentioned device, when the power supply 1 is normal, the thyristors 20a, 20d and the thyristors 20b, 2
The combination of 0c turns on and off repeatedly, and the load 9
However, if a momentary power outage occurs,
As shown in FIG. 5A, the input voltage of the inverter circuit disappears at time _t1 . As a result, the voltage of the commutating capacitor 40 decreases as shown in FIG. 5D. Therefore, if a power outage continues for several seconds, the charge in the commutation capacitor 40 will be discharged, the voltage will drop, and the commutation withstand capacity of the inverter will decrease.
The drawback was that the inverter could not be restarted.

However, in the present invention, in order to eliminate the above-mentioned drawback, the phase of the gate pulse of the thyristor 20d (FIG. 5B) is set to a phase lock. They are synchronized by a loop (not shown), and as shown in FIG. 5C, a gate signal is supplied to the thyristor 43 at time _t3 as a condition for power restoration, and the thyristor 43 is fired. The commutating capacitor 40 is charged to VC1+α as shown in FIG. 5D. Here, α is a voltage component due to the influence of a reactor, etc. Due to the ignition of the thyristor 43, the commutating capacitor 40 is fully charged at time _t3 , as shown in FIG. 5D. After time _t4 , the inverter operates normally and commutates according to the output frequency of the inverter.

In the inverter circuit shown in FIG. 4, when the auxiliary thyristor 43 is turned on, current flows from the first capacitor 7 through the auxiliary thyristor 43, the reactor 44, the commutating capacitor 40, the thyristor 20d, and the reactor 42b, and the commutating capacitor 4
0 as shown in FIG. 5D. Therefore, commutation failure in the inverter is prevented, and even if a momentary power outage lasting several seconds occurs, the device can be restarted when power is restored.

Furthermore, in the present invention, when a momentary power outage occurs in the power supply 1, the inverter circuit 4 temporarily stops operating.
At the same time, the switch 6 is turned on to detect the magnitude, phase, and frequency of the reverse power of the motors 9a to 9n, and when the power is restored, the voltage and phase of the inverter circuit are turned on in synchronization with the back electromotive force of the motor and its phase. This will enable smooth resumption of operation.
That is, the phase component of the induced voltage of the electric motors 9a to 9n is detected by the phase detection transformer 22, and the detection signal is inputted to the zero voltage detection circuit 26 through the filter circuit 23. The output pulse from this is matched with a pulse frequency-divided six times by a frequency divider circuit (not shown) from the voltage-frequency conversion circuit 32,
The phase lock circuit 28 outputs a pulse whose pulse width is the phase difference between these pulses. Next, a DC voltage obtained by smoothing the pulse is output from the low-pass filter 29 via the amplifier circuit 31, and is converted by the voltage-frequency conversion circuit 32 into a pulse having a frequency corresponding to the DC voltage. Therefore, unless the phase correction circuit 36 described below is taken into account, the phase of the output pulse of the voltage-frequency conversion circuit 32 and the zero voltage detection circuit 2
It is locked in a state where the phase of the output pulse of No. 6 matches.

By the way, the filter circuit 23 is necessary to remove harmonics of the detected voltage, and due to the existence of this filter circuit 23, the voltage from the zero voltage detection circuit 26 is The phase of the output pulse is delayed by θ = tan ^-1 2πfT. However, f is the frequency of the induced voltage, and T is
R ₁ C ₁ /2, where R ₁ is the resistance value of the resistors 24a and 24b of the filter circuit 23, and C ₁ is the resistance value of the capacitor 25.
is the capacitance of Therefore, the output pulse of the voltage-frequency conversion circuit 32 will be out of phase with the induced voltage. Therefore, a phase correction circuit 36 is used which has characteristics as shown in FIG. 3 and outputs a voltage corresponding to the phase difference θ when a voltage corresponding to the frequency is input from the amplifier 31.
In the phase lock circuit 28, the relationship between the phase difference obtained by the matching circuit 27 and the width of the pulse output from the phase lock circuit 28 is adjusted by the output voltage value of the phase correction circuit 36. As a result of this adjustment,
A pulse with a pulse width corresponding to the phase difference obtained by correcting the phase difference obtained by the matching circuit 27 by θ is output from the phase lock circuit 28, and the output pulse of the voltage-frequency conversion circuit 32 is eventually the output pulse of the zero voltage detection circuit 26. It is locked with the phase leading by θ.

Figure 2 shows this situation, and Figure A
is the zero point pulse of the induced voltage when there is no phase shift,
B is the output pulse of the zero voltage detection circuit 26, C is the output pulse of the voltage-frequency conversion circuit 32, D is the output pulse of the phase lock circuit 28, and E is the phase correction circuit 3.
This is the output signal of No. 6.

FIG. 3 shows the characteristics of the phase correction circuit 36. The curve l ₀ is an ideal curve given by the phase angle θ = tan ^-1 2πfT, but in the frequency range up to about 300 Hz, it becomes a straight line l ₁ , As shown in l ₂ , two-linear approximation correction is sufficient.

In this way, the inverter circuit 4 includes the logic circuit 3.
A gate signal is supplied through the inverter circuit 4 and the gate circuit 35, and the frequency 6, which is six times the frequency of the induced voltage of the load 9, and the frequency supplied to the inverter circuit 4 match during a power outage.

As a result, the phase of the induced voltage of the motors 9a to 9n matches the phase of the gate signal supplied to the inverter circuit 4 during a power outage, and when the power is restored and the inverter is restarted, it is possible to prevent the injection of current, and when the power is restored, the inverter is restarted. This enables smooth restart of the device at any time.

As described above, the present invention has the following effects.

When the voltage of the first capacitor on the input side of the chopper circuit drops below the lower limit set value during a power outage, the set value of the voltage of the second capacitor on the output side of the chopper circuit is equalized by the amount corresponding to the drop. This is because the on-state ratio of the chopper circuit is reduced, thereby restricting the amount of charge flowing from the first capacitor to the second capacitor, and suppressing the drop in the voltage of the first capacitor. , the inrush current is suppressed by the first capacitor when the power is restored.

Since the electric charge of the first capacitor is applied to the commutation capacitor of the inverter circuit through the auxiliary thyristor at the time of power restoration, the commutation withstand capacity of the inverter circuit can be ensured and commutation failure can be prevented.

A filter circuit for removing harmonics is used when detecting the induced voltage of a motor, and this causes a phase lag in the detected value of the induced voltage, but this phase lag is corrected by a phase correction circuit, so it is accurate. Synchronous input can be performed.

The above makes it possible to restart operations smoothly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a drive control device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the state of phase correction, FIG. 3 is a characteristic diagram showing the input/output pattern of the phase correction circuit, and FIG. The figure is a specific electrical wiring diagram of the inverter circuit, and FIG. 5 is a characteristic diagram of the inverter circuit. DESCRIPTION OF SYMBOLS 1...AC power supply, 2...A rectifier circuit which is a forward converter, 3...A chopper circuit, 4...An inverter circuit which is an inverse converter, 7...A first capacitor, 8...
...Second capacitor, 9...Load, 9a to 9n...
...Permanent magnet electric motor, 10...First voltage setting device, 11...First transformer, 12...First matching circuit, 13...First amplifier circuit, 14...
Second voltage setter, 15...Second transformer, 1
6... Second matching circuit, 17... Second amplifier which is an automatic voltage adjustment amplifier, 18... Phase control circuit, 22... Phase detection transformer, 23... Filter circuit, 26... Zero voltage detection circuit, 28... phase lock circuit, 31... third amplifier, 32...
Voltage/frequency conversion circuit, 35...gate circuit, 3
6...Phase correction circuit.

Claims (1)

[Scope of Claims] 1. A forward conversion circuit, a first smoothing capacitor, a chopper circuit, a second smoothing capacitor, and an inverter circuit are connected to an AC power source in this order, and the AC output from the inverter circuit is synchronized. In a control device that supplies a voltage to an electric motor to drive it and normally controls a chopper circuit based on a deviation between a predetermined set voltage and a detection voltage of a charging voltage of a second capacitor, the first capacitor is connected to a first capacitor; a lower limit voltage setter for setting a lower limit voltage of the charging voltage of the first capacitor; an amplifier that outputs the deviation when the detected voltage of the charging voltage of the first capacitor becomes lower than the lower limit voltage; A matching circuit that subtracts the set voltage by the deviation output from the amplifier, an induced voltage detection circuit that detects the induced voltage of the motor induced during a power outage of the AC power supply, and removes harmonics of the detected voltage of this circuit. , a zero voltage detection circuit that detects the zero point of the output signal from this filter circuit, and an output pulse of a voltage-frequency conversion circuit connected to the subsequent stage and a pulse from the zero voltage detection circuit. , a phase lock circuit that outputs a pulse signal with a pulse width corresponding to the phase difference between the pulses, a low-pass filter that obtains the average value voltage of the output pulses of this phase lock circuit and applies it to the voltage-frequency conversion circuit, and an input/output circuit. The relationship corresponds to the relationship between the frequency and the phase delay in the filter circuit, and the output voltage from the low-pass filter is inputted to give a signal corresponding to the corresponding phase delay to the phase lock circuit. a phase correction circuit that corrects the phase difference of the pulse by the phase delay; a gate circuit that outputs a gate signal for the inverter circuit based on the output pulse from the voltage-frequency conversion circuit; and the first capacitor. A synchronous motor, characterized in that it is provided with a switching element connected between a commutating capacitor of an inverter circuit, turned on at the initial stage of power restoration, and supplying the electric charge of the first capacitor to the commutating capacitor through this switching element. drive control device.