JP3290066B2 - Portable power supply with parallel synchronous operation function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable power supply device such as a portable engine generator, and more particularly, to a portable power supply device which is operated in parallel when a plurality of units are connected in parallel. The present invention relates to a portable power supply device having a function of preventing a cross current from occurring.

[0002]

2. Description of the Related Art When a plurality of portable power supplies, for example, a plurality of portable generators are connected in parallel and operated, if the output voltages of the respective portable generators are not synchronized,
The current difference flows from one portable generator to the other portable generator due to the voltage difference, and an overcurrent may flow to one portable generator, destroying the components. It is necessary to synchronize between output voltages.

For this reason, even when portable generators of the same standard are operated in parallel, signal wiring for confirming each other's operation state is required.
As disclosed in JP-A-202072, it is necessary to devise a method of making a phase coincidence point so that the automatic synchronizer works quickly and surely.
As shown in Japanese Patent Publication No. 0, a special parallel operation adapter is used to operate one of the two units as a master unit and the other unit as a slave unit for parallel operation.

On the other hand, the applicant of the present application has disclosed in Japanese Patent Laid-Open No.
No. 8328 proposes a portable power supply device that does not require a special adapter or the like and does not require special operation.

[0005]

When a plurality of such portable power supply units are operated in parallel, the output voltage is high due to the no-load output voltage of each power supply unit. A cross current occurs from the lower power supply to the lower power supply.

At this time, if the power supply having the lower output voltage is an inverter-type power supply, the reverse current flowing back to the output side (G) of the inverter circuit (eg, the inverter circuit 3a shown in FIG. 6). Causes an inductive action on the choke coils (coils L1 and L2) when the inverter transistors (FETs Q5 to Q8) are switched off, whereby a high voltage is generated in the choke coils. This voltage is the flywheel diodes D3 to D3.
6, is applied to the input side (X-Y) of the inverter circuit 3a to push up the voltage of the capacitor (the capacitor C11 in FIG. 5). May trigger.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and when a plurality of power supply units are connected in parallel to perform a no-load operation, a cross current is generated even when the output voltage difference between the respective power supply units is large. It is an object of the present invention to provide a power supply device capable of suppressing and reliably performing parallel operation.

[0008]

In order to achieve the above object, the present invention provides a bridge type inverter circuit which supplies a DC output obtained by rectifying and smoothing an AC output output from a generator to a bridge type inverter circuit. The switching control of the inverter circuit according to the drive signal is performed so that an AC output of a predetermined frequency is taken out through an output terminal. Each of the transistors forming each arm of the bridge type inverter circuit has a flywheel diode. There are connected in parallel, in a portable power supply choke coil is provided between the output terminal and the bridge type inverter circuit, when connected to an output terminal of the other power supply to the output terminal, its own power supply AC output voltage of device
And an internal voltage detection circuit for detecting that the DC voltage on the input side of the bridge-type inverter circuit has risen due to a cross current caused by a difference between the output voltage of the power supply device and an AC output voltage of another power supply device. Output voltage adjusting means for increasing the output voltage output from the output terminal of the portable power supply device.

Preferably, the output voltage adjusting means adjusts the output voltage by controlling the amplitude of a reference sine wave signal serving as a reference for a drive signal of the bridge type inverter circuit, and detects the internal voltage. The circuit detects an increase in the DC voltage on the input side of the bridge-type inverter circuit, and when the detected value exceeds a predetermined value, increases the amplitude of the reference sine wave signal in accordance with the excess amount, and It is characterized in that the voltage is increased.

[0010] Further, preferably, a protection circuit for interrupting an output current in an overload state is provided, and the output voltage adjusting means is adapted to respond to the excess amount when the output current exceeds a predetermined value. The amplitude of the reference sine wave signal is reduced, and the output voltage is reduced.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a portable power supply according to an embodiment of the present invention. In the figure, the output side of the alternator 1 is connected to the input side of the rectifying / smoothing circuit 2, and the output side of the rectifying / smoothing circuit 2 is generated when there is no load operation in parallel connection with another power supply device. The input side of a cross current detection circuit 31 for detecting a certain cross current is connected to the input side of an inverter and a low pass filter (hereinafter referred to as “LPF”) 3, and the output side of the inverter and the LPF 3 is connected to a voltage detector 4. And a current detector 5 connected to output terminals T1 and T1. The output of the cross current detection circuit 31 is connected to the voltage balance circuit 18.
Is connected to the input side.

An output side of a voltage controlled oscillator (hereinafter referred to as “VCO”) 6 for outputting an oscillation signal for producing an output target waveform signal is connected to an input side of a frequency divider 7. The output side is connected to the input side of a sine wave forming circuit 8 for generating an output target waveform signal, and the output side of the sine wave forming circuit 8 is LP
Pulse width modulator (hereinafter referred to as "PWM") through F9
10 inputs.

Further, the output side of the voltage detector 4 is connected to the non-inverting input terminal (+) of the operational amplifier 11, and the output side of the operational amplifier 11 is connected to the input side of the rectangular wave converter 13 via the resistor 12, The output side of the square wave converter 13 is connected to the input side of the inverter 14 and the input side of the phase difference detector 15. The output side of the current detector 5 is a rectangular wave converter 1
6, are connected to the input side of the comparison circuit 17 and the voltage balance circuit 18. The output side of the rectangular wave converter 16 is connected to the input side of the phase difference detector 15, and the output side of the phase difference detector 15 is connected to the input side of the VCO 6. The input side of the phase difference detector 15 is also connected to the output side of the sine wave conversion circuit 8, and the input side of the sine wave conversion circuit 8 has a voltage balance circuit 18 connected thereto.
Is also connected. The output side of the comparison circuit 17
It is connected to the input side of the protection circuit 19.

Further, the input side of the NAND circuit 20 is connected to the inverter 14 and the output side of the operation / stop controller 21, and the output side of the operation / stop controller 21 is connected to the D flip-flop 2.
2 and the input side of the inverter 23 and the PWM
10 inputs are also connected. The input side of the operation / stop controller 21 is connected to the output side of the protection circuit 19. A control terminal of the operation / stop controller 21 is connected to a control input terminal of the PWM 10. C of D flip-flop 22
The K (clock) terminal is the output side of the NAND circuit 20, the R (reset) terminal is the output side of the inverter 23, the Q
The bar (inverted output) terminal is connected to the sine wave conversion circuit 8 and the PWM 1
0 (reset) terminal. The output side of the inverter 23 is connected to the R terminal of the counter 24. As the counter 24, for example, μPD4024
(Nidec) may be used. The CK terminal of the counter 24 is the output side of the frequency divider 7 and the Q6 (output) terminal is the inverter 2
5 is connected to the input side. The output side of the inverter 25 is connected to the input side of the rectangular wave converter 13 via the resistor 26.

The parallel operation of the portable power supply having such a connection and configuration is performed by connecting the output terminals T1 and T1 of its own device to the output terminals T1 and T1 of another device.

Next, the operation of the portable power supply device shown in FIG. 1 will be described.

The AC output from the AC generator 1 is rectified and smoothed by the rectifying and smoothing circuit 2 to become DC power. This DC power is supplied to an inverter controlled by the PWM 10 and an LPF.
3 and is output to the load from the output terminals T1 and T1. The output voltage appearing on the output line is detected by the voltage detector 4 and the output voltage signal a output from the voltage detector 4 is sinusoidal as shown in FIG. The rectangular wave signal b as shown in FIG.
Is output to the inverter 14 and the phase difference detector 15. The signal b 'output from the square wave converter 16 by inputting the output current signal from the current detector 5 is a similar signal, and is input to the phase difference detector 15. Phase difference detector 15
Represents a phase difference voltage corresponding to the phase difference between the signals b and b 'in the VCO6.
To control the oscillation frequency of the VCO 6.

The oscillation signal whose frequency is controlled and output from the VCO 6 is frequency-divided by the frequency divider 7 and input to the sine wave circuit 8 as a clock signal. The sine wave generating circuit 8 generates a step-like sine wave signal by the clock signal, the sine wave signal is input to the PWM 10 via the LPF 9, and the pulse width modulated by the sine wave signal is PWM.
It is output from 10. The LPF 9 is a filter for removing a step portion of the step-like sine wave signal to obtain a smooth sine wave signal. The energization time of each gate constituting the inverter and the inverter of the LPF 3 is controlled by the pulse output from the PWM 10, and is output from the inverter as a pulse train having a pulse width corresponding to the sine wave signal from the LPF 9, and the output of the inverter is The power is converted into a sine wave AC power by the inverter and the LPF of the LPF 3, and is output from the output terminals T1 and T1.

When the operation / stop controller 21 is set to the operation state, the output signal c of the operation / stop controller 21 changes from "L" level (stop state) to "H" level as shown in FIG. Becomes

The D flip-flop 22 has a D terminal connected to the output signal c, a CK terminal connected to the inverted signal of the rectangular wave signal b and a NAND signal d (see FIG. 2D) of the output signal c, and an R terminal connected to the D terminal. 2 has an inverted signal f of the output signal c (FIG. 2).
(See (f)). The Q bar terminal of the D flip-flop 22 outputs a signal Q bar corresponding to the signals c, d, and f (see FIG. 2E). Signal Q bar and signal c,
The relationship between d and f is shown in the table. In the table, ↑ indicates the rising portion of the pulse signal d, ↓ indicates the falling portion, s indicates the signal on the S terminal of the D flip-flop 22, and the signal s is always at the “L” level. In addition, * indicates that either “L” or “H” may be used (don't care).

[0022]

[Table 1] At the start of operation, the own power supply device is connected in parallel with the other power supply device, an AC output voltage is supplied from the other power supply device to the output line of the own power supply device, and when the operation / stop controller 21 enters the operation mode, a signal c is output. The signal Q bar goes to the “L” level at the first rising edge of the signal d, as shown in the second row of the table (see FIGS. 2D and 2E), and the sine wave forming circuit 8
Is released, and the output target waveform signal is output from the sine wave conversion circuit 8 to the LPF 9. Thereby, LP
The signal of the output target waveform is output from F9, and the own power supply device can supply the load with an AC output having a phase substantially matching the phase of the output waveform of the other power supply device. However, when the other power supply is stopped or disconnected and the AC output voltage is not supplied, the pulse signal is not supplied to the CK terminal of the D flip-flop 22 and the Q bar terminal is not supplied. The initial state of the "H" level is maintained, and the sine wave conversion circuit 8 remains in the reset state.
Does not output the output target waveform signal, and the own power supply device cannot supply the AC output to the load.

The counter 24 is provided to solve the above-mentioned problem, and enables the portable power supply device to start up independently. That is, when the signal c is set to “H” and the signal f is set to “L” while the operation / stop controller 21 is in the operating state, the reset state of the counter 24 is released, and after a predetermined time elapses according to the clock from the frequency divider 7. , The level of the output terminal Q6 changes from “L” to “H” from “L”, and the output signal level of the inverter 25 changes from “H” to “H”. As a result, as can be seen from the table, the output signal Q bar of the D flip-flop 22 becomes the “L” level, and the reset state of the sine wave forming circuit 8 is released. AC power having a waveform based on the output target waveform signal to be output can be output.

With respect to the output characteristics when the portable power supply device started to operate as described above is operated alone,
Description will be given based on the output current-voltage characteristic diagram of the power supply device shown in FIG.

As the output current increases, the output voltage gradually decreases as indicated by the output characteristics according to the output current-voltage characteristics of the power supply itself. When the output voltage value of the current detector 5 reaches the output current A1 indicated by a point, the voltage balance circuit 18 starts operating to decrease the amplitude of the reference sine wave signal of the sine wave conversion circuit 8. That is, as shown in the output characteristics, the output voltage decreases as the output current increases, and decreases to the position where the maximum decrease width is reached (in this embodiment, the maximum value of the voltage decrease width Vd is 4 V). here,
The slope of the characteristic curve shown by the output characteristics can be changed by setting, and during parallel operation, adjust the output current of the other power supply while balancing the output voltage of the other power supply between the output characteristics I do.

The output current continues to increase despite the decrease in the output voltage, and enters the state of the output characteristic shown in FIG.
When this state has elapsed for a predetermined time or more,
When an output signal indicating an overcurrent state is continuously input to the protection circuit 19 for a predetermined time or more, a signal is output from the protection circuit 19
Input to the stop controller 21,
An operation stop signal is input to WM10, and the inverter and L
The operation of the inverter of PF3 is stopped.

Next, when the portable power supply device of the present embodiment is connected in parallel with another power supply device, the operation performed by the portable power supply device of the present embodiment will be briefly described under no-load operation and overload operation. The operation will be described separately.

First, when no load operation is performed, the output voltage of the portable power supply (own power supply) of the present embodiment is lower than the output voltage of the other power supply, and a cross current occurs (“S” in the figure).
20 "), the output voltage from the rectifying / smoothing circuit 2 also increases because the internal voltage of the power supply device itself increases as described above. Is output to the voltage balance circuit 18, and the voltage balance circuit 18
Outputs to the sine wave conversion circuit 8 a signal such that the amplitude of the sine wave signal output from the sine wave conversion circuit 8 increases. As a result, the output voltage of the own power supply rises to the output voltage of the other power supply, and the occurrence of cross current is suppressed.

Next, the overload operation is performed, and as shown in FIG. 4, the output current value of the portable power supply device of this embodiment (indicated by "S10" in the figure) is changed to the current value A1 previously indicated by a point. When it reaches, the output voltage starts to decrease according to the output characteristics. Due to this, the output current shared on the other power supply side starts to increase, that is, the output current on the other power supply side, which has only borne an output current smaller than the output current value of the own power supply, starts to increase, When the amount of voltage drop reaches the point in FIG. 4, the sum of the maximum output currents of the two is obtained as the output current. Thus, the above-described protection circuit 20
The maximum combined calculation force is obtained in the current amount range where does not operate.

Next, each component of FIG. 1 will be described in detail with reference to FIGS.

Each of FIGS. 5 to 17 is a configuration diagram showing each component of FIG. 1 and its associated circuit. 5 and 6,
1a is a three-phase output winding wound independently on the stator of the AC generator 1, and 1b is a single-phase auxiliary winding. The rotor (not shown) of the alternator 1 is formed with magnetic poles of multi-pole permanent magnets, and is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1a is connected to a bridge rectifier circuit 2a composed of three thyristors and three diodes, and the output terminal of the bridge rectifier circuit 2a is connected to a smoothing circuit 2b. The bridge rectifying circuit 2a and the smoothing circuit 2b constitute a rectifying and smoothing circuit 2.

The output terminal of the single-phase auxiliary winding 1b is connected to a constant voltage supply device A1 having positive and negative output terminals E and F. The constant voltage supply device A1 includes two sets of rectifier circuits, a smoothing circuit,
The constant voltage circuit A1a has one circuit in one set for the current in one direction from the single-phase auxiliary winding 1b, and the other set for the current in the direction opposite to the one direction. Each circuit operates, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

A2 is a thyristor control circuit. One end on the power input side is connected to the positive output terminal E of the constant voltage supply A1, and the other end is grounded together with the positive terminal of the smoothing circuit 2b. The signal input terminal of the thyristor control circuit A2 is composed of a series circuit of a capacitor C1 and resistors R1 to R3, one end of the capacitor C1 is connected to the positive output terminal E of the constant voltage supply device A1, and the other end of the thyristor control circuit A2 is connected to the other end. Connected to the negative terminal of the smoothing circuit 2b. The connection point between the resistors R1 and R2 is connected to the base of the transistor Q1.
Is connected to the base of the transistor Q2, and the collector of the transistor Q2 is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 2a.
It is configured to control the input signal of the gate input circuit in accordance with the potential of the connection point with the second.

The output of the operation / stop controller 21 is connected to a connection point K between the capacitor C1 and the resistor R1. According to the operation / stop controller 21, the positive output terminal E of the constant voltage supply device A1 is used.
The cathode side of the Zener diode D1 is connected to the input side (G) of the constant voltage circuit A1a provided on the side, and the anode side of the Zener diode D1 is connected to the negative output terminal F of the constant voltage supply device A1 via a resistor. , An inverting input terminal (−) of an inverting comparator 211 composed of an operational amplifier
And the non-inverting input terminal (+) of the inverting comparator 211
Is grounded via a resistor. The output side of the inverting comparator 211 is connected to one terminal on the input side of the NOR circuit 212,
On the other hand, the other terminal on the input side of the NOR circuit 212 is connected to a protection circuit 19 including a counter (not shown) for detecting an overcurrent state of the power supply device and counting the duration of the overcurrent state. Outputs an "H" level signal when counting a predetermined number of pulses (elapsed time).
12 is supplied. The output side of the NOR circuit 212 is connected to the input side of the inverter 213 and the base of the transistor Q3 via a resistor. The emitter of the transistor Q3 is connected to the negative output terminal F of the constant voltage supply A1, while the collector is connected to the positive output terminal E of the constant voltage supply A1 via the resistor R4 and to the constant voltage via the capacitor C2. It is connected to the negative output terminal F of the supply device A1.
The positive terminal of the capacitor C2 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to the positive output terminal E of the constant voltage supply A1, while the emitter is connected to the anode of the diode D2 and the thyristor control circuit. A2 is connected to a connection point K between the capacitor C1 and the resistor R1. The cathode of the diode D2 is connected to the positive terminal of the capacitor C2. NOR circuit 21
2 are the D terminal of the NAND circuit 20 and the D flip-flop 22 of FIG.
It is also connected to the control terminal of WM10.

The output side of the smoothing circuit 2b is connected to the inverter and the inverter circuit 3a (switching device) of the LPF 3 shown in FIG. The inverter circuit 3a is composed of a bridge circuit composed of four FETs (field effect transistors) Q5 to Q8. Flywheel diodes D3 to D6 are connected in parallel to the FETs Q5 to Q8 forming the respective arms of the bridge circuit. . FET Q5
The drive signal circuits connected to the gate terminals Q8 to Q8 will be described later.

The output side of the inverter circuit 3a is connected to output terminals T1 and T1 to which a load (not shown) is connected via the inverter and the LPF 3b of the LPF 3. L
PF3b includes coils L1, L connected in series to the load.
2 and a capacitor C3 connected in parallel to the load.

The drains of the FETs Q5 and Q6 and the smoothing circuit 2
b between the current detection resistors R7 and R8
Are connected respectively. Current detection resistors R7, R8
7 are connected to a current detector 5, which is shown in detail in FIG. The current detector 5
An operational amplifier 51 that inverts an input signal from point N, adds the input signal from point M, amplifies the signal, and forms a sine wave signal; operational amplifiers 52, 53 that perform full-wave rectification on the output signal of the operational amplifier 51; D10, D11 and a resistor R for smoothing the output signals of the diodes D10, D11.
9, a capacitor C7, and an operational amplifier 54 for amplifying the output signal smoothed by the resistor R9 and the capacitor C7.

The output side of the current detector 5 is a rectangular wave converter 16
And the input side of the voltage balance circuit 18 and the input side of the comparison circuit 17.

The comparison circuit 17 includes a comparator 171 and two series-connected resistors R10 and R11 each having one end connected to the positive output terminal E of the constant voltage supply device A1 and the other end grounded.
And a series circuit. The connection point between the resistors R10 and R11 is connected to the inverting input terminal (-) of the comparator 171 to form a threshold value Vi. The output side of the current detector 5 is a comparator 171
Are connected to the non-inverting input terminal (+).

Inverter circuit 3 input from M and N points
The currents flowing through the FETs Q5 and Q6 a are inverted by the operational amplifier 51 and superimposed to form a sinusoidal voltage signal. In the sinusoidal voltage signal output from the operational amplifier 51, the positive half wave is rectified by the operational amplifier 52 and the diode D10, the negative half wave is rectified by the operational amplifier 53 and the diode D11, and smoothed by the resistor R9 and the capacitor C7. DC voltage. This DC voltage is DC-amplified by the operational amplifier 54 and input to the comparison circuit 17.

The output of the comparator 171 becomes "H" level only when the output voltage of the current detector 5 is larger than the threshold value Vi.

The output side of the comparison circuit 17 is connected to the input side of the protection circuit 19.

Two output lines l of the inverter circuit 3a
Is connected to an input terminal G of the voltage detector 4 shown in FIG. 8, and one end of a series circuit of the resistors R12 and R13 and one end of a series circuit of the resistors R14 and R15 are connected to the input terminal G. On the other hand, the other ends of these series resistance circuits are connected to the positive output terminal E of the constant voltage supply device A1. Resistance R12, R
13 and the connection point of the resistors R14 and R15 are respectively
A non-inverting input terminal (+) and an inverting input terminal (-) of the operational amplifier 41 are connected via the resistors R16 and R17, and a high frequency component cutting capacitor C8 is connected between the two connection points. . The non-inverting input terminal (+) of the operational amplifier 41 is a capacitor C9 for cutting high frequency components.
Grounded. The output side of the operational amplifier 41 is connected to the non-inverting input terminal (+) of the distortion correction circuit A6 and the non-inverting input terminal (+) of the operational amplifier 11 via a resistor.

One output line l of the inverter circuit 3a
And the output voltage appearing on the other output line 1 (the waveforms of these output voltages are PWM signal waveforms)
Are voltage dividing resistors R12, R13 and R14, R, respectively.
15, a signal obtained by removing the carrier frequency of the PWM signal by the capacitor C8, that is, the AC output voltage of the output terminals T1 and T1, is connected to the connection point between the capacitor C8 and the resistor R16 and the connection point between the capacitor C8 and the resistor R17. The two AC signals are compared by an operational amplifier 41, and the difference between the two AC signals, that is, an AC signal including a waveform distortion or an offset component of the output voltage (corresponding to the waveform distortion or the offset component). (An AC signal having an average level obtained by the correction)
6 is output.

In FIG. 8, 9 is an LPF and 10 is a PWM.
It is. The output side of the sine wave conversion circuit 8 is connected to the inverting input terminal (-) of the operational amplifier of the LPF 9. This LPF9
Is for converting the step-like sine wave output from the sine wave conversion circuit 8 into a smooth sine wave. The output side of the LPF 9 is connected to the inverting input terminal (-) of the operational amplifier of the distortion correction circuit A6, and the output side of the voltage detector 4 is connected to the non-inverting input terminal (+) of the operational amplifier. The distortion correction circuit A6 corrects a sine wave level output from the sine wave conversion circuit 8 via the LPF 9 with a detection signal output from the voltage detector 4, and outputs a corrected sine wave signal.

In FIG. 8, reference numeral 101 denotes a rectangular wave oscillator, and the frequency of the rectangular wave oscillated by the rectangular wave oscillator 101 is set to a value much higher than the frequency of the sine wave output from the LPF 9. The output side of the rectangular wave oscillator 101 is connected to an integrating circuit 102, which integrates the rectangular wave and converts it into a triangular wave signal.

The sine wave signal output from the LPF 9 and corrected by the distortion correction circuit A6 and the triangular wave signal output from the integration circuit 102 are superimposed on each other and the inverter buffer 100
(Pulse width modulation circuit). Inverter buffer 100 is an amplifier having a predetermined threshold (threshold level). When a signal having a level exceeding this threshold is input, it outputs an “L” level signal, while a signal having a level lower than the threshold is input. When this is done, an "H" level signal is output to form the aforementioned PWM signal (pulse width modulation signal). For example, the input terminal side has a fixed threshold value for the input signal to the gate terminal. C-
IC with MOS gate threshold level
It consists of.

The output side of the inverter buffer 100 is A
The other input terminal of the AND circuit 107 is connected to one input terminal of the ND circuit 107 and the D flip-flop 2
The output (signal Q bar) of the Q bar terminal of the inverter 2 is the inverter 10
6 is input.

The inverter 106 and the AND circuit 107
A gate circuit of a WM signal is formed, and a D flip-flop 2
The gate is opened when the signal Q bar from 2 becomes "L". Therefore, the PWM signal is output from the falling point of the signal Q bar, that is, from the zero-cross point of the positive gradient of the AC output voltage.

The output of the AND circuit 107 is connected to the inverter 1
The signal is input to one input terminal of the NAND circuit 104 via the input terminal 03 and is directly input to one input terminal of the NAND circuit 105 as it is. The output terminal J of the NOR circuit 222 of the operation / stop controller 22 is connected to the other input terminal of the NAND circuit 104 and the other input terminal of the NAND circuit 105.

The output side of the NAND circuit 104 is connected to a first push-pull amplifier composed of transistors Q9 and Q10. Transistor Q of first push-pull amplifier
9 is a positive electrode output terminal E of the constant voltage supply device A1.
The collector of the transistor Q10 is a constant voltage supply A
1 negative output terminal F.

The output terminal of the first push-pull amplifier (the connection point between the emitters of the transistors Q9 and Q10) is connected to the anode of the diode D12 and the diode D13.
Is connected to the connection point with the cathode. Diode D12
Is connected to the positive output terminal E of the constant voltage supply device A1.
The anode of the diode D13 is connected to the negative output terminal F of the constant voltage supply A1. Diode D12, D13
Is for absorbing a surge generated by a pulse transformer described later.

The connection point between the anode of the diode D12 and the cathode of the diode D13 is connected to one end of each of primary coils L3 and L4 of the pulse transformers A and C via a capacitor C4 for cutting low frequency components. The other ends of the primary side coils L3 and L4 are connected to the negative output terminal F of the constant voltage supply device A1. The signal immediately before passing through the capacitor C4 is a PWM signal having a constant amplitude with respect to the reference level, and the average voltage (integral value) of this signal changes in the same cycle as the sine wave from the LPF 9, so that PW
The M signal contains the same frequency component as the sine wave.

After the PWM signal has passed through the capacitor C4, the capacitor C4 is converted into a pulse signal train in which the entire pulse train goes up and down in the opposite phase to the same frequency component as the sine wave and the average voltage is always zero. Is set to such a constant value.
The pulse signal train whose average voltage is always zero is supplied to the primary coils L3 and L4 of the pulse transformers A and C.

Similarly, the output terminal of the NAND circuit 105 is connected to a second push-pull amplifier comprising transistors Q11 and Q12, and the output terminal of the second push-pull amplifier is connected to the anode of the diode D14 and the diode D1.
5 is connected to the connection point with the cathode. This connection point
Pulse transformers B and D are connected to respective one ends of primary coils L5 and L6 via a capacitor C5 having a constant value set similarly to the above-described capacitor C4.

Next, returning to FIG.
A drive signal circuit connected to each gate terminal of the FETs Q5 to Q8 of a will be described. One end of the secondary side of the pulse transformer A is connected to the P resistor before passing through the attenuation resistor R5 and the capacitor C4.
Series circuit with capacitor C6 for WM signal reproduction, resistor R
6 is connected to the gate terminal of the FET Q5 through a parallel circuit of the diode D9, while the other end on the secondary side of the pulse transformer A is connected to the source terminal of the FET Q5. A connection point between the capacitor C6 and the parallel circuit including the resistor R6 and the diode D9 is connected to the other end on the secondary side of the pulse transformer A via a series circuit of zener diodes D7 and D8. The diode D9 has an anode on the gate terminal side of the FET Q5, and has a zener diode D7,
D8 is connected so that the anodes face each other.

The secondary side of each pulse transformer B, C, D,
Between the gate terminals of the corresponding FETs Q6 to Q8,
A circuit exactly the same as the circuit provided between the secondary side of the pulse transformer A and the gate terminal of the FET Q5 is provided.

FIG. 9 is a circuit diagram showing an example of a rectangular wave converter 13 for an AC output voltage signal. This circuit is a positive feedback amplifier circuit using an operational amplifier. A sine wave signal having a phase corresponding to the phase of the AC output voltage is output from the voltage detector 4, input to the rectangular wave converter 13 via the operational amplifier 11, is positive-feedback amplified by the rectangular wave converter 13, and has a sharp rising edge. , A rectangular wave signal b having a falling characteristic.

FIG. 10 is a circuit diagram showing an example of a rectangular wave converter 16 for an AC output current signal. This circuit is a high amplification circuit using an operational amplifier. The rectangular wave converter 16 receives a sine wave signal having a phase corresponding to the phase of the load current from the current detector 5, and outputs a rectangular wave signal b 'having sharp rising and falling characteristics.

FIG. 11 is a circuit diagram showing an example of the phase difference detector 15. The operation of the phase difference detector 15 will be described with reference to FIG. A square wave signal g (FIG. 12A) output from the square wave converter 13 and indicating the voltage phase of the AC output, and a rectangular wave signal h output from the square wave converter 16 and indicating the current phase of the AC output (FIG. 12 (b)) is an input terminal 15
The signal is input to the NAND circuit 151 via T1 and 15T2, and the output is a signal i (FIG. 12C). Signal i
And the signal g are input to the NAND circuit 152, and the signal i and the signal h are input to the NAND circuit 153, and output the signal g '(FIG. 12 (d) and the signal h' (FIG. 12 (e)), respectively. The g 'and the signal h' are input to the NAND circuit 154, and the output is a signal i '(FIG. 12 (f)).
As can be seen from FIGS. 12 (a), (b) and (f),
The signal i 'is a pulse having a pulse width corresponding to the phase difference between the voltage and the current of the AC output, and the leading and trailing edges of the leading-phase rectangular wave signal g are rising pulses.

Inverters 155, 158, NAND circuits 156, 157, capacitor 15C, and resistor 15R1,1
5R2 constitutes a phase difference / voltage converter for generating a voltage corresponding to the phase difference between the voltage of the AC output and the current. The signal j (FIG. 12 (g)) is a signal obtained by inputting a pulse output from the sine wave conversion circuit 8 through the input terminal 15T3 and inverting the pulse by the inverter 155, and oscillating output from the VCO 6. This signal indicates the phase of the signal, and the frequency of the signal j is a half cycle of the output target waveform signal. That is, for a half cycle of the output target waveform signal, this half cycle is divided into the first half and the second half. Is a reference signal for determining whether the phase difference signal i is a lag phase or a lead phase. The signal j determines a gate section of the signal i '. In FIG. 11, the signal j is "H".
, Signal i 'is output from NAND circuit 156 as signal k. NAN in the section where the signal j is "L"
The signal i 'is output from the D circuit 157,
Since the signal i 'is "L" in the "L" section of the signal j, no change occurs in the output signal of the NAND circuit 157, that is, the output signal 1 of the inverter 158. That is, as shown in FIGS. 12 (h) and 12 (i), the signal k becomes “H” every time the signal i ′ becomes “L”, while the signal l maintains “L”. Here, the “H” level and the “L” level are, for example, 8 V and −8 V. When the signal k is “H” and the signal 1 is “L”, 8 V and −8 V cancel each other and the signal m (FIG. 12 (j)) becomes 0V. Next, when the signal k becomes “L”, both the signal k and l also become “L”.
It is discharged toward −8 V, and then when the signal k becomes “H”, it is charged toward 0 V as shown in FIG.
The level of the average voltage changes between V and -8V. Note that the above time chart is an example in the case where the current of the AC power is later in phase than the voltage. However, when the current is earlier in phase than the voltage, as shown in FIG.
And the level of the average voltage changes between + 8V, and the fact that the signal j has a 倍 cycle of the output target waveform is combined.
A voltage between + 4V will be generated. The voltage according to the phase difference is output from the output terminal 15T4 to the VCO 6.

FIG. 13 is a circuit diagram showing an example of the VCO 6 in which the oscillation frequency is controlled by the variable capacitance diode 61. In other words, the fact that the junction capacitance decreases when the reverse bias voltage applied to the variable capacitance diode 61 increases, for example, the frequency can be increased by increasing the reverse bias voltage, and the AC output voltage If the phase is faster than the current, the frequency can be increased, and if the phase is late, the frequency can be decreased. A voltage corresponding to the phase difference is input to the VCO 6 from the phase difference detector 15 via the input terminal 6T1, and the VCO 6 outputs an oscillation signal having a frequency corresponding to the voltage from the output terminal 6T2. When the crystal oscillator 62 is used for the VCO 6, the frequency is stable, but a change of about ± 0.01% is possible depending on the combination capacitance value.

FIG. 14 is a circuit diagram showing an example of the frequency divider 7. For example, μP74HC4040 and μP74 manufactured by Nidec Corporation
It comprises a HC4017 counter and the like. An oscillation signal is input from the VCO 6 to an input terminal 7T1 of the frequency divider 7,
A frequency-divided signal obtained by dividing this signal is output from the output terminal 7T2.

FIG. 15 is a circuit diagram showing an example of the sine wave forming circuit 8, which is composed of, for example, a multiplexer 4051 and the like. The terminal X of the multiplexer 4051 is an output terminal, and the input terminal X depends on the state of the terminals A, B, C, and IH.
It is connected to any one of 0 to X7 or disconnected. Each of the input terminals X0 to X7 is connected to a connection portion of each voltage dividing resistor. Voltages corresponding to the electrical positions are generated at the respective connection portions, and these voltages at the respective levels are sequentially input to the respective input portions in accordance with the input of the frequency-divided signal from the frequency divider 7 to the sine-wave circuit 8. By outputting from the output terminal X via the terminals X0 to X7, a step-like sine wave signal can be obtained, and this sine wave signal is output to the LPF 9 via the terminal 8T4. In FIG. 15, a terminal 8T1 is an input terminal for a frequency-divided signal from the frequency divider 7, a terminal 8T2 is an output terminal for outputting a pulse signal indicating the phase of the oscillation signal to the phase difference detector 15, and terminals 8T3 and 8T5 are The reset terminal, terminal 8T6, is an input terminal for a voltage balance signal from the voltage balance circuit 18. Since the signal Q bar is input to the terminals 8T3 and 8T5, a sine wave signal is generated from the falling edge of the signal Q bar, that is, from the zero cross point of the positive gradient of the AC output voltage, and the phase of the AC output voltage and the sine wave signal That is, the phase of the output target waveform signal matches.

FIG. 16 is a circuit diagram showing an example of the voltage balance circuit 18. The voltage balance circuit 18 includes an analog switch 181 that switches on / off an input signal (voltage) at a set threshold, a resistor, and a capacitor. The threshold value of the analog switch 181 is set to be equal to the voltage V0 at the neutral point of the device.

The input terminal of the 20 KHz rectangular wave is a resistor 18R.
1, two capacitors 18C1 and 18C2 each having one end connected to the positive output terminal E of the constant voltage supply device A1 and the other end connected to the negative output terminal F of the constant voltage supply device A1.
The output side of the operational amplifier 54 is connected to a connection point J2 of the same potential as the connection point J1 via a resistor 18R2.
The output side of the cross current detection circuit 31 is connected via a resistor 18R3 to a connection point J3 having the same potential as the above, and the control input CONT of the analog switch 181 is also connected to this connection point J3. Further, the input side of the analog switch 181 is connected to a connection point of a series circuit composed of two resistors, one end of which is grounded and the other end is connected to the negative output terminal F of the constant voltage supply device A1, and the output side is a sine. It is connected to the terminal 8T6 of the wave forming circuit 8.

Hereinafter, the operation of the voltage balance circuit 18 of this embodiment will be described with reference to FIGS. FIG.
As shown in FIG. 6, the control input signal (CONT) of the analog switch 181 and the output signal of the analog switch 181 are denoted by b and c, respectively.

FIG. 18 is a diagram showing the output characteristics of the amplitude of the output target waveform. The vertical axis and the horizontal axis represent the output voltage and output current (load current) indicating the amplitude of the output target waveform, respectively. FIG. 19 is a diagram showing a time transition of the voltage of the signals b and c at the current values I1, I2 and I3 of the load current shown in FIG. In the figure, the vertical axis and the horizontal axis indicate the voltage V and the time t, respectively, and the voltage V1 and the voltage V2 on the vertical axis indicate the voltage of the positive output terminal E and the negative output terminal F of the constant voltage supply device A1, respectively. Further, in the diagram showing the time transition of the voltage of the signal B, the voltage V0 indicates the voltage at the neutral point and corresponds to the threshold value of the analog switch 181.

The 20 KHz rectangular wave is supplied to the capacitor 18C.
1, 18C2, is converted into a triangular wave, superimposed on the output signal A from the operational amplifier 54 at the connection point J2 (having the same potential as the connection point J1) and becomes a control input signal B. Based on the control input signal B, the analog switch 181 is turned on. The signal is controlled and output to the terminal 8T6 of the sine wave conversion circuit 8 as a signal C.

That is, when the load current is the current I2 in FIG.
In the (normal output current state), the output signal from the operational amplifier 54 is maintained at a low level, and the output signal from the operational amplifier 311 of the cross current detection circuit 31 is maintained at a high level. The voltage of the signal B becomes, for example, a level as shown in FIG.
While the voltage of the control input signal B exceeds the threshold value V0, the analog switch 181 is turned on and outputs a standard level voltage having a predetermined duty ratio to the terminal 8T6 of the sine-wave circuit 8 (FIG. 19B2). ). On the other hand, when the load current is the current I1 in FIG. 18 (almost no load state) and the internal voltage increases as described above, that is, when a cross current occurs,
The output voltage of the operational amplifier 311 decreases, and the voltage level of the control input signal B becomes lower than that of FIG. 19 (b1) (FIG. 19).
(A1)). Accordingly, the time during which the voltage of the control input signal B exceeds the threshold value V0 decreases, so that the on-time of the analog switch 181 decreases as shown in FIG. Further, when the load current becomes the current I3 (overload state) shown in FIG. 18, the output voltage of the operational amplifier 54 rises from the voltage level when the load current is the current I2, and the voltage level of the control input signal B becomes the voltage shown in FIG. b1) (FIG. 19 (c1)). Accordingly, the time during which the voltage of the control input signal B exceeds the threshold value V0 increases, so that FIG. 19 (c2)
As shown in (5), the on-time of the analog switch 181 increases.

FIG. 1 shows an example using the analog switch 181 and the like.
9 (a2) to output voltage (current) as shown in FIG. 19 (c2).
Is called chopper control, and in the present embodiment, the amplitude of the sine wave signal of the sine wave conversion circuit 8 is chopper controlled, and the output voltage increases or decreases. That is, when the on-time of the analog switch 181 is shortened, the amplitude of the sine wave signal increases and the output voltage increases, while when the on-time increases, the amplitude of the sine wave signal decreases and the output voltage decreases.

The frequency of the signal for performing the chopper control is higher than the commercial frequency (50 Hz or 60 Hz), and the sine wave signal controlled by the chopper is filtered by a subsequent filter. A sine wave signal having almost no distortion is output from the power supply device.

FIG. 17 is a circuit diagram showing an example of the cross current detection circuit 31, in which the operational amplifier 311 and the resistors 31R1 to 31R are connected.
R4.

The non-inverting input terminal (+) of the operational amplifier 311
Is connected to a connection point S of the smoothing circuit 2b, and to the positive output terminal E of the constant voltage supply device A1 via a resistor 31R1. That is, the potential difference between the negative output line of the smoothing circuit 2b and the positive output terminal E of the constant voltage supply device A1 is applied to the non-inverting input terminal (+) of the operational amplifier 311 by the resistors R2 and R3 and the resistor 31R1. It is divided and input.

The inverting input terminal (-) of the operational amplifier 311 is connected to the connection point between the resistors 31R2 and 31R3.
The other end of the resistor 31R2 is connected to the positive output terminal E of the constant voltage supply A1, and the other end of the resistor 31R3 is grounded. Further, the output side of the operational amplifier 311 is connected to the inverting input terminal (-) of the operational amplifier 311 via the resistor 31R4.

The output side of the operational amplifier 311, that is, the output side of the cross current detection circuit 31 is connected to the terminal 18 T 2 of the voltage balance circuit 18 as described above.

The operation performed when the portable power supply device configured as described above is connected in parallel with another power supply device will be described below.

First, when the two portable power supply devices S10 and S20 according to the present embodiment are connected in parallel and operated without load, the own power supply device is set to S20, that is, the output voltage is If the cross-current is lower than the output power of the device and a cross current occurs, the internal voltage of the own power supply increases as described above, and the potential of the non-inverting input terminal (+) of the operational amplifier 311 decreases. Since the difference between the lowered potential and the potential of the inverting input terminal (−) of the operational amplifier 311 is amplified by the operational amplifier 311, the voltage balance circuit 18
, A voltage lower than that before the other power supply devices are connected in parallel is input. As a result, as described with reference to FIGS. 18 and 19, the output voltage of the self-powered device is
And the cross current can be suppressed.

Next, the operation of the two portable power supplies S10 and S20 according to the present embodiment when they are operated in parallel in an overload region will be described with reference to FIG. The two power supplies S10 and S20 have unavoidable variations in their respective rated output voltages due to slight differences in the accuracy of circuit components, temperature characteristics, and the like.
This always occurs for each power supply device), and the one having a high output voltage characteristic is referred to as the own power supply device S10. As described above, the output current of the own power supply device S10 is A1 (approximately 15A).
The output current of the other power supply device S20 at the time when
1A, which still has a margin of 4A.

When the self-power supply device S10 reaches A1, the output voltage from the operational amplifier 54 starts to rise as described above, so that the output voltage decreases according to the output characteristics of FIG. [V] Lowers and reaches a point.

In the present embodiment shown in FIG. 4, when the output voltage of the own power supply device S10 decreases by 2 V (point in the figure), the output of the other power supply device S20 also becomes approximately 15 A, and the maximum output by the parallel operation is obtained. Current 15 [A] +15
[A] = 30 [A] can be obtained. Therefore,
If the load current is between 26A and 30A, the output voltage is balanced between points in FIG. 4 and does not reach the point.

As described above, when one of the power supplies reaches the maximum current, the total output of both the maximum currents can be taken out without limiting the total output of the parallel operation.

Further, when the output voltage of the own power supply device S10 decreases from the state of the point and reaches the point, that is,
The output of the operational amplifier 171 of the comparison circuit 17 in FIG.
When the counter reaches the predetermined level, the counter of the protection circuit 19 in FIG. 5 starts counting operation.
Becomes "H" level, the operation of the inverter circuit 3a stops, and the portable power supply device is shut off.

In the present embodiment, the self-power supply S
The case where the output voltage of the power supply 10 is higher than that of the other power supply device S20 has been described. Conversely, when the output voltage of the other power supply device S20 is higher, the operation of the own power supply device S10 of this embodiment is The operation is performed similarly.

[0085]

As described above, according to the present invention,
A DC output obtained by rectifying and smoothing the AC output output from the generator is supplied to a bridge-type inverter circuit, and switching control of the bridge-type inverter circuit is performed according to a drive signal, so that a predetermined value is output through an output terminal. And a flywheel diode connected in parallel to each of the transistors forming each arm of the bridge-type inverter circuit, and a choke coil between the bridge-type inverter circuit and the output terminal. In the portable power supply device provided with, when the output terminal of another power supply device is connected to the output terminal, the AC output voltage of its own power supply device and the other power supply device
An internal voltage detection circuit that detects an increase in the DC voltage on the input side of the bridge-type inverter circuit due to a cross current generated by a difference between the output voltage and the AC output voltage of the bridge-type inverter circuit; and the portable power supply according to the voltage increase detection signal. Output voltage adjusting means for increasing the output voltage output from the output terminal of the device, so that when a plurality of power supply devices are connected in parallel and operating under no load, the difference between the output voltages of each power supply device Even if it is large, there is an effect that the cross flow is suppressed and the parallel operation can be surely performed.

Preferably, the output voltage adjusting means adjusts the output voltage by controlling an amplitude of a reference sine wave signal which is a reference of a drive signal of the bridge type inverter circuit, and detects the internal voltage. The circuit detects an increase in the DC voltage on the input side of the bridge-type inverter circuit, and when the detected value exceeds a predetermined value, increases the amplitude of the reference sine wave signal in accordance with the excess amount, and Since the voltage is increased, the output voltage can be easily adjusted.

Further, preferably, a protection circuit is provided for interrupting the output current in an overload state, and the output voltage adjusting means, when the output current exceeds a predetermined value, responds to the excess amount. Since the amplitude of the reference sine wave signal is reduced and the output voltage is reduced, stable operation can be performed over the entire range from the time of no-load operation to the time of overload operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a portable power supply device according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is an output current-voltage characteristic diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 4 is an output current-voltage characteristic diagram when the embodiment of FIG. 1 is operated in parallel with another power supply device.

FIG. 5 is a circuit diagram showing a part of the configuration of the embodiment of FIG. 1 in detail.

FIG. 6 is a circuit diagram showing a part of the configuration of the embodiment of FIG. 1 in detail.

FIG. 7 is a circuit diagram illustrating an example of a current detector and a comparison circuit.

FIG. 8 is a circuit diagram showing in detail a part of the configuration of the embodiment of FIG. 1;

FIG. 9 is a circuit diagram illustrating an example of a rectangular wave converter.

FIG. 10 is a circuit diagram illustrating an example of a rectangular wave converter.

FIG. 11 is a circuit diagram illustrating an example of a phase difference detector.

FIG. 12 is a time chart for explaining the operation of the circuit in FIG. 12;

FIG. 13 is a circuit diagram illustrating an example of a VOC.

FIG. 14 is a circuit diagram illustrating an example of a frequency divider.

FIG. 15 is a circuit diagram illustrating an example of a sine wave conversion circuit.

FIG. 16 is a circuit diagram illustrating an example of a voltage balance circuit.

FIG. 17 is a circuit diagram illustrating an example of a cross current suppression circuit.

FIG. 18 is a diagram showing output characteristics of the amplitude of an output target waveform.

FIG. 19 is a diagram showing a time transition of the voltages of signals B and C in FIG. 16;

[Explanation of symbols]

Reference Signs List 3 Inverter and LPF (bridge type inverter circuit) 8 Sinusoidal circuit (output voltage adjusting means) 18 Voltage balance circuit (output voltage adjusting means) 19 Protection circuit 31 Cross current detecting circuit (internal voltage detecting circuit) T1 output terminals Q5 to Q8 FET (transistor) D3 ~ D6 Flywheel diode L1, L2 Choke coil

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/48 G05F 1/00 H02J 3/38

Claims (3)

(57) [Claims] 1. A DC output obtained by rectifying and smoothing an AC output output from a generator is supplied to a bridge-type inverter circuit, and the bridge-type inverter circuit is subjected to switching control in accordance with a drive signal, so that an output is obtained. A terminal is configured to take out an AC output of a predetermined frequency via a terminal, and a flywheel diode is connected in parallel to a transistor forming each arm of the bridge-type inverter circuit, and the bridge-type inverter circuit is connected to the output terminal. In a portable power supply device provided with a choke coil between the output terminals, when an output terminal of another power supply device is connected to the output terminal, the AC output voltage of the own power supply device and another power supply device are exchanged.
An internal voltage detection circuit that detects an increase in the DC voltage on the input side of the bridge-type inverter circuit due to a cross current caused by a difference between the output voltage and the output voltage, and the portable power supply device according to the voltage increase detection signal. Output voltage adjusting means for increasing the output voltage output from the output terminal of the parallel synchronous operation function characterized by having
Portable power supply device comprising. 2. The output voltage adjusting means adjusts the output voltage by controlling an amplitude of a reference sine wave signal which is a reference of a drive signal of the bridge type inverter circuit, and controls the output voltage by the internal voltage detection circuit. A rise in DC voltage on the input side of the bridge type inverter circuit is detected,
2. The parallel connection according to claim 1, wherein when the detected value exceeds a predetermined value, the amplitude of the reference sine wave signal is increased in accordance with the excess amount, and the output voltage is increased.
Portable power supply device with synchronous operation function . 3. A protection circuit for interrupting an output current in an overload state, wherein said output voltage adjusting means, when said output current exceeds a predetermined value, said reference sine corresponding to the excess amount. 3. The portable power supply device having a parallel synchronous operation function according to claim 2, wherein the amplitude of the wave signal is reduced to reduce the output voltage.