JPH0256012B2 - - Google Patents
Info
- Publication number
- JPH0256012B2 JPH0256012B2 JP58019397A JP1939783A JPH0256012B2 JP H0256012 B2 JPH0256012 B2 JP H0256012B2 JP 58019397 A JP58019397 A JP 58019397A JP 1939783 A JP1939783 A JP 1939783A JP H0256012 B2 JPH0256012 B2 JP H0256012B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- signal
- circuit
- supply system
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005856 abnormality Effects 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 1
Landscapes
- Direct Current Feeding And Distribution (AREA)
- Supply And Distribution Of Alternating Current (AREA)
Description
【発明の詳細な説明】
(1) 発明の属する技術分野の説明
本発明は、電源制御装置に関するもので、特に
電源異常発生に対するデータ・ログ方式に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a power supply control device, and particularly relates to a data logging method for the occurrence of a power supply abnormality.
(2) 従来技術の説明
電源制御装置においては、電源異常があつた場
合システム保護のためその電源制御装置をパワー
オフするのが一般的である。(2) Description of the Prior Art In a power supply control device, when a power supply abnormality occurs, it is common to turn off the power to protect the system.
従来、この種の電源制御装置は第１図に示すよ
うに電源システム１と電源異常箇所表示素子５−
ｉ（ｉ＝１〜ｎ）とから構成されていた。電源シ
ステム１は第２図に一例を示すように電源制御回
路３と電源回路４−ｉ（ｉ＝１〜ｎ）とにより構
成され、電源回路４−ｉがアラームになると、電
源制御回路３から電源異常箇所表示信号６を送出
し、表示素子５−ｉを点灯させる方法がとられて
いた。 Conventionally, this type of power supply control device has a power supply system 1 and a power supply abnormality display element 5- as shown in FIG.
i (i=1 to n). The power supply system 1 is composed of a power supply control circuit 3 and a power supply circuit 4-i (i=1 to n), as an example shown in FIG. A method has been adopted in which a power supply abnormality point display signal 6 is sent and the display element 5-i is turned on.
しかし、この方法では異常箇所を示す表示素子
５−ｉを調べる時点で電源システム１はすべにパ
ワー・オフしており、電源システム１がどのよう
な状態の時に異常になつたかがわからず、その原
因究明に多大の時間と労力を必要とするという欠
点があつた。 However, with this method, the power supply system 1 has already been powered off by the time the display element 5-i indicating the abnormality point is checked, so it is not possible to know what state the power supply system 1 was in when the abnormality occurred. The problem was that it required a lot of time and effort to investigate.
また従来の方法では、電源異常の内容を詳しく
知るためには表示素子の数を増加しなければなら
ず、加えて電源回路４−ｉ（ｉ＝１〜ｎ）の数が
増加すると、それに応じて表示素子の数が大幅に
増加することになり、広い実装スペースが必要と
なるばかりでなく、コストも高くなるという欠点
があつた。 In addition, in the conventional method, in order to know the details of the power supply abnormality, it is necessary to increase the number of display elements, and in addition, when the number of power supply circuits 4-i (i = 1 to n) increases, This results in a significant increase in the number of display elements, which not only requires a large mounting space but also increases costs.
(3) 発明の目的の説明
本発明の目的は、マイクロコンピユータを用い
て常時、電源システムの状態を監視し、電源異常
が発生したことを示す電源異常信号をトリガとし
て電源システムの状態を示すデータの更新をスト
ツプし、一方でパワー・オフシーケンスを並行し
て実行することにより上記欠点を解決し、電源シ
ステムの保護を行うとともに、電源異常発生時点
における電源システムの状態を詳細に知ることが
でき、かつ電源回路の数が増加してもスペース及
びコストの面に影響を与えない装置を提供するこ
とにある。(3) Description of the purpose of the invention The purpose of the present invention is to constantly monitor the status of a power supply system using a microcomputer and generate data indicating the status of the power supply system using a power supply abnormality signal that indicates that a power supply abnormality has occurred as a trigger. This solves the above drawback by stopping the update of the power supply system while simultaneously executing the power-off sequence, which protects the power supply system and allows detailed knowledge of the state of the power supply system at the time of a power failure. The object of the present invention is to provide a device that does not affect space and cost even when the number of power supply circuits increases.
(4) 発明の構成
本発明は、電源回路及び電源制御回路からなる
電源システムと、前記電源回路のアラーム信号及
び前記電源回路と電源制御回路との間の制御信号
を取り込み遂次内部メモリの更新を行い、前記電
源制御回路からの電源異常信号トリガとして内部
メモリの更新を止め、電源異常が発生した時点の
前記電源システムにおけるアラーム信号及び制御
信号を保持するマイクロコンピユータとから構成
したことを特徴とするものである。(4) Structure of the Invention The present invention provides a power supply system consisting of a power supply circuit and a power supply control circuit, and an internal memory that successively updates an alarm signal of the power supply circuit and a control signal between the power supply circuit and the power supply control circuit. and a microcomputer that stops updating the internal memory in response to a power supply abnormality signal trigger from the power supply control circuit, and holds an alarm signal and a control signal in the power supply system at the time when the power supply abnormality occurs. It is something to do.
(5) この発明の実施例の説明
次に本発明の実施例について図面を参照して詳
細に説明する。第３図は本発明の一実施例を示す
もので、第３図において、本発明の電源制御装置
は電源システム１とマイクロコンピユータ（以
下、マイコンという）２とから構成されている。
次に電源システム１の一例を示す第４図を参照し
ながら第３図の動作を説明する。(5) Description of embodiments of the present invention Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 shows an embodiment of the present invention. In FIG. 3, the power supply control device of the present invention is composed of a power supply system 1 and a microcomputer (hereinafter referred to as microcomputer) 2.
Next, the operation shown in FIG. 3 will be explained with reference to FIG. 4 showing an example of the power supply system 1.
まず、マイコン２は電源制御回路３から電源回
路４−ｉ（ｉ＝１〜ｎ）への信号、例えば電源オ
ン／オフ指示信号、電源回路４−ｉから電源制御
回路３への信号、例えばオン／オフ完了信号、ア
ラーム信号等を電源システム１の状態信号として
取り込み、マイコン２の内部メモリを遂次最新の
状態に更新しつづける。 First, the microcomputer 2 receives a signal from the power supply control circuit 3 to the power supply circuit 4-i (i=1 to n), such as a power on/off instruction signal, and a signal from the power supply circuit 4-i to the power supply control circuit 3, such as an on/off instruction signal. /Off completion signal, alarm signal, etc. are taken in as status signals of the power supply system 1, and the internal memory of the microcomputer 2 is continuously updated to the latest status.
電源回路４−ｉでアラームが発生すると、アラ
ーム信号が電源制御回路３に送出されると同時
に、電源システムの状態信号としてマイコン２に
送出される。電源制御回路３ではアラーム信号を
受信すると、電源回路４−ｉに対してオフ指示信
号を送出すると同時に、マイコン２に対して電源
異常信号を送出する。マイコン２では電源制御回
路３からの電源異常信号をトリガとしてマイコン
２の内部メモリの更新をストツプする。 When an alarm occurs in the power supply circuit 4-i, an alarm signal is sent to the power supply control circuit 3, and at the same time, it is sent to the microcomputer 2 as a status signal of the power supply system. When the power supply control circuit 3 receives the alarm signal, it transmits an off instruction signal to the power supply circuit 4-i, and simultaneously transmits a power abnormality signal to the microcomputer 2. The microcomputer 2 uses the power abnormality signal from the power supply control circuit 3 as a trigger to stop updating of the internal memory of the microcomputer 2.
従つてマイコン２の内部メモリには電源回路４
−ｉでアラームが発生した瞬間の電源システム全
体の状態信号が保持されることになる。 Therefore, the internal memory of the microcomputer 2 contains the power supply circuit 4.
The status signal of the entire power supply system at the moment when the alarm occurred at -i is held.
(6) 発明の効果の説明
本発明は以上説明したように、電源回路がアラ
ームになつた時点の電源システムの状態を保持す
るようにしたので、アラームの発生原因を詳細
に、かつ迅速に発見できる効果がある。(6) Description of effects of the invention As explained above, the present invention maintains the state of the power system at the time when the power circuit generates an alarm, so that the cause of the alarm can be discovered in detail and quickly. There is an effect that can be achieved.
第１図は、電源異常を表示する従来の方法を示
すブロツク図、第２図は第１図における電源シス
テムの一例を示す回路図、第３図は本発明の一実
施例を示すブロツク図、第４図は第３図における
電源システムの一例を示す回路図である。
１……電源システム、２……マイクロコンピユ
ータ、３……電源制御回路、４−ｉ（ｉ＝１〜ｎ）
……電源回路、７……電源異常信号、８……電源
システムの状態信号。
FIG. 1 is a block diagram showing a conventional method for displaying a power supply abnormality, FIG. 2 is a circuit diagram showing an example of the power supply system in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a circuit diagram showing an example of the power supply system in FIG. 3. 1... Power supply system, 2... Microcomputer, 3... Power supply control circuit, 4-i (i=1 to n)
...Power supply circuit, 7...Power supply abnormality signal, 8...Power system status signal.
Claims (1)
テムと、前記電源回路のアラーム信号及び前記電
源回路と電源制御回路との間の制御信号を取り込
み遂次内部メモリの更新を行い、前記電源制御回
路からの電源異常信号をトリガとして内部メモリ
の更新を止め、電源異常が発生した時点の前記電
源システムにおけるアラーム信号及び制御信号を
保持するマイクロコンピユータとから構成したこ
とを特徴とする電源制御装置。1 A power supply system consisting of a power supply circuit and a power supply control circuit, an alarm signal of the power supply circuit, and a control signal between the power supply circuit and the power supply control circuit are taken in, and the internal memory is successively updated, and the internal memory is updated. A power supply control device comprising: a microcomputer that stops updating an internal memory using a power supply abnormality signal as a trigger, and holds an alarm signal and a control signal in the power supply system at the time when a power supply abnormality occurs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58019397A JPS59148531A (en) | 1983-02-08 | 1983-02-08 | Power source controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58019397A JPS59148531A (en) | 1983-02-08 | 1983-02-08 | Power source controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59148531A JPS59148531A (en) | 1984-08-25 |
| JPH0256012B2 true JPH0256012B2 (en) | 1990-11-29 |
Family
ID=11998137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58019397A Granted JPS59148531A (en) | 1983-02-08 | 1983-02-08 | Power source controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59148531A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4673824A (en) * | 1986-03-03 | 1987-06-16 | Tektronix, Inc. | Power supply switch circuit |
| JPH01144555A (en) * | 1987-11-30 | 1989-06-06 | Yokogawa Electric Corp | High-frequency induction-coupled plasma analyzer |
| JP2638257B2 (en) * | 1990-05-16 | 1997-08-06 | 株式会社ユアサコーポレーション | Error handling circuit for control power supply |
-
1983
- 1983-02-08 JP JP58019397A patent/JPS59148531A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59148531A (en) | 1984-08-25 |
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