JPH0255339U - - Google Patents
Info
- Publication number
- JPH0255339U JPH0255339U JP13324888U JP13324888U JPH0255339U JP H0255339 U JPH0255339 U JP H0255339U JP 13324888 U JP13324888 U JP 13324888U JP 13324888 U JP13324888 U JP 13324888U JP H0255339 U JPH0255339 U JP H0255339U
- Authority
- JP
- Japan
- Prior art keywords
- channel
- computer system
- standardized
- processor
- communication control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の基本的な構成を示す構成ブロ
ツク図、第２図は本考案の一実施例を示す構成ブ
ロツク図、第３図は動作の一例を示すタイムチヤ
ート、第４図はＳＣＳＩ等の規格化されたＩ／Ｏ
チヤンネルを介して複数のコンピユータが結合し
て構成されるシステムの構成概念図、第５図は第
４図におけるコンピユータ内部の構成概念図であ
る。
１，２…ホストコンピユータ、３…共有デイバ
イス、１１…プロセツサ、１２…メモリ、１３…
Ｉ／Ｏインターフエイスチヤネル部、１４…コマ
ンド処理部、１５…ホストインターフエイス、１
６…ＳＣＳＩインターフエイス、１７…ＤＭＡ制
御部。
Fig. 1 is a block diagram showing the basic structure of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing an example of operation, and Fig. 4 is a SCSI Standardized I/O such as
FIG. 5 is a conceptual diagram of a system configured by connecting a plurality of computers via a channel. FIG. 5 is a conceptual diagram of the internal configuration of the computer in FIG. 4. 1, 2...Host computer, 3...Shared device, 11...Processor, 12...Memory, 13...
I/O interface channel section, 14... Command processing section, 15... Host interface, 1
6...SCSI interface, 17...DMA control section.
Claims (1)
いる複数のホストコンピユータからなるコンピユ
ータ・システムにおいて、 前記Ｉ／Ｏチヤネルインターフエイス部に、別
のホストコンピユータからＩ／Ｏチヤネルを介し
て送られるコマンドの処理部を設け、当該コマン
ド処理部において、通信制御の為のコマンド処理
を行うようにしたことを特徴とするコンピユータ
・システム。[Claims for Utility Model Registration] In a computer system consisting of a plurality of host computers connected via a standardized I/O channel, an 1. A computer system comprising: a processor for processing commands sent via a /O channel; and the command processor processes commands for communication control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13324888U JPH0255339U (en) | 1988-10-12 | 1988-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13324888U JPH0255339U (en) | 1988-10-12 | 1988-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0255339U true JPH0255339U (en) | 1990-04-20 |
Family
ID=31390935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13324888U Pending JPH0255339U (en) | 1988-10-12 | 1988-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0255339U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5537642A (en) * | 1978-09-08 | 1980-03-15 | Fujitsu Ltd | Inter-processor communication system |
-
1988
- 1988-10-12 JP JP13324888U patent/JPH0255339U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5537642A (en) * | 1978-09-08 | 1980-03-15 | Fujitsu Ltd | Inter-processor communication system |