JPH0254933A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0254933A JPH0254933A JP20608588A JP20608588A JPH0254933A JP H0254933 A JPH0254933 A JP H0254933A JP 20608588 A JP20608588 A JP 20608588A JP 20608588 A JP20608588 A JP 20608588A JP H0254933 A JPH0254933 A JP H0254933A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- substrate
- oxide film
- oxygen
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 26
- 239000001301 oxygen Substances 0.000 claims abstract description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims description 17
- 230000007547 defect Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 5
- 230000001376 precipitating effect Effects 0.000 claims 2
- 238000005247 gettering Methods 0.000 abstract description 32
- 239000012535 impurity Substances 0.000 abstract description 9
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000001133 acceleration Effects 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 2
- -1 Phosphorus ions Chemical class 0.000 abstract 1
- 238000010521 absorption reaction Methods 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 239000002244 precipitate Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000011109 contamination Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001556 precipitation Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は、重金属汚染等を取り除くためのゲッタリング
サイトを形成する半導体装置の製造方法に係わり、特に
ゲッタリングサイトを基板の主表面側に形成する半導体
装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device that forms gettering sites for removing heavy metal contamination, etc. The present invention relates to a method of manufacturing a semiconductor device formed on the main surface side of a semiconductor device.
(従来の技術)
゛ト導体装置の製造工程中に導入される重金属汚染は、
自由電子(正孔)のトラップ、放出の中心を形成したり
、pn接合のリークの原因となり、半導体素子の電気的
特性を劣化させる。例えば、MO5半導体素子において
は、重金属による1゜り電流が相互コンダクタンスの低
下等を引き起こし、歩留り低下の大きな原因となる。一
方、最近の半導体集積回路の素子数の増加、それに伴う
半導体集積回路の素子寸法の減少は、微量な汚染が素子
特性や集積回路の歩留りに影響を与えることを意味する
。(Prior art) Heavy metal contamination introduced during the manufacturing process of conductor devices is
It forms a center for trapping and emitting free electrons (holes), causes leakage of pn junctions, and deteriorates the electrical characteristics of semiconductor devices. For example, in MO5 semiconductor devices, a 1° current caused by heavy metals causes a decrease in mutual conductance, etc., which is a major cause of a decrease in yield. On the other hand, the recent increase in the number of elements in semiconductor integrated circuits and the accompanying decrease in the element dimensions of semiconductor integrated circuits means that trace amounts of contamination affect element characteristics and the yield of integrated circuits.
従来、このような汚染をゲッタリングする方法として、
半導体基板の裏面に機械的場傷を与えたり高濃度の不純
物を導入し、これに汚染重金属を吸収する方法が用いら
れている。しかしながら、このような裏面処理は製造工
程の初期に行われるため、表面からの2Ti染を防ぐた
めに余分の工程を必要としたり、多数の熱処理工程を経
るうちに効果がす1モ減してしまう等の欠点があった。Traditionally, methods for gettering such contamination include
A method is used in which heavy metal contamination is absorbed by mechanically damaging the back surface of a semiconductor substrate or introducing high-concentration impurities. However, since such back surface treatment is performed at the beginning of the manufacturing process, an extra step is required to prevent 2Ti staining from the front surface, and the effectiveness decreases by 1 mo after going through multiple heat treatment steps. There were drawbacks such as.
また、集積回路の製造に当たっては、厚いフィールド酸
化膜により素子分離nfl域には応力がかかり重金属等
の不純物が集まりリーク電流を生じ易くすると言う問題
があった。Further, in the manufacture of integrated circuits, there is a problem in that the thick field oxide film applies stress to the element isolation nfl region, causing impurities such as heavy metals to collect therein, making it easy to generate leakage current.
(発明が解決しようとする課題)
このように従来、半導体基板の裏面側にゲッタリングサ
イトを形成する方法では、表面からの汚染を防ぐために
余分の工程を行わなければならない、また素子工程の初
期にゲッタリングサイトを形成するため多数の熱処理を
経るうちにゲッタリング能力が落ちてくる問題があった
。(Problems to be Solved by the Invention) As described above, in the conventional method of forming gettering sites on the back side of a semiconductor substrate, an extra step is required to prevent contamination from the surface, and the There is a problem in that the gettering ability deteriorates after undergoing multiple heat treatments to form gettering sites.
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、余分の工程を必要とせず、多数の熱
工程を経てもその効果の減少しないゲッタリングサイト
を形成することができ、半導体素子の製造歩留り向上環
に寄与し得る半導体装置の製造方法を提供することにあ
る。The present invention has been made in consideration of the above circumstances, and its purpose is to form a gettering site that does not require any extra steps and whose effectiveness does not decrease even after multiple thermal steps. An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to improving the manufacturing yield of semiconductor devices.
[発明の構成]
(課題を解決するための手段)
本発明の骨子は、半導体基板上に形成される素子のpn
接合よりも深い領域にイオン注入を行い、それに続く最
初の熱処理条件を最適化して、基板の主表面側にゲッタ
リングサイトを形成することにある。[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to provide a pn of an element formed on a semiconductor substrate.
The purpose of this method is to perform ion implantation in a region deeper than the junction, then optimize the initial heat treatment conditions to form gettering sites on the main surface side of the substrate.
即ち本発明は、ゲッタリングサイトを持つ半導体装置の
製造方法において、半導体基板の主表面から該基板上に
形成される半導体素子のpn接合よりも深い領域にイオ
ン注入を行って結晶欠陥の核を形成し、次いでこれに続
く最初の熱処理を900〜1100℃で15分以上行い
前記結晶欠陥の核に酸素を析出させるようにした方法で
ある。ここで、熱処理温度900℃未満ではトラップさ
れる欠陥層が形成されず、また1100’Cより高い場
合固溶限が高くなるため、この欠陥が存在してもトラッ
プされない。That is, the present invention is a method for manufacturing a semiconductor device having a gettering site, in which ions are implanted from the main surface of a semiconductor substrate into a region deeper than the pn junction of a semiconductor element formed on the substrate to remove the nuclei of crystal defects. In this method, a first heat treatment is performed at 900 to 1100° C. for 15 minutes or more to precipitate oxygen at the nuclei of the crystal defects. Here, if the heat treatment temperature is lower than 900° C., a defect layer to be trapped is not formed, and if the heat treatment temperature is higher than 1100° C., the solid solubility limit becomes high, so even if such defects exist, they are not trapped.
また本発明は、ゲッタリングサイトを持つ半導体装置の
製造方法において、半導体基板の主表面に素子分離のた
めのフィールド酸化膜を形成したのち、この酸化膜を通
してJJ 、Nにイオン注入を行って結晶欠陥の核を形
成し、次いでこれに続く最初の熱処理を900〜110
0℃で15分以上行い、前記酸化膜の直下に反転層を形
成すると共に前記結晶欠陥の核に酸素を析出させるよう
にした方法である。The present invention also provides a method for manufacturing a semiconductor device having gettering sites, in which a field oxide film for element isolation is formed on the main surface of a semiconductor substrate, and then ions are implanted into JJ and N through this oxide film to crystallize. Nucleation of the defects and subsequent initial heat treatment at 900-110°C
This method is performed at 0° C. for 15 minutes or more to form an inversion layer directly under the oxide film and to precipitate oxygen at the nuclei of the crystal defects.
(作 用)
本発明によれば、半導体基板の主表面側にゲッタリング
サイトが形成されるので、このゲッタリングサイトによ
り素子形成領域における汚染重金属を吸収することがで
き、素子の製造歩留り向上をはかることが可能である。(Function) According to the present invention, gettering sites are formed on the main surface side of the semiconductor substrate, so that the gettering sites can absorb heavy metal contamination in the element formation region, thereby improving the manufacturing yield of the elements. It is possible to measure it.
また、基板の裏面側にゲッタリングサイトを形成する方
法とは異なり1、熱処理工程を経るうちにゲッタリング
効果が半減する等の不都合もない。Furthermore, unlike the method of forming gettering sites on the back side of the substrate, there is no inconvenience such as the gettering effect being reduced by half during the heat treatment process.
(実施例)
まず、実施例を説明する前に、本発明の基本原理につい
て説明する。(Example) First, before describing an example, the basic principle of the present invention will be explained.
本発明者等は、数McV以上の高エネルギーイオン注入
により基板表面から数μmの領域に結晶欠陥の核を形成
した後、温度条件を種々変えて熱処理を行った。その結
果、900〜1loo’cで熱処理を行った試料では、
透過型電子顕微鏡で測定したところ、イオン注入条件よ
り定まるRp(イオンの侵入深さ)の位置に転位ループ
が観測された。さらに、2次イオン質量分析法で測定を
したところ、上記電子顕微鏡で観測されたのと同じ位置
に酸素のピークが観aF+され、この位置に酸素の析出
が起こっていることが確認された。The present inventors formed crystal defect nuclei in a region several μm from the substrate surface by high-energy ion implantation of several McV or more, and then performed heat treatment under various temperature conditions. As a result, in the samples heat-treated at 900 to 1 loo'c,
When measured using a transmission electron microscope, a dislocation loop was observed at the position Rp (ion penetration depth) determined by the ion implantation conditions. Furthermore, when measurements were performed using secondary ion mass spectrometry, an oxygen peak was observed aF+ at the same position as observed using the electron microscope, and it was confirmed that oxygen was precipitated at this position.
また、900℃未満或いは1100’cより高い熱処理
温度では上記転位ループが減少するのが観f1glされ
、さらに1200℃、 800’Cで熱処理した場合
にはこのような酸素の析出は殆ど見られなかった。なお
、熱処理時間は差はど影響ないが、あまりに短いと90
0〜1100℃の志度でも酸素の析出が不十分である。Furthermore, it has been observed that the above dislocation loops decrease at heat treatment temperatures below 900°C or higher than 1100'C, and when the heat treatment is conducted at 1200°C and 800'C, almost no such oxygen precipitation is observed. Ta. Note that the difference in heat treatment time has no effect, but if it is too short, 90%
Even at a temperature of 0 to 1100°C, oxygen precipitation is insufficient.
本発明者等の実験によれば、熱処理時間は15分間以上
もあれば十分であることが確認された。According to experiments conducted by the present inventors, it has been confirmed that a heat treatment time of 15 minutes or more is sufficient.
このような析出物が形成された試料では、それ以外の領
域に転位は観δP1されていない。従って、本発明のよ
うにイオン注入後900〜1100℃の温度で15分以
上熱処理することにより、基板の主表面側に酸素の析出
層を形成することができ、この析出層を安定なゲッタリ
ングサイトとして使用することが可能となる。In the sample in which such precipitates were formed, no dislocations δP1 were observed in other regions. Therefore, by performing heat treatment at a temperature of 900 to 1100°C for 15 minutes or more after ion implantation as in the present invention, an oxygen precipitate layer can be formed on the main surface side of the substrate, and this precipitate layer can be used as a stable gettering layer. It can be used as a website.
以下、本発明の詳細を図示の実施例によりて説明する。Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第1図は本発明の一実施例方法に係わる半導体装置の製
造工程を示す断面図である。まず、第1図(a)に示す
如く、シリコン基板11に加速電圧1.5McVで不純
物12としての燐をI X 1015cm−2イオン注
入した。このような基板を5枚用意した。FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), ions of phosphorus as an impurity 12 were implanted into a silicon substrate 11 at an acceleration voltage of 1.5 McV at I.times.10.sup.15 cm.sup.-2. Five such substrates were prepared.
なお、このイオン注入は室温で行った。次いで、第1図
(b)に示す如く、これらの基板11を非酸化性雰囲気
中で、窒素雰゛囲気中の温度を夫々 800゜900、
1000.1100.1200℃にして20分間の熱処
理を行った。この熱処理により、第1図(C)に示す如
(基板表面側に酸素の析出層13を形成した。Note that this ion implantation was performed at room temperature. Next, as shown in FIG. 1(b), these substrates 11 were heated in a non-oxidizing atmosphere at temperatures of 800°, 900°, and 900° respectively in a nitrogen atmosphere.
Heat treatment was performed at 1000.1100.1200° C. for 20 minutes. As a result of this heat treatment, an oxygen precipitate layer 13 was formed on the substrate surface side as shown in FIG. 1(C).
上記熱処理後に試料の断面構造を透過型電子顕微鏡によ
り調べたところ、900.1000.1100℃で熱処
理した基板には第2図に示す如<Rpに対応する基板表
面10より約1.7μmの位置に酸素が析出しているこ
とが確認された。さらに、各基板を2次イオン質量分析
法により調べたところ、第3図に示す如< 90(1
,100(1,1100℃で熱処理した基板には深さ
1.7μm付近に燐のピークと共に酸素のピークが存在
することが確認された。但し、第3図で (a)は 8
00℃、 (b)は 900℃、 (c)は1000℃
、 (d)は1100℃、 (e)は1200℃で熱処
理した場合を示している。そして、この酸素の析出物は
その後の素子形成工程においてゲッタリングサイトとし
て有効に作用することも確かめられた。After the above heat treatment, the cross-sectional structure of the sample was examined using a transmission electron microscope. As shown in FIG. It was confirmed that oxygen was precipitated. Furthermore, when each substrate was examined by secondary ion mass spectrometry, it was found that <90 (1
, 100 (1,1100°C heat treated substrate has a depth
It was confirmed that an oxygen peak existed in the vicinity of 1.7 μm along with a phosphorus peak. However, in Figure 3, (a) is 8
00℃, (b) is 900℃, (c) is 1000℃
, (d) shows the case of heat treatment at 1100°C, and (e) shows the case of heat treatment at 1200°C. It was also confirmed that this oxygen precipitate effectively acts as a gettering site in the subsequent element forming process.
なお、深さ 1.7μmは通常の素子の形成に際しては
素子形成領域よりも十分深い深さであり、このゲッタリ
ングサイトが素子形成に不都合を与えることはない。Note that the depth of 1.7 μm is sufficiently deeper than the element formation region when forming a normal element, and this gettering site does not cause any inconvenience to the element formation.
このように本実施例方法では、半導体素子形成の初期に
おいて全面にイオン注入を行うため、イオン注入及び所
定温度の熱処理の2工程でゲッタリングサイトを形成す
ることができる。また、形成されたゲッタリングサイト
は酸素の析出物であるため、従来法の燐ゲッタリングに
比べてゲッタリングサイトか多く、外方拡散等の問題も
ない。As described above, in the method of this embodiment, since ions are implanted over the entire surface at the initial stage of semiconductor element formation, gettering sites can be formed in two steps: ion implantation and heat treatment at a predetermined temperature. Further, since the formed gettering sites are oxygen precipitates, there are more gettering sites than in the conventional method of phosphorus gettering, and there are no problems such as outward diffusion.
また、本工程後に続く素子形成工程では、900℃以上
の高温プロセスにおいてはプロセス中に酸素が析出し新
たにゲッタリングサイトが形成されるため常にゲッタリ
ング能力が追加される。従って、基板結晶無欠陥化処理
工程を、大幅な工程簡略によって容易に且つ確実に実施
することができ、素子製造歩留まりの向上等に寄与する
ことができる。Further, in the element formation step that follows this step, gettering ability is always added because oxygen precipitates during the process and new gettering sites are formed in the high temperature process of 900° C. or higher. Therefore, the substrate crystal defect-free treatment step can be carried out easily and reliably by greatly simplifying the process, and can contribute to improving the device manufacturing yield and the like.
次に、本発明の他の実施例について説明する。Next, other embodiments of the present invention will be described.
第4図は本発明の他の実施例方法を説明するための断面
図であり、これは本発明をMOSFET間の素子分離に
応用した例である。FIG. 4 is a sectional view for explaining another embodiment method of the present invention, and this is an example in which the present invention is applied to element isolation between MOSFETs.
本実施例では、フィールドイオン注入を先の実施例同様
に高エネルギーで行い、先の実施例と同様の熱処理を施
すことにより、フィールド直下に重金属等をゲッタリン
グする部分を形成するようにしている。第4図(a)に
示す如く、シリコン基板41上にフィールド酸化膜42
を形成した後、フィールドのイオン注入43を高エネル
ギーで行い、さらに先の実施例と同様の熱処理を施した
。In this example, the field ion implantation is performed at high energy as in the previous example, and the same heat treatment as in the previous example is performed to form a part for gettering heavy metals etc. directly under the field. . As shown in FIG. 4(a), a field oxide film 42 is formed on a silicon substrate 41.
After forming, field ion implantation 43 was performed at high energy, followed by heat treatment similar to the previous example.
これにより、フィールド酸化膜42の直下に反転層44
を形成すると共にその下の領域に酸素析出層45を形成
することができた。つまり、フィールドイオン注入とゲ
ッタリング層形成が同時に行えることになる。As a result, an inversion layer 44 is formed directly under the field oxide film 42.
It was possible to form an oxygen precipitated layer 45 in the region below it. In other words, field ion implantation and gettering layer formation can be performed simultaneously.
ここで、酸素析出層45の位置がフィールド酸化膜42
に近すぎると、素子分離にリークを与える虞れがある。Here, the position of the oxygen precipitated layer 45 is located at the field oxide film 42.
If it is too close to , there is a risk of leakage in device isolation.
さらに、反転層44の不純物濃度は素子分離のためにあ
る一定以上の量が必要である。従って、イオン注入条件
は、ドーズ量をフィールド酸化膜直下のドーパント濃度
が素子分離に十分な量となるように、またその注入エネ
ルギーを注入ドーパントの投影飛程(Rp)を中心に形
成される酸素の析出物が素子分離にリークを与えない程
度に十分深くなるように選べばよい。Furthermore, the impurity concentration of the inversion layer 44 needs to be higher than a certain level for element isolation. Therefore, the ion implantation conditions are such that the dose is set so that the dopant concentration directly under the field oxide film is sufficient for device isolation, and the implantation energy is set so that the implanted dopant's projected range (Rp) is the center of the oxygen formation. The depth may be selected so that the precipitates are sufficiently deep to the extent that they do not cause leakage to device isolation.
このようにして条件を選びフィールド酸化膜を介してイ
オン注入を行い、その後先の実施例と同様の処理を施し
た。その結果、熱処理工程後もドーパントの再拡散は殆
どなく、フィールド酸化膜下での素子分離を行うと同時
に、従来応力により生じていた不純物の影響を取り除く
ためのゲッタリングサイトを素子にリークを与えない程
度に十分深い領域に形成することができた。この時のS
IMS分析結果(2次イオン質量分析法で測定をした結
果)を第5図に示す。このように、従来の素子分離イオ
ン注入と略同じ工程数で、更にゲッタリングサイトを形
成することが可能となった。The conditions were selected in this way and ions were implanted through the field oxide film, followed by the same treatment as in the previous example. As a result, there is almost no re-diffusion of dopants even after the heat treatment process, and at the same time, the elements are isolated under the field oxide film, and at the same time, gettering sites are created to eliminate the effects of impurities that conventionally occur due to stress. We were able to form it in a sufficiently deep area to the extent that it did not. S at this time
The IMS analysis results (results measured by secondary ion mass spectrometry) are shown in FIG. In this way, it has become possible to further form gettering sites with approximately the same number of steps as conventional element isolation ion implantation.
なお、第4図(a)に示す工程の後は、同図(b)に示
す如くゲート酸化膜46を介してゲート電極47を形成
し、さらにゲート電極47をマスクにソース・ドレイン
領域48a、48b形成のためのイオン注入を行うこと
により、フィールド酸化膜42により素子分離された2
つのMOSFETが完成することになる。なお、前記ゲ
ッタリングサイト形成のためのイオン注入は素子形成後
に行うことも可能である。After the step shown in FIG. 4(a), a gate electrode 47 is formed through the gate oxide film 46 as shown in FIG. 4(b), and then using the gate electrode 47 as a mask, source/drain regions 48a, By performing ion implantation to form 48b, two elements separated by the field oxide film 42 are formed.
Two MOSFETs will be completed. Note that the ion implantation for forming the gettering site can also be performed after the element is formed.
かくして本実施例方法によれば、基板表面側の特にフィ
ールド酸化膜直下に酸素析出層を形成することができ、
この酸素析出層をゲッタリングサイトとして使用するこ
とができる。従って、先の実施例と同様に素子製造歩留
りの向上をはかることができる。しかも、フィールドイ
オン注入と同時に酸素析出層形成を行うことができるの
で、製造工程の簡略化をはかることも可能である。Thus, according to the method of this embodiment, an oxygen precipitated layer can be formed on the substrate surface side, especially directly under the field oxide film,
This oxygen precipitated layer can be used as a gettering site. Therefore, as in the previous embodiment, it is possible to improve the device manufacturing yield. Furthermore, since the formation of the oxygen precipitated layer can be performed simultaneously with the field ion implantation, it is also possible to simplify the manufacturing process.
なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記熱処理条件は900〜1100℃に
限るものではなく、基板表面側に酸素の析出層が形成さ
れる温度であればよい。本発明者等の実験では、900
〜1100℃の範囲であれば確実に酸素の析出層が形成
されるのが判明している。Note that the present invention is not limited to the embodiments described above. For example, the heat treatment conditions are not limited to 900 to 1100°C, and may be any temperature at which a precipitated layer of oxygen is formed on the surface of the substrate. In experiments conducted by the inventors, 900
It has been found that an oxygen precipitate layer is reliably formed within the range of ~1100°C.
さらに、熱処理時間は20分に同等限定されるものでは
なく、イオン注入量や注入深さ等の条件により適宜変更
可能である。−数的には、15分以上程度の処理時間で
あれば十分である。また、イオン注入する不純物は燐に
限るものではなく、ゲッタリングサイトとして作用する
ものを適宜選択すればよい。その他、本発明の要旨を逸
脱しない範囲で、種々変形して実施することができる。Further, the heat treatment time is not limited to 20 minutes, but can be changed as appropriate depending on conditions such as the amount of ion implantation and the depth of implantation. - Numerically speaking, a processing time of about 15 minutes or more is sufficient. Further, the impurity to be ion-implanted is not limited to phosphorus, and any impurity that acts as a gettering site may be selected as appropriate. In addition, various modifications can be made without departing from the gist of the present invention.
[発明の効果]
以上詳述したように本発明によれば、半導体基板上に形
成される素子のpn接合よりも深い領域にイオン注入を
行い、それに続く最初の熱処理条件を最適化することに
より、多数の熱工程を経てもその効果の減少しないゲッ
タリングサイトを形成することができ、半導体素子の製
造歩留り向上等に寄与することが可能となる。[Effects of the Invention] As detailed above, according to the present invention, ion implantation is performed in a region deeper than the pn junction of an element formed on a semiconductor substrate, and by optimizing the subsequent initial heat treatment conditions, , it is possible to form a gettering site whose effect does not decrease even after a large number of thermal processes, and it is possible to contribute to improving the manufacturing yield of semiconductor devices.
第1図は本発明の一実施例に係わる半導体装置の製造工
程を示す断面図、第2図は上記工程後の試料の断面構造
を示す模式図、第3図は上記工程後の試料の2次イオン
質量分析法による分析結果を示す特性図、第4図は本発
明の他の実施例を説明するための工程断面図、第5図は
第4図に続き熱処理工程を施した試料の2次イオン質量
分析法による分析結果を示す特性図である。
11.41・・・シリコン基板、1.2.43・・・燐
(注入不純物)、13.45・・・酸素析出層、42・
・・フィールド酸化膜、44・・・反転層、46・・・
ゲート酸化膜、47・・・ゲート電極、48a、48b
・・ソース・ドレイン領域。FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the cross-sectional structure of a sample after the above process, and FIG. 4 is a cross-sectional view of a process for explaining another embodiment of the present invention, and FIG. 5 is a second diagram of a sample subjected to a heat treatment process following FIG. 4. FIG. 3 is a characteristic diagram showing analysis results by secondary ion mass spectrometry. 11.41... Silicon substrate, 1.2.43... Phosphorus (implanted impurity), 13.45... Oxygen precipitation layer, 42.
...Field oxide film, 44...Inversion layer, 46...
Gate oxide film, 47...gate electrode, 48a, 48b
...Source/drain region.
Claims (3)
導体素子のpn接合よりも深い領域にイオン注入を行っ
て結晶欠陥の核を形成する工程と、次いでこれに続く最
初の熱処理を900〜1100℃で行い前記結晶欠陥の
核に酸素を析出させる工程とを含むことを特徴とする半
導体装置の製造方法。(1) A step of implanting ions from the main surface of the semiconductor substrate into a region deeper than the pn junction of the semiconductor element formed on the substrate to form crystal defect nuclei, followed by a first heat treatment for 900 days. A method for manufacturing a semiconductor device, comprising the step of precipitating oxygen at the nuclei of the crystal defects by performing the process at a temperature of 1100°C to 1100°C.
ド酸化膜を形成する工程と、次いで前記酸化膜を通して
前記基板にイオン注入を行って結晶欠陥の核を形成する
工程と、次いでこれに続く最初の熱処理を900〜11
00℃で行い、前記酸化膜の直下に反転層を形成すると
共に前記結晶欠陥の核に酸素を析出させる工程とを含む
ことを特徴とする半導体装置の製造方法。(2) a step of forming a field oxide film for element isolation on the main surface of a semiconductor substrate; then a step of implanting ions into the substrate through the oxide film to form crystal defect nuclei; First heat treatment to 900-11
A method for manufacturing a semiconductor device, comprising: forming an inversion layer directly under the oxide film and precipitating oxygen at the nuclei of the crystal defects, the method being performed at 00°C.
ーパント濃度が素子分離に必要十分となり、且つ注入ド
ーパントの投影飛程(Rp)が素子分離にリーク電流を
与えない深さに設定したことを特徴とする請求項2記載
の半導体装置の製造方法。(3) The conditions for the ion implantation are that the dopant concentration under the oxide film is necessary and sufficient for device isolation, and the projected range (Rp) of the implanted dopant is set to a depth that does not cause leakage current to device isolation. 3. The method of manufacturing a semiconductor device according to claim 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63206085A JP2744022B2 (en) | 1988-08-19 | 1988-08-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63206085A JP2744022B2 (en) | 1988-08-19 | 1988-08-19 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0254933A true JPH0254933A (en) | 1990-02-23 |
JP2744022B2 JP2744022B2 (en) | 1998-04-28 |
Family
ID=16517571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP63206085A Expired - Lifetime JP2744022B2 (en) | 1988-08-19 | 1988-08-19 | Method for manufacturing semiconductor device |
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JP (1) | JP2744022B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008103664A (en) * | 2006-09-20 | 2008-05-01 | Fujifilm Corp | Rear irradiation type imaging element, manufacturing method of same and imaging apparatus equipped with same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5618430A (en) * | 1979-07-25 | 1981-02-21 | Fujitsu Ltd | Manufacture of semiconductor element |
JPS59188925A (en) * | 1983-04-12 | 1984-10-26 | Toshiba Corp | Manufacture of semiconductor device |
JPS6042840A (en) * | 1983-08-19 | 1985-03-07 | Toshiba Corp | Method for processing semiconductor wafer |
JPS6084813A (en) * | 1983-10-17 | 1985-05-14 | Toshiba Corp | Manufacture of semiconductor device |
JPS6151930A (en) * | 1984-08-22 | 1986-03-14 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-08-19 JP JP63206085A patent/JP2744022B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5618430A (en) * | 1979-07-25 | 1981-02-21 | Fujitsu Ltd | Manufacture of semiconductor element |
JPS59188925A (en) * | 1983-04-12 | 1984-10-26 | Toshiba Corp | Manufacture of semiconductor device |
JPS6042840A (en) * | 1983-08-19 | 1985-03-07 | Toshiba Corp | Method for processing semiconductor wafer |
JPS6084813A (en) * | 1983-10-17 | 1985-05-14 | Toshiba Corp | Manufacture of semiconductor device |
JPS6151930A (en) * | 1984-08-22 | 1986-03-14 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008103664A (en) * | 2006-09-20 | 2008-05-01 | Fujifilm Corp | Rear irradiation type imaging element, manufacturing method of same and imaging apparatus equipped with same |
Also Published As
Publication number | Publication date |
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JP2744022B2 (en) | 1998-04-28 |
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