JPH0645270A - Method for heat-treating semiconductor substrate - Google Patents

Method for heat-treating semiconductor substrate

Info

Publication number
JPH0645270A
JPH0645270A JP21665892A JP21665892A JPH0645270A JP H0645270 A JPH0645270 A JP H0645270A JP 21665892 A JP21665892 A JP 21665892A JP 21665892 A JP21665892 A JP 21665892A JP H0645270 A JPH0645270 A JP H0645270A
Authority
JP
Japan
Prior art keywords
heat treatment
heat
semiconductor substrate
ion implantation
lattice defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP21665892A
Other languages
Japanese (ja)
Inventor
Junichi Shimomura
順一 下村
Nobuyuki Okimoto
信之 沖本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP21665892A priority Critical patent/JPH0645270A/en
Publication of JPH0645270A publication Critical patent/JPH0645270A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To reduce a lattice defect of the part where ions are implanted by suitably heat treating after ion implantion. CONSTITUTION:After ions of As, P, B, BF2, etc., are implanted in a semiconductor substrate, a first heat treatment is conducted at 600 to 800 deg.C, and then a second heat treatment is executed at 800 less than 1000 deg.C. It is desirable to execute the second treatment for 500sec or longer. The first treatment is conducted by lamping, and the second treatment can be executed for 500sec or longer. Further, the first and second treatments may be conducted in a lamp- annealing furnace.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板の熱処理方
法に関し、さらに詳しくは、集積回路などの半導体素
子、とくにAs,P,B,BF2 等のイオンを注入した
部分の半導体素子の格子欠陥を低減するための熱処理方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for heat treating a semiconductor substrate, and more particularly to a semiconductor device such as an integrated circuit, particularly a lattice of a semiconductor device such as As, P, B and BF 2 where ions are implanted. The present invention relates to a heat treatment method for reducing defects.

【0002】[0002]

【従来の技術】LSIの半導体基板に素子を形成する方
法として不純物をイオン注入することは注入層の形状の
コントロールがしやすいことから広く用いられている。
しかし所要の深さまでイオンを注入するためには注入イ
オン種、基板結晶面、イオン注入方向、基板表面の状態
に応じたエネルギーを与える必要がある。素子の種類に
より注入深さ、注入量は異なるが、10〜500keV
の高い注入エネルギーが必要となり、必然的に基板内に
格子欠陥が生じることになる。とくにソース、ドレイン
部のように高濃度のイオンを注入した部分では、注入層
はもはや結晶構造を有せず、個々のSi原子の配列が不
規則な非晶質となっている。このような非晶質或は結晶
構造をなしていても格子欠陥を含んだ層は所要の半導体
特性を示さないため、イオン注入後熱処理を施し結晶性
の回復を図っている。これらの技術については特開昭6
3−181418号公報、特開平2−56927号公報
及び特開平3−278525号公報に開示されている。
またイオン注入時にシリコン基板を900℃以上に加熱
する技術も特開昭61−22623号公報に開示されて
いる。
2. Description of the Related Art Ion implantation of impurities is widely used as a method of forming an element on a semiconductor substrate of an LSI because it is easy to control the shape of the implantation layer.
However, in order to implant ions to a required depth, it is necessary to apply energy according to the implanted ion species, substrate crystal plane, ion implantation direction, and substrate surface condition. The implantation depth and dose depend on the type of device, but 10-500 keV
Of high implantation energy, which inevitably results in lattice defects in the substrate. In particular, in the portion where a high concentration of ions is implanted, such as the source and drain portions, the implantation layer no longer has a crystal structure, and the arrangement of individual Si atoms is irregular and amorphous. A layer containing lattice defects does not exhibit the required semiconductor characteristics even if it has such an amorphous or crystalline structure, and therefore heat treatment is performed after the ion implantation to recover the crystallinity. These techniques are disclosed in JP-A-6
It is disclosed in JP-A-3-181418, JP-A-2-56927 and JP-A-3-278525.
Further, a technique of heating a silicon substrate to 900 ° C. or higher at the time of ion implantation is also disclosed in JP-A-61-22623.

【0003】[0003]

【発明が解決しようとする課題】このようにイオン注入
により形成された格子欠陥を熱処理により消滅させる技
術は広く知られており、一定の効果が得られてきた。し
かしLSIの微細化により、より高度な結晶の完全性が
要求されているのに対し、従来から実施されている熱処
理によればシリコン基板にはなお格子欠陥が残留し、半
導体特性の劣化が懸念されることが本発明者らの調査で
明らかになった。一方格子欠陥の消滅には熱処理温度が
高いほど有効であることは自明であるが、素子の微細化
に伴いイオン注入領域を浅くすること、ホットキャリヤ
ー防止のため注入層の形状、不純物濃度を精密にコント
ロールすることが必要となっており、高温熱処理は不純
物の拡散を招くので不都合である。このような理由から
比較的低温での格子欠陥を消滅させる熱処理の出現が待
たれていた。本発明は上述の問題を解決するものであ
り、イオン注入後の熱処理を適切に行ない、イオン注入
部の格子欠陥を大きく低減させる半導体基板の熱処理方
法を提供することを課題とするものである。
Techniques for eliminating the lattice defects formed by ion implantation by heat treatment are widely known, and certain effects have been obtained. However, with the miniaturization of LSIs, a higher degree of crystal perfection is required, whereas according to the heat treatment that has been conventionally performed, lattice defects still remain in the silicon substrate, which may deteriorate semiconductor characteristics. It was revealed by the investigation of the present inventors that this is done. On the other hand, it is obvious that the higher the heat treatment temperature is, the more effective it is to eliminate the lattice defects. However, with the miniaturization of the device, the ion implantation region should be made shallower, and the shape of the implantation layer and the impurity concentration should be precise to prevent hot carriers. Therefore, high temperature heat treatment is disadvantageous because it causes diffusion of impurities. For this reason, the appearance of heat treatment for eliminating lattice defects at a relatively low temperature has been awaited. The present invention solves the above-mentioned problems, and an object of the present invention is to provide a heat treatment method for a semiconductor substrate, which appropriately performs heat treatment after ion implantation and significantly reduces lattice defects in the ion implanted portion.

【0004】[0004]

【課題を解決するための手段】本発明の特徴は低温での
熱処理の後比較的高温での熱処理を行うことによりイオ
ン注入により形成された格子欠陥の低減を図ることにあ
る。イオン注入後の熱処理条件を変えて残留格子欠陥の
状態を広範に調査した結果、熱処理温度が高いほど残留
格子欠陥の密度が減少するが、完全に消滅させることは
困難で、それが表面近くに存在すること、本発明の熱処
理方法によれば格子欠陥を電気特性に影響を与えない深
い位置にコントロールできることを見出した。よって本
発明は、次の方法を採った。すなわち、半導体基板にイ
オンを注入した後600℃を超え800℃以下の温度で
第1の熱処理を行い、引き続き800℃を超え1000
℃未満の温度で第2の熱処理を行うことを特徴とする半
導体基板の熱処理方法である。第2の熱処理を500秒
を超えて行えば好適である。また、第1の熱処理をラン
ピングにより行い、第2の熱処理を500秒を超えて行
ってもよい。第1および第2の熱処理をランプアニール
炉で行うと好適である。
A feature of the present invention is to reduce the lattice defects formed by ion implantation by performing heat treatment at a relatively low temperature after heat treatment at a low temperature. As a result of extensively investigating the state of residual lattice defects by changing the heat treatment conditions after ion implantation, the density of residual lattice defects decreases as the heat treatment temperature increases, but it is difficult to completely eliminate them, and it is difficult to completely eliminate them. It has been found that the existence of the lattice defects can be controlled at a deep position that does not affect the electrical characteristics by the heat treatment method of the present invention. Therefore, the present invention has adopted the following method. That is, after implanting ions into the semiconductor substrate, the first heat treatment is performed at a temperature higher than 600 ° C. and lower than 800 ° C.
A method for heat treating a semiconductor substrate is characterized in that the second heat treatment is performed at a temperature of less than ° C. It is preferable to perform the second heat treatment for more than 500 seconds. Alternatively, the first heat treatment may be performed by ramping and the second heat treatment may be performed for more than 500 seconds. It is preferable to perform the first and second heat treatments in a lamp annealing furnace.

【0005】[0005]

【作用】本発明の請求範囲の数値限定の理由を説明す
る。第1の熱処理温度:600℃以下ではイオン注入に
より非晶質化した領域の結晶化が十分に起きないこと、
逆に800℃を超えると前述のとおり残留格子欠陥が極
表面近傍に残留するような結晶化の過程をとり、本発明
の目的である格子欠陥フリーの極表面層を得ることがで
きない。従って、熱処理温度を600℃を超え800℃
以下とした。第2の熱処理温度:800℃以下の熱処理
では結晶の完全性が十分ではなく、微細な格子欠陥が残
留し、さらにドーパントの電気活性化率が十分ではな
く、所要の電気的特性が得られないこと、1000℃以
上ではドーパントの拡散が顕著になり、意図どおりのド
ーパントの空間的分布が得られないので800℃を超え
1000℃未満とした。第2の熱処理の時間:第2の熱
処理時間が短い場合、イオン注入条件によっては格子欠
陥が完全に消滅しないで残留し、素子の電気特性に影響
する場合がある。500秒以上の熱処理を施せばイオン
注入条件にかかわらず電気特性に影響するような格子欠
陥が残留しないため、500秒以上の熱処理が望まし
い。
The reason for limiting the numerical values of the claims of the present invention will be described. First heat treatment temperature: If the temperature is 600 ° C. or lower, crystallization of the region amorphized by ion implantation does not occur sufficiently,
On the other hand, when the temperature exceeds 800 ° C., the crystallization process in which residual lattice defects remain near the pole surface as described above is taken, and the lattice defect-free pole surface layer, which is the object of the present invention, cannot be obtained. Therefore, if the heat treatment temperature exceeds 600 ℃ and 800 ℃
Below. Second heat treatment temperature: In the heat treatment at 800 ° C. or less, the crystal integrity is not sufficient, fine lattice defects remain, and the electrical activation rate of the dopant is not sufficient, so that the required electrical characteristics cannot be obtained. That is, at 1000 ° C. or higher, the diffusion of the dopant becomes remarkable and the spatial distribution of the dopant as intended cannot be obtained. Second heat treatment time: When the second heat treatment time is short, depending on the ion implantation conditions, the lattice defects do not completely disappear and remain, which may affect the electrical characteristics of the device. If the heat treatment is performed for 500 seconds or longer, lattice defects that affect the electrical characteristics do not remain regardless of the ion implantation conditions. Therefore, the heat treatment for 500 seconds or longer is desirable.

【0006】[0006]

【実施例】P型(100)Si基板表面に熱酸化法によ
りSiO2 膜を11nm厚さに成膜した。基板表面にA
sイオンをエネルギー70keVで5×1015atom
s/cm2 の密度で注入した。電子顕微鏡観察用薄膜試
料作製時の表面保護のためSiON膜を成膜した後、本
発明法である650℃:300秒、980℃:300秒
の熱処理及び比較例として1000℃:30分の熱処理
を施した。透過電子顕微鏡用断面薄膜試料を作製し、残
留格子欠陥の状態を観察した。本発明の熱処理を施した
場合はAで示す表面から100nm深さのみに格子欠陥
が残留するが、比較例(従来熱処理法)ではBで示す1
00nm深さ位置の他にCで示す表面からわずか40n
m深さ位置にも格子欠陥が残留しており、LSI製造プ
ロセスとして不都合であることが分かる。他の熱処理条
件での格子欠陥の残留深さを表1に示す。本実施例はA
sイオン注入の例であるが、B,P,BF2 等所要のト
ランジスタ特性を付与するための他の元素イオン、分子
イオン注入の場合でも前述の熱処理条件の選択により同
様の効果が得られることは明らかである。また本実施例
ではいずれも所定の温度に保持した熱処理炉に基板を挿
入した場合であるが、ランプアニール炉で急速に加熱し
ても事情は変わらない。なお、本実施例ではイオン注入
前に11nm厚の酸化膜を成膜したが薄い膜の有無はイ
オン注入、熱処理による回復挙動に大きくは影響しな
い。
EXAMPLE An SiO 2 film having a thickness of 11 nm was formed on the surface of a P-type (100) Si substrate by a thermal oxidation method. A on the substrate surface
5 × 10 15 atom of s ion with energy of 70 keV
Injection was performed at a density of s / cm 2 . After forming a SiON film for surface protection during the preparation of a thin film sample for electron microscope observation, heat treatment at 650 ° C. for 300 seconds and 980 ° C. for 300 seconds, which is the method of the present invention, and heat treatment at 1000 ° C. for 30 minutes as a comparative example. Was applied. A cross-sectional thin film sample for a transmission electron microscope was prepared and the state of residual lattice defects was observed. When the heat treatment of the present invention is applied, lattice defects remain only at a depth of 100 nm from the surface indicated by A, but in the comparative example (conventional heat treatment method), B indicates 1
Only 40n from the surface indicated by C in addition to the 00nm depth position
It can be seen that lattice defects remain at the m depth position, which is inconvenient for the LSI manufacturing process. Table 1 shows residual depths of lattice defects under other heat treatment conditions. This embodiment is A
This is an example of s ion implantation, but the same effect can be obtained by selecting the above-mentioned heat treatment conditions even in the case of implanting other elemental ions such as B, P, BF 2 and the like for imparting required transistor characteristics, and molecular ion implantation. Is clear. Further, in each of the examples, the substrate was inserted into the heat treatment furnace maintained at a predetermined temperature, but the situation does not change even if the substrate is rapidly heated in the lamp annealing furnace. In this example, an 11 nm-thick oxide film was formed before ion implantation, but the presence or absence of a thin film does not significantly affect the recovery behavior by ion implantation or heat treatment.

【0007】[0007]

【表1】 [Table 1]

【0008】[0008]

【発明の効果】本発明は、LSI製造工程でイオン注入
後の残留格子欠陥の影響を大幅に低減することができる
ので、LSIの生産性の向上に優れた効果を奏する。
According to the present invention, the influence of residual lattice defects after ion implantation can be significantly reduced in the LSI manufacturing process, and therefore, the LSI productivity is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】Si基板表面にAsイオン注入後の断面透過電
子顕微鏡写真である。
FIG. 1 is a cross-section transmission electron microscope photograph after As ion implantation on a Si substrate surface.

【図2】Asイオン注入後、本発明法である650℃:
300秒、980℃:300秒の熱処理を行なった後の
残留格子欠陥の状態を示す断面透過電子顕微鏡写真であ
る。
FIG. 2 shows the method of the present invention at 650 ° C. after As ion implantation:
It is a cross-section transmission electron microscope photograph which shows the state of the residual lattice defect after heat-processing for 300 seconds and 980 degreeC: 300 seconds.

【図3】Asイオン注入後、比較例である1000℃:
30分の熱処理を行なった後の残留格子欠陥の状態を示
す断面透過電子顕微鏡写真である。
FIG. 3 is a comparative example at 1000 ° C. after As ion implantation:
It is a cross-section transmission electron microscope photograph which shows the state of the residual lattice defect after heat processing for 30 minutes.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板にイオンを注入した後600
℃を超え800℃以下の温度で第1の熱処理を行い、引
き続き800℃を超え1000℃未満の温度で第2の熱
処理を行うことを特徴とする半導体基板の熱処理方法。
1. 600 after implanting ions into a semiconductor substrate
A method for heat treating a semiconductor substrate, which comprises performing a first heat treatment at a temperature higher than 800 ° C. and lower than 800 ° C., and then performing a second heat treatment at a temperature higher than 800 ° C. and lower than 1000 ° C.
【請求項2】 該第2の熱処理を500秒を超えて行う
請求項1記載の半導体基板の熱処理方法。
2. The method for heat treating a semiconductor substrate according to claim 1, wherein the second heat treatment is performed for more than 500 seconds.
【請求項3】 該第1の熱処理をランピングにより行い
該第2の熱処理を500秒を超えて行う請求項1記載の
半導体基板の熱処理方法。
3. The method for heat treating a semiconductor substrate according to claim 1, wherein the first heat treatment is performed by ramping, and the second heat treatment is performed for more than 500 seconds.
【請求項4】 該第1および第2の熱処理をランプアニ
ール炉で行う請求項1記載の半導体基板の熱処理方法。
4. The heat treatment method for a semiconductor substrate according to claim 1, wherein the first and second heat treatments are performed in a lamp annealing furnace.
JP21665892A 1992-07-23 1992-07-23 Method for heat-treating semiconductor substrate Withdrawn JPH0645270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21665892A JPH0645270A (en) 1992-07-23 1992-07-23 Method for heat-treating semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21665892A JPH0645270A (en) 1992-07-23 1992-07-23 Method for heat-treating semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH0645270A true JPH0645270A (en) 1994-02-18

Family

ID=16691907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21665892A Withdrawn JPH0645270A (en) 1992-07-23 1992-07-23 Method for heat-treating semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0645270A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349039A (en) * 1999-06-02 2000-12-15 Nec Corp Manufacture of semiconductor device having shallow diffusion layer
JP2001156293A (en) * 1999-09-17 2001-06-08 Matsushita Electronics Industry Corp Manufacturing method for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349039A (en) * 1999-06-02 2000-12-15 Nec Corp Manufacture of semiconductor device having shallow diffusion layer
JP2001156293A (en) * 1999-09-17 2001-06-08 Matsushita Electronics Industry Corp Manufacturing method for semiconductor device

Similar Documents

Publication Publication Date Title
EP0269349B1 (en) Method of making an article comprising a buried SiO2 layer
JP4065661B2 (en) Method for forming a shallow junction in a semiconductor wafer
JPS62501320A (en) Semiconductor with shallow hyper-doped region and its processing method using implanted impurities
JPH08203842A (en) Manufacture of semiconductor device
JPH0777259B2 (en) Method for manufacturing polycrystalline silicon resistor having desired temperature coefficient
JPH0642465B2 (en) Method of forming shallow junction
JP2998330B2 (en) SIMOX substrate and method of manufacturing the same
JPH0645270A (en) Method for heat-treating semiconductor substrate
US4784964A (en) EPI defect reduction using rapid thermal annealing
Lecrosnier Gettering by ion implantation
JP2943369B2 (en) Semiconductor substrate manufacturing method
JPH0964355A (en) Manufacture of semiconductor element
JPH11145146A (en) Semiconductor substrate and its manufacture
US11862477B2 (en) Method for manufacturing semiconductor device having gallium oxide-based semiconductor layer
JP3732472B2 (en) Manufacturing method of MOS transistor
JP2685384B2 (en) Semiconductor substrate manufacturing method
TW201820477A (en) Device forming method
JP2527545B2 (en) Method for manufacturing semiconductor device
JPH05275362A (en) Manufacture of semiconductor device
JP2020155447A (en) Method of forming semiconductor device
JPH03265131A (en) Manufacture of semiconductor device
JPH0689869A (en) Manufacture of semiconductor element
JPH05218051A (en) Method of intrinsic gettering treatment
JPH03139827A (en) Forming method for low resistance layer on silicon by ion implanting of two or more elements having different atomic radii
JPH0729845A (en) Fabrication of semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991005