JP2001156293A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shallow the junction of an extension high-concentartion impurity diffusion layer, preventing a dislocation loop defect layer from being formed in an extension high-concentration impurity diffusion layer and a pocket im purity diffusion layer. SOLUTION: A P-type impurity diffusion layer 103 is formed on the surface of a semiconductor substrate 100, and then a gate electrode 102 is formed on the semiconductor substrate 100 through the intermediary of a gate insulating film 101. Indium ions are implanted using the gate electrode 102 as a mask for the formation of an amorphous layer, and arsenic ions are implanted using the gate electrode 102 as a mask. The semiconductor substrate 100 is thermally treated at 400 to 550 deg.C to turn the amorphous layer to a crystal layer, and then arsenic ions are implanted using the gate electrode 102 and a side wall 107 as a mask. Indium ions and arsenic ions which are implanted are activated, by which an extension high-concentration impurity diffusion layer 105 possessed of a shallow junction, a pocket impurity diffusion layer 106, and a high- concentration impurity diffusion layer 104 possessed of a deep junction are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MIS type semiconductor device having a fine structure capable of realizing ultra-high integration of a semiconductor integrated circuit and operating at high speed and with low power consumption.

[0002]

2. Description of the Related Art With the ultra-high integration of semiconductor integrated circuits,
There is a demand for miniaturization of the MIS transistor, and a MIS transistor having a shallow junction is required for the realization thereof.

FIG. 10 shows a conventional MIS having a shallow junction.
1 shows a cross-sectional structure of a type transistor, in which a gate electrode 3 is formed on a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. On both sides of the gate electrode 3 in the surface portion of the semiconductor substrate 1, that is, in a region serving as a source or a drain, an n-type impurity such as arsenic is diffused and a high-concentration impurity diffusion layer 5 having a deep junction, 5
, An n-type impurity such as arsenic is diffused and has a junction shallower than the high-concentration impurity diffusion layer 5, and an extension high-concentration impurity diffusion layer 6 below the extension high-concentration impurity diffusion layer 6. Positioned pocket impurity diffusion layers 7 are formed by diffusing p-type impurities, for example, boron. Further, a sidewall 8 made of an insulating film is formed on a side surface of the gate electrode 3.

Hereinafter, a method for manufacturing a conventional MIS transistor will be described with reference to FIGS. 11 (a) to 11 (e).

First, as shown in FIG. 11A, a gate electrode 3 made of polysilicon is formed on a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween.

Next, using the gate electrode 3 as a mask, arsenic as an n-type impurity and boron as a p-type impurity are sequentially ion-implanted, and as shown in FIG. 6A and a p-type ion implantation layer 7A are formed respectively.

Next, after depositing a silicon nitride film over the entire surface of the semiconductor substrate 1 at a temperature of about 700 ° C., the silicon nitride film is subjected to anisotropic etching to obtain a structure shown in FIG. As shown in FIG. 5, a sidewall 8 is formed on the side surface of the gate electrode 3.

Next, the gate electrode 2 and the side wall 8
As a mask, arsenic, which is an n-type impurity, is ion-implanted, and a heat treatment is performed at a temperature of about 900 ° C. to 1000 ° C. for about 10 seconds to form an n-type impurity having a deep junction as shown in FIG. -Type high-concentration impurity diffusion layer 5, an n-type extension high-concentration impurity diffusion layer 6 located inside the high-concentration impurity diffusion layer 5 and having a junction shallower than the high-concentration impurity diffusion layer 5, and the extension high-concentration impurity diffusion layer 6. A p-type pocket impurity diffusion layer 7 located below the impurity diffusion layer 6 is formed.

Next, a cobalt film having a thickness of about 10 nm and a titanium nitride film having a thickness of about 20 nm are sequentially deposited on the semiconductor substrate 1 by a sputtering method. A heat treatment is performed for about 10 seconds, and thereafter, the titanium nitride film and the unreacted cobalt film are selectively etched and removed with a mixed solution of sulfuric acid, hydrogen peroxide, and water. Next, at a temperature of about 800 ° C., 10
A heat treatment is performed for about a second, and a cobalt silicide layer 9 having a thickness of about 30 nm is self-aligned on the surface of the gate electrode 3 and the surface of the high-concentration impurity diffusion layer 5 as shown in FIG. It is formed.

In the conventional method of manufacturing a MIS transistor, the arsenic ion implantation energy constituting the n-type ion implantation layer 6A serving as the extension high-concentration impurity diffusion layer 6 is improved in order to improve the driving power of the MIS transistor. To make the junction of the extension high-concentration impurity diffusion layer 6 shallow. Further, in this case, the implantation dose of arsenic ions tends to be increased in order to reduce the parasitic resistance between the source region and the drain region.

[0011]

However, when arsenic ions are implanted with a high implantation dose and a low implantation energy to form an n-type ion implantation layer 6A, a low-temperature heat treatment for forming the sidewalls 8 is performed. The process, that is, the heat treatment at a relatively low temperature of about 700 ° C. causes transient enhanced diffusion (TED) of arsenic, which is an impurity of the n-type ion-implanted layer 6A, and the extension high-concentration impurity diffusion having a shallow junction as designed. There is a problem that the layer 6 cannot be formed. Here, the transient enhanced diffusion is a phenomenon in which an excessively present point defect between lattices and an implanted impurity interact with each other and diffuse, so that the impurity is diffused beyond a diffusion coefficient in a thermal equilibrium state. That means.

FIG. 12 shows the profile of the impurities constituting the extension high-concentration impurity diffusion layer 6 and the pocket impurity diffusion layer 7 in the depth direction (along the line AA 'in FIG. 10). As can be seen from FIG. 12, the distribution of arsenic in the extension high-concentration impurity diffusion layer 6 in the depth direction is deeply diffused due to the excessively accelerated diffusion during the heat treatment. The boron constituting the pocket impurity diffusion layer 7 is also deeply diffused under the influence of the excessively accelerated diffusion, and loses the sharpness of the distribution. As can be seen from FIG. 12, it is difficult to form the extension high-concentration impurity diffusion layer 6 and the pocket impurity diffusion layer 7 which are shallow, steep, and have excellent short-channel characteristics by the conventional method.

In view of the above, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the junction of an extension high-concentration impurity diffusion layer is made shallow and an increase in leak current can be suppressed.

[0014]

In order to achieve the above object, a first method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate electrode on a semiconductor region via a gate insulating film; Implanting heavy ions having a large mass into the region using the gate electrode as a mask to form an amorphous layer in the semiconductor region; implanting a first impurity into the semiconductor region using the gate electrode as a mask; Performing a first heat treatment at a temperature of 400 ° C. to 550 ° C. on the region to restore the amorphous layer to a crystal layer; and performing a second heat treatment on the semiconductor region to reduce the first impurity. A first conductivity type extension high-concentration impurity diffusion layer having a shallow junction that is diffused,
And forming a second-conductivity-type pocket impurity diffusion layer which is located below the extension high-concentration impurity diffusion layer and in which heavy ions are diffused.

According to the first method of manufacturing a semiconductor device, heavy ions forming a pocket impurity diffusion layer are implanted with a large mass to form an amorphous layer in a semiconductor region.
Since the first impurity is ion-implanted, channeling of the first impurity can be prevented. Therefore, the junction of the extension high-concentration impurity diffusion layer can be made shallow, so that miniaturization can be achieved without reducing the driving force of the transistor.

After ion implantation of heavy ions forming the pocket impurity diffusion layer and first impurities forming the extension high-concentration impurity layer, the ion implantation is performed at 400 to 550 ° C.
Heat treatment at a temperature of to recover the crystallinity of the semiconductor region, and then activate the first impurity and heavy ions,
Since the extension high-concentration impurity diffusion layer and the pocket impurity diffusion layer are formed, no amorphous-crystal interface and dislocation loop defect layer are formed on the extension high-concentration impurity diffusion layer and the pocket impurity diffusion layer. For this reason, it is possible to avoid a situation in which impurity atoms are trapped and segregated by the dislocation loop defect layer, so that a leak current due to the dislocation loop defect layer can be reduced.

According to a second method of manufacturing a semiconductor device according to the present invention, a step of forming a gate electrode on a semiconductor region via a gate insulating film and a step of forming heavy ions with a large mass in the semiconductor region using the gate electrode as a mask are performed. Performing a first heat treatment at a high temperature for a short time on the semiconductor region a plurality of times after ion implantation at an implantation dose at which a layer is not formed, and a first impurity in the semiconductor region using the gate electrode as a mask. And a second heat treatment performed on the semiconductor region to diffuse the first impurity, thereby forming a first conductivity type extension high-concentration impurity diffusion layer having a shallow junction, and an extension high-concentration impurity. Forming pocket impurity diffusion layers of the second conductivity type located below the impurity diffusion layers and in which heavy ions are diffused. Eteiru.

According to the second method of manufacturing a semiconductor device, heavy ions constituting the pocket impurity diffusion layer are implanted by dividing the heavy ions having a large mass into an implantation dose that does not form an amorphous layer. Since no amorphous layer is formed, no amorphous crystal interface and thus no dislocation loop defect layer are formed. For this reason, it is possible to avoid a situation in which impurity atoms are trapped and segregated by the dislocation loop defect layer, so that a leak current due to the dislocation loop defect layer can be reduced. As described above, since the dislocation loop defect layer is not formed, the leakage current is reduced, whereby a semiconductor device using heavy ions with a small junction depth and a small junction leakage current can be manufactured.

Although the implantation dose is reduced every time heavy ions are implanted, since the heavy ions are implanted a plurality of times, the impurity concentration of the pocket impurity diffusion layer does not decrease.

Further, since a rapid thermal treatment at a high temperature for a short time is performed every time heavy ions are implanted, damage to the crystal of the semiconductor region due to heavy ion implantation is recovered each time without being accumulated. Can be further reduced.

According to a third method of manufacturing a semiconductor device of the present invention, a gate electrode is formed on a semiconductor region via a gate insulating film, and heavy ions having a large mass are implanted into the semiconductor region using the gate electrode as a mask. Forming an amorphous layer in the semiconductor region; implanting a first impurity in the semiconductor region using the gate electrode as a mask; and implanting an IV in the semiconductor region using the gate electrode as a mask.
Ion implantation of an element of group III to depress the position of the amorphous layer in the depth direction of the substrate, and by performing a second heat treatment on the semiconductor region, the first impurity is diffused to form a shallow junction. A first conductivity type extension high-concentration impurity diffusion layer, and a second high-concentration impurity diffusion layer located below the extension high-concentration impurity diffusion layer, in which heavy ions are diffused.
Forming a conductive type pocket impurity diffusion layer.

According to the third method of manufacturing a semiconductor device, a heavy ion constituting a pocket impurity diffusion layer is ion-implanted to form an amorphous layer in a semiconductor region, and then a first impurity is ion-implanted. Therefore, a situation in which the first impurity is channeled can be prevented. Therefore, the junction of the extension high-concentration impurity diffusion layer can be made shallow, so that miniaturization can be achieved without reducing the driving force of the transistor.

After the heavy ions forming the pocket impurity diffusion layers and the first impurities forming the extension high-concentration impurity diffusion layers are ion-implanted, a group IV element is ion-implanted to position the amorphous layer on the substrate. Push down in the depth direction, and then activate the first impurity and heavy ions to form an extension high concentration impurity diffusion layer and a pocket impurity diffusion layer. No interface between the amorphous crystal and the dislocation loop defect layer is formed. Therefore, it is possible to avoid a situation in which the impurity atoms segregate in the dislocation loop defect layer, and thus it is possible to reduce the leak current.

A fourth method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate electrode on a semiconductor region via a gate insulating film; After performing ion implantation at an implantation dose at which a layer is not formed, and performing a heat treatment at a high temperature for a short time on the semiconductor region a plurality of times, the first conductive type extension high concentration in which heavy ions are diffused. A step of forming an impurity diffusion layer, a step of forming a sidewall on the side surface of the gate electrode, and a step of ion-implanting an impurity into the semiconductor region using the gate electrode and the sidewall as a mask, and activating the impurity to increase the extension height. The first conductivity type, which is located outside the impurity diffusion layer and has a deep junction where impurities are diffused and has a deep junction. And a step of forming a degree impurity diffusion layer.

According to the fourth method for manufacturing a semiconductor device, heavy ions constituting the extension high-concentration impurity diffusion layer are ion-implanted at an implantation dose such that an amorphous layer is not formed. Since it is not formed, the amorphous layer-crystal interface and thus the dislocation loop defect layer waveform are not affected. For this reason, it is possible to avoid a situation in which the heavy ions are captured by the dislocation loop defect layer and segregated, so that the leak current can be reduced. As described above, since the dislocation loop defect layer is not formed, the leakage current is reduced, whereby a semiconductor device using heavy ions with a small junction depth and a small junction leakage current can be manufactured.

Although the implantation dose is reduced each time heavy ions are implanted, since the heavy ions are implanted a plurality of times, the impurity concentration of the pocket impurity diffusion layer does not decrease.

Further, since a rapid thermal treatment at a high temperature for a short time is performed every time heavy ions are implanted, damage to the crystal of the semiconductor region due to heavy ion implantation is recovered each time without being accumulated. Can be further reduced.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a method for manufacturing a MIS transistor according to a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c) and 2 (a) to 2 (a) to 2 (a).
This will be described with reference to FIG.

First, as shown in FIG. 1A, a p-type impurity such as indium ion is implanted into a semiconductor substrate 100 made of p-type silicon at an implantation energy of 200 keV and an implantation dose of about 1 × 10 ¹² / cm ^2. Ion implantation. Immediately after the ion implantation, the semiconductor substrate 100 is heated to 100 ° C.
The first heat treatment (high-speed heat treatment: RTA) in which the temperature is raised to a high temperature of 950 to 1050 ° C. at a rate of 950 / sec and held at this temperature for a short time of about 1 to 10 seconds, is performed. Becomes a channel region on the surface of
A type impurity diffusion layer 103 is formed.

Next, as shown in FIG. 1B, a polysilicon film having a thickness of about 250 nm is formed on a semiconductor substrate 100 via a gate insulating film 101 having a thickness of about 2.5 nm. Alternatively, the gate electrode 102 made of polymetal is formed.

Next, the gate electrode 10 is formed on the semiconductor substrate 100.
2 as a mask, a p-type impurity such as indium ion is implanted at an implantation energy of 15 keV and 1 × 10 ¹⁴ / cm
Ion implantation is performed at an implantation dose of about ² . This implantation of indium ions is for forming a pocket impurity layer, but an amorphous layer is formed in the semiconductor substrate 100 by implantation of heavy ions having a large mass such as indium ions. Thereafter, an implantation energy of 10keV impurity such as arsenic ions of an n-type and 5 × 10 ¹⁴ /
Ion implantation is performed at an implantation dose of about cm ² . This implantation of arsenic ions is for forming an extension high concentration impurity layer.

In this manner, as shown in FIG. 1C, an n-type extension high-concentration impurity layer having a shallow junction doped with arsenic ions is formed in a region serving as a source region or a drain of the semiconductor substrate 100. A p-type pocket impurity layer 106A doped with indium ions is formed below 105A and the extension high concentration impurity layer 105A. Here, the extension high concentration impurity layer 105A or the pocket impurity layer 106
The reason why it is referred to as A and not as an impurity diffusion layer is that these impurity layers have not been subjected to a heat treatment yet.

Next, with respect to the semiconductor substrate 100,
After the second heat treatment at an extremely low temperature of 550 ° C. is performed to change the amorphous layer formed in the semiconductor substrate 100 into a crystal layer (after recovering the crystallinity of the semiconductor substrate 100), the heat treatment is performed at 100 ° C. / 950-
By performing a third heat treatment (RTA) by raising the temperature to a high temperature of 1050 ° C. and holding the temperature for a short time of about 1 to 10 seconds, as shown in FIG.
The n-type extension high-concentration impurity diffusion layer 105 (formed by subjecting the extension high-concentration impurity layer 105A to a heat treatment) and having a shallow junction formed by diffusing arsenic ions into regions serving as source and drain A p-type pocket impurity diffusion layer 106 (formed by subjecting the pocket impurity layer 106A to heat treatment) is formed below the extension high-concentration impurity diffusion layer 105 and in which indium ions are diffused.

Next, after depositing a silicon nitride film having a thickness of, for example, 50 nm over the entire surface of the semiconductor substrate 100, the silicon nitride film is subjected to anisotropic etching to obtain a structure shown in FIG. As shown in b), a sidewall 107 is formed on the side surface of the gate electrode 102. still,
A sidewall 107 made of a silicon oxide film may be formed instead of the silicon nitride film.

Next, the gate electrode 10 is formed on the semiconductor substrate 100.
After implanting an n-type impurity, for example, arsenic ion with an implantation energy of 30 keV and an implantation dose of about 3 × 10 ¹⁵ / cm ² by using the mask 2 and the sidewall 107 as a mask, the temperature is raised to 100 to 150 ° C./sec. 950 at the rate
By performing a fourth heat treatment (RTA) of raising the temperature to a high temperature of ５０1050 ° C. and holding the temperature for a short time of about 1 to 10 seconds, arsenic ions are formed in the source region and the drain region of the semiconductor substrate 100. An n-type high-concentration impurity diffusion layer 104 having a diffused and deep junction is formed.

According to the first embodiment, indium ions for forming the pocket impurity diffusion layer 106 are 1 ×
Ion implantation at an implantation dose of about 10 ¹⁴ / cm ² ,
Since arsenic ions are implanted after the formation of the amorphous layer in the semiconductor substrate 100, it is possible to prevent the arsenic ions from largely entering the depth direction of the substrate due to channeling.

According to the first embodiment, in order to form the pocket impurity diffusion layer 106, indium ions, which are heavy ions having a large mass number, are used, and ion implantation for forming the pocket impurity diffusion layer 106 is performed. Is performed before the ion implantation for forming the extension high-concentration impurity diffusion layer 105, the ion implantation for forming the pocket impurity diffusion layer 106 has the effect of preliminarily amorphizing the semiconductor substrate 100 (pre-amorphization). Effect). Therefore, it is not necessary to separately perform ion implantation for pre-amorphization for preventing channeling.

The junction between the extension high-concentration impurity layer 105A and the extension high-concentration impurity diffusion layer 105 can be made shallower by the pre-amorphization effect by ion implantation of heavy ions.

The implantation dose at which an amorphous layer can be formed by indium ion implantation is 5 × 10 ¹³ /
Since it is not less than cm ² , the ion implantation for forming the pocket impurity diffusion layer 106 can also serve as the step of forming the amorphous layer by ion-implanting indium having the implantation dose or more.

After the implantation of indium ions and arsenic ions, a second heat treatment at an extremely low temperature is performed to restore the crystallinity of the semiconductor substrate 100, and then a third heat treatment (RTA) is performed to extend the semiconductor substrate 100. Since the high-concentration impurity diffusion layer 105 and the pocket impurity diffusion layer 106 are formed, the dislocation loop defect layer formed at the amorphous crystal interface formed immediately after the ion implantation for forming the pocket impurity layer 106A is suppressed. . By suppressing the formation of the dislocation loop defect layer, it is possible to suppress the impurity atoms from being captured and precipitated by the dislocation loop defect layer. In addition, suppressing the formation of a dislocation loop defect layer can suppress a junction leak current caused by a dislocation loop. Therefore, a semiconductor device with a small junction depth and a small junction leakage current can be manufactured. it can.

Further, in order to form the extension high-concentration impurity diffusion layer 105 and the pocket impurity diffusion layer 106, the third heat treatment is performed at high speed and rapidly after the heat treatment at a very low temperature. Sufficient activation can be increased. By performing high-temperature and rapid heat treatment, excessively accelerated diffusion of impurity ions is suppressed, the junction depth is kept small, and the activation is enhanced.However, immediately after the implantation of a high dose of indium ions, When a high-temperature and rapid heat treatment is applied, formation of a dislocation loop defect layer is promoted and precipitation of indium on the dislocation loop defect layer increases. Thus, as in the first embodiment, the second heat treatment at a very low temperature is followed by the third heat treatment at a high temperature and a rapid temperature, thereby forming a dislocation loop defect layer and an indium dislocation loop defect layer. It is possible to enhance the activation of the diffusion layer made of indium or other impurities while suppressing the precipitation of the diffusion layer.

In addition, indium ions, which are heavy ions having a large mass, are implanted into the semiconductor substrate 100 to form the p-type impurity diffusion layer 103 serving as a channel region. Since the impurity concentration is low, the mobility of the carrier concentration does not decrease, and a steep impurity concentration can be obtained in a region slightly deeper than the surface of the substrate in the channel region, so that the transistor can be miniaturized without reducing the driving force of the transistor. Can be planned.

Further, since heat treatment (RTA) is performed immediately after the implantation of indium ions having a large mass to form the p-type impurity diffusion layer 103, damage to the crystal of the semiconductor substrate 100 caused by the implantation of indium ions is promptly reduced. You can recover.

In the first embodiment, indium ions are implanted into the p-type impurity diffusion layer 103 serving as a channel region. Instead, boron ions or both boron ions and indium ions are implanted. Ion implantation may be performed.

Although indium ions are used for forming the pocket impurity diffusion layer 106, ions of the same group 3B element having a larger mass number than indium may be used instead.

Further, the third heat treatment (the step shown in FIG. 2A) may be omitted. In this case, the n-type extension high-concentration impurity diffusion layer 105, the p-type pocket impurity diffusion layer 106, and the high-concentration impurity diffusion layer 104 are simultaneously formed by the fourth heat treatment (step shown in FIG. 2C). It is formed.

In the first embodiment, the n-channel MI
Although the transistor is an S-type transistor, a p-channel MIS transistor may be used instead. In the case of a p-channel MIS transistor, the pocket impurity diffusion layer 106
5B which is heavier than antimony ion such as antimony ion or bismuth ion as impurity ion
Group element ions can be used.

(Second Embodiment) Hereinafter, a method for manufacturing a MIS transistor according to a second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (c) and 4 (a) to 4 (c). It will be described with reference to FIG.

First, as shown in FIG. 3A, a p-type impurity such as indium ion is implanted into a p-type semiconductor substrate 200 at an implantation energy of 200 keV and at 1 × 10 ¹² / c.
Ion implantation is performed at an implantation dose of about m ² . Immediately after the ion implantation, the temperature of the semiconductor substrate 200 is increased to a high temperature of 950 to 1050 ° C. at a rate of 100 ° C./sec.
The first heat treatment (R
By performing TA), a p-type impurity diffusion layer 203 serving as a channel region is formed on the surface of the semiconductor substrate 200.

Next, as shown in FIG. 3B, a polysilicon film having a thickness of about 250 nm is formed on the semiconductor substrate 200 via a gate insulating film 201 having a thickness of about 2.5 nm. Alternatively, a gate electrode 202 made of polymetal is formed.

Next, the gate electrode 20 is formed on the semiconductor substrate 200.
2 as a mask, a p-type impurity such as indium ion is implanted at an implantation energy of 15 keV and 1 × 10 ¹³ / cm
After ion implantation at an implantation dose of ² or less, the semiconductor substrate 200 is heated at a rate of 100 ° C./sec.
A second heat treatment (RTA) is performed in which the temperature is raised to a high temperature of ° C and the temperature is kept for a short time of about 1 to 10 seconds at the temperature. By repeating the ion implantation step and the heat treatment step, for example, a total of eight times, pocket impurity diffusion in which indium ions are diffused into the source region and the drain region on the surface of the semiconductor substrate 200 as shown in FIG. A layer 206 is formed.

Although the number of times of repeating the ion implantation step and the heat treatment step is not limited to eight, the ion implantation with the implantation dose divided so as to be small enough not to form an amorphous layer by indium ion implantation is performed plural times. In order to obtain a predetermined impurity concentration. Further, it is necessary to perform high-temperature and short-time heat treatment immediately after each of the plurality of ion implantations. Also, for convenience,
A plurality of heat treatments, for example, a total of eight heat treatments are collectively referred to as a second heat treatment.

Next, the gate electrode 20 is formed on the semiconductor substrate 200.
2 as a mask, n-type impurities such as arsenic ions
After ion implantation at an implantation energy of 0 keV and an implantation dose of about 5 × 10 ¹⁴ / cm ² , the semiconductor substrate 200
Was heated to a high temperature of 950 to 1050 ° C. at a heating rate of 100 ° C./second, and a third heat treatment (RTA) was performed at this temperature for a short period of time of about 1 to 10 seconds to obtain FIG.
As shown in (a), an extension high concentration impurity diffusion layer 205 having a shallow junction formed by arsenic ions being diffused is formed on the surface of the pocket impurity diffusion layer 206.

Next, after depositing a silicon nitride film having a thickness of, for example, 50 nm over the entire surface of the semiconductor substrate 200, the silicon nitride film is subjected to anisotropic etching to obtain a structure shown in FIG. As shown in b), a sidewall 207 is formed on the side surface of the gate electrode 202. still,
A sidewall 207 made of a silicon oxide film may be formed instead of the silicon nitride film.

Next, the gate electrode 20 is formed on the semiconductor substrate 200.
After implanting an n-type impurity, for example, arsenic ion with an implantation energy of 30 keV and an implantation dose of about 3 × 10 ¹⁵ / cm ² using the mask 2 and the sidewall 207 as a mask, the temperature is increased at a rate of 100 ° C./sec. 950-105
By raising the temperature to a high temperature of 0 ° C. and performing a fourth heat treatment (RTA) at the temperature for a short period of time of about 1 to 10 seconds, arsenic ions are formed in the source region and the drain region of the semiconductor substrate 200. N diffused and have a deep junction
A high-concentration impurity diffusion layer 204 is formed.

According to the second embodiment, in the step of implanting indium ions, the predetermined implantation dose is 1 × 10 ¹³ / c.
Since the low dose ion implantation divided into the implantation dose of m ² or less is performed in a plurality of times, the semiconductor substrate 200
Since no amorphous layer is formed on the substrate, no amorphous-crystal interface is formed. In addition, since a dislocation loop defect layer formed near the amorphous-crystal interface is not formed, a situation in which impurity atoms are captured by the dislocation loop defect layer and segregated can be avoided. Also,
Since a dislocation loop defect layer is not formed, a leakage current is reduced, whereby a semiconductor device using heavy ions with a small junction depth and a small junction leakage current can be manufactured.

Since a rapid thermal treatment is performed every time indium ions are implanted at a divided low dose, damage to the crystal of the semiconductor substrate 200 due to indium ion implantation can be recovered each time. Therefore, it is possible to prevent the semiconductor substrate 200 from becoming amorphous by accumulating implantation damage every time ion implantation is performed by dividing a predetermined dose amount into a plurality of times. In addition, since the damage is recovered every ion implantation, the crystal defects included in the crystal layer (the layer that is not made amorphous) are also reduced, so that the leak current can be further reduced.

Since a large amount of indium ions are implanted into the semiconductor substrate 200 to form the p-type impurity diffusion layer 203 serving as a channel region, the impurity concentration is low in a region of the channel region closest to the substrate surface. Therefore, the mobility of carriers does not decrease, and a sharp impurity concentration can be obtained in a region slightly deeper than the surface of the substrate in the channel region, so that the transistor can be miniaturized without reducing the driving force of the transistor.

Since heat treatment (RTA) is performed immediately after the implantation of indium ions having a large mass to form the p-type impurity diffusion layer 203, damage to the crystal of the semiconductor substrate 200 due to the implantation of indium ions is caused. Can be recovered.

In the second embodiment, indium ions are implanted into the impurity diffusion layer 203 serving as a channel region. Instead, boron ions or both boron ions and indium ions are implanted. You may.

Further, the third heat treatment (step shown in FIG. 4A) may be omitted. In this case, the n-type extension high concentration impurity diffusion layer 205 and the high concentration impurity diffusion layer 204 are simultaneously formed by the fourth heat treatment (step shown in FIG. 4C).

The pocket impurity diffusion layer 206 has
Although indium was used as the impurity ions, ions of the same group 3B element having a larger mass number than indium may be used instead.

In the second embodiment, the n-channel MI
Although the transistor is an S-type transistor, a p-channel MIS transistor may be used instead. In the case of a p-channel MIS transistor, the pocket impurity diffusion layer 206
It is preferable to implant antimony ions as impurity ions.

(Third Embodiment) Hereinafter, a method of manufacturing a MIS transistor according to a third embodiment of the present invention will be described with reference to FIGS. 5 (a) to 5 (d) and FIGS. 6 (a) to 6 (c). It will be described with reference to FIG.

First, as shown in FIG. 5A, a p-type impurity such as indium ion is implanted into a semiconductor substrate 300 made of p-type silicon at an implantation energy of 200 keV and an implantation dose of about 1 × 10 ¹² / cm ^2. Ion implantation. Immediately after the ion implantation, the semiconductor substrate 300 is heated to 100 ° C.
The temperature is raised to a high temperature of 950 to 1050 ° C. at a temperature rising rate of 950 ° C./sec, and the temperature is kept at this temperature for a short time of about 1 to 10 seconds.
By performing the second heat treatment (RTA), a p-type impurity diffusion layer 303 serving as a channel region is formed on the surface of semiconductor substrate 300.

Next, as shown in FIG. 5B, a polysilicon film having a thickness of about 250 nm is formed on the semiconductor substrate 300 via a gate insulating film 301 having a thickness of about 2.5 nm. Alternatively, a gate electrode 302 made of polymetal is formed.

Next, the gate electrode 30 is formed on the semiconductor substrate 300.
2 as a mask, a p-type impurity such as indium ion is implanted at an implantation energy of 15 keV and 1 × 10 ¹⁴ / cm
Ion implantation is performed at an implantation dose of about ² (1 × 10 ¹⁶ / cm ² or less) to form an amorphous layer in the semiconductor substrate 300, and then an n-type impurity is formed on the semiconductor substrate 300 using the gate electrode 302 as a mask. For example, 10 ke of arsenic ion
As shown in FIG. 5C, ions are implanted at an implantation energy of V and an implantation dose of about 5 × 10 ¹⁴ / cm ² .
In regions that become the source and the drain of the semiconductor substrate 300,
An n-type extension high-concentration impurity layer 305A doped with arsenic ions and having a shallow junction and a p-type pocket impurity layer 306A which is located below the extension high-concentration impurity layer 405A and doped with indium ions are formed. I do.

Next, in the step shown in FIG.
Germanium ions are implanted at an implantation energy of 150 keV and an implantation dose of about 1 × 10 ¹⁶ / cm ² . By doing so, the amorphous layer formed in the semiconductor substrate 300 is pushed down in the depth direction of the substrate, so that the amorphous crystal interface is replaced with the amorphous crystal interface (1) as shown by a white arrow in FIG. ) Position to the amorphous-crystal interface
It moves to the position (2), that is, in the substrate depth direction. The position of the amorphous-crystal interface (2) is pushed down in the depth direction of the substrate to a position deeper than a depletion layer formed near the junction between the high-concentration impurity diffusion layer 304 formed later and the substrate. I have. As a result, amorphous
Even if a dislocation loop defect layer is formed at the crystal interface, the dislocation loop defect layer is located at a position unrelated to the high-concentration impurity diffusion layer 304 serving as a source / drain. The leakage current flowing through the substrate does not increase.

Next, the temperature of the semiconductor substrate 300 is raised to a high temperature of 950 to 1050 ° C. at a rate of about 100 ° C./second, and the semiconductor substrate 300 is kept at that temperature for a short time of about 1 to 10 seconds.
By performing the second heat treatment (RTA), FIG.
As shown in (a), an n-type extension high-concentration impurity diffusion layer 305 having a shallow junction and a p-type extension layer 305 located below the extension high-concentration impurity diffusion layer 305 are formed in the source region and the drain region of the semiconductor substrate 300. Is formed.

Next, after depositing a silicon nitride film having a thickness of, for example, 50 nm over the entire surface of the semiconductor substrate 300, the silicon nitride film is subjected to anisotropic etching to obtain a structure shown in FIG. As shown in b), a sidewall 307 is formed on the side surface of the gate electrode 302. still,
Instead of the silicon nitride film, a sidewall 307 made of a silicon oxide film may be formed.

Next, using the gate electrode 302 and the side wall 307 as a mask, an n-type impurity such as arsenic ion is implanted at an implantation energy of 30 keV and 3 × 10 ¹⁵ / c.
After ion implantation at an implantation dose of about m ² ,
The temperature is raised to a high temperature of 950 to 1050 ° C. at a heating rate of / sec, and the temperature is kept for a short time of about 1 to 10 seconds at the third temperature.
By performing the second heat treatment (RTA), an n-type high-concentration impurity diffusion layer 304 having a deep junction in the source region and the drain region of the semiconductor substrate 300 is formed.

According to the third embodiment, indium ions for forming the pocket impurity diffusion layer 306 are 1 ×
Ion implantation at an implantation dose of about 10 ¹⁴ / cm ² ,
Since arsenic ions are implanted after the formation of the amorphous layer in the semiconductor substrate 300, channeling of the arsenic ions can be prevented. In the third embodiment, in order to form the pocket impurity diffusion layer 306, an effect of using a large mass number of indium ions to previously amorphize the semiconductor substrate 300 (amorphization effect) is included. Therefore, there is no need to separately perform an implantation step for pre-amorphization.

Further, the junction of the extension high-concentration impurity layer 105A and, consequently, the extension high-concentration impurity diffusion layer 105 can be made shallower by the preamorphization effect accompanying the heavy ion implantation for forming the pocket impurity diffusion layer 306.

The implantation dose for forming an amorphous layer by indium ion implantation is 5 × 10
¹³ / cm ² or more (1 × 10 ¹⁶ / cm ² or less) may be used.

After the implantation of indium ions and arsenic ions, germanium ions are implanted to push down the amorphous layer formed in the semiconductor substrate 300 in the depth direction of the substrate, and then a second heat treatment (RTA) is performed. Is performed to form the extension high-concentration impurity diffusion layer 305 and the pocket impurity diffusion layer 306, heat treatment can be performed in a state where the interface between the amorphous crystal and the transistor has an electrical influence on the transistor. For this reason, even if rapid heat treatment is performed in the presence of the amorphous-crystal interface, the dislocation loop defect layer is formed at a position away from the vicinity of the junction, so that the leakage current is suppressed. Further, since the dislocation loop defect layer exists at a position deeply distant from the high indium concentration region, the situation where indium ions are deposited on the dislocation loop defect layer is also suppressed.

It should be noted that as ions for pushing down the amorphous layer formed in the semiconductor substrate 300 in the depth direction of the substrate, ions of a group IV element such as silicon ions may be used instead of germanium ions. . When silicon ions are used, it is preferable to perform ion implantation at an implantation energy of 120 keV and an implantation dose of about 1 × 10 ¹⁶ / cm ² .

As described above, when the group IV element is ion-implanted, the semiconductor substrate 300 becomes p-type or n-type and the source region or the drain region is adversely affected because the dopant is electrically neutral. Can be avoided.

According to the third embodiment, the second heat treatment for forming the extension high-concentration impurity diffusion layer 305 and the pocket impurity diffusion layer 306 is a rapid heat treatment, so that the activity of arsenic ions and indium ions is reduced. Since the rate of conversion can be increased and the transient accelerated diffusion of arsenic ions can be prevented, the junction of the extension high-concentration impurity diffusion layer 305 can be made shallower.

Since a large amount of indium ions are implanted into the semiconductor substrate 300 to form the p-type impurity diffusion layer 303 serving as a channel region, the impurity concentration is low in a region of the channel region closest to the substrate surface. Therefore, the mobility of carriers does not decrease, and a sharp impurity concentration can be obtained in a region slightly deeper than the surface of the substrate in the channel region, so that the transistor can be miniaturized without reducing the driving force of the transistor.

Since the heat treatment (RTA) is performed immediately after the implantation of indium ions having a large mass to form the p-type impurity diffusion layer 303, damage to the crystal of the semiconductor substrate 300 due to the implantation of the indium ions. Can be recovered.

In the third embodiment, indium ions are implanted into the p-type impurity diffusion layer 303 serving as a channel region. Instead, boron ions or both boron ions and indium ions are implanted. Ion implantation may be performed.

The pocket impurity diffusion layer 306 has
Although indium was used as the impurity ions, ions of the same group 3B element having a larger mass number than indium may be used instead.

Further, the second heat treatment (the step shown in FIG. 6A) may be omitted. In this case, the n-type extension high-concentration impurity diffusion layer 305, the p-type pocket impurity diffusion layer 306, and the high-concentration impurity diffusion layer 304 are simultaneously formed by the third heat treatment (step shown in FIG. 6C). It is formed.

In the third embodiment, the n-channel MI
Although the transistor is an S-type transistor, a p-channel MIS transistor may be used instead. In the case of a p-channel MIS transistor, the pocket impurity diffusion layer 306
As the impurity ions, antimony ions or ions of a 5B group element having a larger mass number than antimony ions can be used.

(Fourth Embodiment) Hereinafter, a method of manufacturing a MIS transistor according to a fourth embodiment of the present invention will be described with reference to FIGS. 8A to 8C and FIGS. 9A and 9B. It will be described with reference to FIG.

First, as shown in FIG. 8A, an n-type impurity such as arsenic ion
After ion implantation at an implantation energy of 30 keV and an implantation dose of about 1 × 10 ¹² / cm ² , for example, phosphorus ions are implanted to form an n-type well region 400a.
An implantation energy of 60 keV, an implantation dose of 4 × 10 ¹² / cm ² , an implantation energy of 540 keV and 1
Ion implantation is performed at an implantation dose of × 10 ¹³ / cm ² .

Immediately after the ion implantation, the temperature of the semiconductor substrate 400 is raised to a high temperature of 950 to 1050 ° C. at a rate of 100 ° C./second, and the semiconductor substrate 400 is kept at the temperature for a short period of time of about 1 to 10 seconds for By performing the second heat treatment (RTA),
An n-type impurity diffusion layer 408 serving as a channel region and an n-type well region 400a are formed on the surface of the semiconductor substrate 400.

Next, as shown in FIG. 8B, a polysilicon film having a thickness of about 250 nm is formed on a semiconductor substrate 400 via a gate insulating film 401 having a thickness of about 2.5 nm. Alternatively, a gate electrode 402 made of polymetal is formed.

Next, the gate electrode 40 is formed on the semiconductor substrate 400.
2 as a mask, a p-type impurity such as indium ion is implanted at an implantation energy of 5 keV and 1 × 10 ¹³ / cm ^2.
After ion implantation at an implantation dose of about 100 ° C./sec, the temperature is raised to a high temperature of 950 to 1050 ° C. at a rate of about 100 ° C./sec.
A second heat treatment (RTA) is performed. By repeating the ion implantation step and the heat treatment step, for example, a total of 20 times, as shown in FIG. 8C, indium ions are diffused into the source region and the drain region on the surface of the semiconductor substrate 400 to form a shallow junction. A p-type extension high concentration impurity diffusion layer 409 is formed.

Although the number of times of repeating the ion implantation step and the heat treatment step is not limited to 20, the ion implantation with the implantation dose divided so small that an amorphous layer is not formed by implantation of indium ions may be performed a plurality of times. In order to obtain a predetermined impurity concentration. Further, it is necessary to perform high-temperature and short-time heat treatment immediately after each of the plurality of ion implantations. For convenience, a plurality of heat treatments, for example, a total of 20 heat treatments are collectively referred to as a second heat treatment.

Next, after depositing a silicon nitride film having a thickness of, for example, 50 nm over the entire surface of the semiconductor substrate 400, the silicon nitride film is subjected to anisotropic etching to obtain a structure shown in FIG. As shown in a), a sidewall 407 is formed on the side surface of the gate electrode 402. still,
Instead of the silicon nitride film, a sidewall 407 made of a silicon oxide film may be formed.

Next, using the gate electrode 402 and the sidewall 407 as a mask, a p-type impurity such as boron ion is implanted at an implantation energy of 5 keV and 3 × 10 ¹⁵ / c.
After ion implantation at an implantation dose of about m ² ,
/ Second at a temperature rising rate of 950 to 1050 ° C.
By performing the second heat treatment (RTA), FIG.
As shown in (b), a p-type high-concentration impurity diffusion layer 410 having a deep junction in the source region and the drain region of the semiconductor substrate 400 is formed.

According to the fourth embodiment, in the step of implanting indium ions, the predetermined implantation dose is 1 × 10 ¹³ / c.
Since the low dose ion implantation divided into the implantation dose of m ² or less is performed in a plurality of times, the semiconductor substrate 400
No amorphous layer is formed on the extension, and no amorphous-crystal interface is formed on the extension high-concentration impurity layer 409A. Thereby, 5 × 10 ¹³ /
Since the dislocation loop defect layer is not formed near the amorphous crystal interface due to the ion implantation of indium ions having a dose larger than cm ^2, it is possible to avoid a situation in which impurity atoms are captured by the dislocation loop defect layer and segregated. . Thus, the extension high-concentration impurity diffusion layer 409 made of indium can be formed.

In addition, since the dislocation loop defect layer is not formed, the leakage current is reduced, whereby a semiconductor device using heavy ions, having a small junction depth and a small junction leakage current can be manufactured.

Further, since the rapid heat treatment is performed each time the indium ions are divided and implanted, damage to the crystal of the semiconductor substrate 400 due to the implantation of indium ions can be recovered each time. Therefore, it is possible to prevent the semiconductor substrate 200 from becoming amorphous by accumulating implantation damage every time ion implantation is performed by dividing a predetermined dose amount into a plurality of times. In addition, since the damage is recovered for each ion, the crystal defects included in the crystal layer (the layer that is not made amorphous) are also reduced, so that the leak current can be further reduced.

In the fourth embodiment, arsenic ions are implanted into the n-type impurity diffusion layer 403 serving as a channel region. Alternatively, antimony ions may be implanted.

Although indium is used for the extension high-concentration impurity diffusion layer 409, ions of the same group 3B element having a larger mass number than indium may be used instead.

In the fourth embodiment, the p-channel MI
Although an S-type transistor, an n-channel MIS-type transistor may be used instead. In the case of an n-channel MIS transistor, antimony ions or ions of a 5B group having a larger mass number than antimony may be used as the impurity ions in the extension high-concentration impurity diffusion layer 409.

[0099]

According to the first method for manufacturing a semiconductor device,
Since channeling of the first impurity can be prevented, the junction of the extension high-concentration impurity diffusion layer can be made shallower, so that miniaturization can be achieved without reducing the driving force of the transistor.

After the crystallinity of the semiconductor region is restored, the first impurity and heavy ions are activated to form the extension high concentration impurity diffusion layer and the pocket impurity diffusion layer. No amorphous crystal interface and no dislocation loop defect layer are formed in the pocket impurity diffusion layer. For this reason, it is possible to avoid a situation in which impurity atoms are trapped and segregated in the dislocation loop defect layer, so that a leak current due to the dislocation loop defect layer can be reduced.

According to the second method for manufacturing a semiconductor device, since no amorphous layer is formed in the semiconductor region, no amorphous-crystal interface and thus no dislocation loop defect layer are formed. Therefore, impurity atoms are captured by the dislocation loop defect layer and segregated. Can be avoided. For this reason, the leakage current due to the dislocation loop defect layer can be reduced, so that a semiconductor device using heavy ions with a small junction depth and a small junction leakage current can be manufactured.

In addition, since a rapid thermal treatment at a high temperature for a short time is performed every time heavy ions are implanted, damage to the crystal of the semiconductor region caused by heavy ion implantation is recovered each time without being accumulated. Can be further reduced.

According to the third method of manufacturing a semiconductor device, it is possible to prevent channeling of the first impurity, so that the junction of the extension high-concentration impurity diffusion layer can be made shallower, so that the driving force of the transistor can be reduced. Can be achieved without reducing the size.

After the group IV element is ion-implanted to lower the position of the amorphous layer in the depth direction of the substrate, the first
In order to activate the impurities and heavy ions, and to form an extension high-concentration impurity diffusion layer and a pocket impurity diffusion layer, the extension high-concentration impurity diffusion layer and the pocket impurity diffusion layer have an amorphous-crystal interface and a dislocation loop defect layer. Not formed. For this reason,
Since a situation in which impurity atoms are trapped and segregated by the dislocation loop defect layer can be avoided, a leak current caused by the dislocation loop defect layer can be reduced.

According to the fourth method for manufacturing a semiconductor device, in the indium ion implantation step, a low-dose ion implantation in which a predetermined implantation dose is divided is performed a plurality of times. Since no layer is formed, no amorphous-crystal interface is formed in the extension high-concentration impurity layer. As a result, a dislocation loop defect layer formed near the amorphous-crystal interface is not formed, so that a situation in which impurity atoms are captured by the dislocation loop defect layer and segregated can be avoided.

Since the dislocation loop defect layer is not formed, the leakage current is reduced.
A semiconductor device having a small junction depth and a small junction leakage current can be manufactured.

Since a rapid heat treatment is performed each time indium ions are divided and implanted, damage to the semiconductor region due to indium ion implantation is recovered each time. Accordingly, it is possible to prevent the semiconductor region from becoming amorphous by accumulating implantation damage each time the predetermined implantation dose is divided and implanted in a plurality of times. In addition, since the damage is recovered every time the implantation is performed, the crystal defects themselves included in the crystal layer (the layer that is not made amorphous) are also reduced, so that the leak current can be further reduced.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views showing steps of a method for manufacturing a MIS transistor according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to a second embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to a second embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to a third embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a state where an amorphous crystal interface formed in a semiconductor region moves in a substrate depth direction in a third embodiment of the present invention.

FIGS. 8A to 8C are cross-sectional views illustrating steps of a method for manufacturing a MIS transistor according to a fourth embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional views illustrating respective steps of a method for manufacturing a MIS transistor according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional MIS transistor.

FIGS. 11A to 11E are cross-sectional views showing steps of a conventional method for manufacturing a MIS transistor.

FIG. 12 is a diagram showing a relationship between a depth from a substrate surface and an impurity concentration in a conventional MIS transistor.

[Explanation of symbols]

 Reference Signs List 100 semiconductor substrate 101 gate insulating film 102 gate electrode 103 p-type impurity diffusion layer 104 n-type high-concentration impurity diffusion layer 105 n-type extension high-concentration impurity diffusion layer 105A n-type extension high-concentration impurity layer 106 p-type pocket Impurity diffusion layer 106A p-type pocket impurity layer 107 sidewall 200 semiconductor substrate 201 gate insulating film 202 gate electrode 203 p-type impurity diffusion layer 204 n-type high concentration impurity diffusion layer 205 n-type extension high concentration impurity diffusion layer 206 p-type pocket impurity diffusion layer 207 sidewall 300 semiconductor substrate 301 gate insulating film 302 gate electrode 303 p-type impurity diffusion layer 304 n-type high concentration impurity diffusion layer 305 n-type extension high concentration impurity diffusion layer 305 n-type extension high-concentration impurity layer 306 p-type pocket impurity diffusion layer 306A p-type pocket impurity layer 307 sidewall 400 semiconductor substrate 401 gate insulating film 402 gate electrode 407 sidewall 408 n-type impurity diffusion layer 409 p-type Extension high concentration impurity diffusion layer 410 p-type high concentration impurity diffusion layer

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shinji Odanaka 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F040 DA00 DA13 DC01 EC07 EE05 EF02 EM01 EM02 EM03 FA05 FA07 FB02 FB04 FC11 FC14 FC15

Claims (15)

[Claims] A step of forming a gate electrode on a semiconductor region via a gate insulating film; and implanting heavy ions having a large mass into the semiconductor region using the gate electrode as a mask to form an amorphous layer in the semiconductor region. Forming a first region using the gate electrode as a mask in the semiconductor region.
Ion-implanting an impurity of the following; a step of performing a first heat treatment at a temperature of 400 ° C. to 550 ° C. on the semiconductor region to restore the amorphous layer to a crystal layer; By performing the heat treatment of step 2, the first impurity is diffused to form a first conductivity type extension high-concentration impurity diffusion layer having a shallow junction, and the heavy impurity layer located below the extension high-concentration impurity diffusion layer. Forming a second impurity-type pocket impurity diffusion layer in which ions are diffused, respectively. 2. A step of forming a sidewall on a side surface of the gate electrode, ion-implanting a second impurity into the semiconductor region using the gate electrode and the sidewall as a mask, and activating the second impurity. Forming a first-conductivity-type high-concentration impurity diffusion layer located outside the extension high-concentration impurity diffusion layer and having a deep junction formed by diffusion of the second impurity. 2. The method for manufacturing a semiconductor device according to claim 1, wherein 3. The heavy ion implantation dose is 5 × 1.
^{2. The} method for manufacturing a semiconductor device according to claim 1, wherein the value is 0 ¹³ / cm ² or more. 4. The method according to claim 1, wherein in the second heat treatment, the temperature is increased to a temperature of 950 to 1050 ° C. at a rate of 100 ° C./sec or more,
2. The method for manufacturing a semiconductor device according to claim 1, wherein a rapid heat treatment is performed at the temperature for 1 to 10 seconds. 5. A step of forming a gate electrode on a semiconductor region via a gate insulating film, and ion-implanting heavy ions having a large mass into the semiconductor region using the gate electrode as a mask at an implantation dose at which an amorphous layer is not formed. Performing a first heat treatment at a high temperature for a short time on the semiconductor region a plurality of times; and implanting a first impurity ion into the semiconductor region using the gate electrode as a mask. By performing a second heat treatment on the semiconductor region, a first conductivity type extension high concentration impurity diffusion layer having a shallow junction formed by diffusion of the first impurity and a first conductivity type extension high concentration impurity diffusion layer are formed. Forming pocket impurity diffusion layers of the second conductivity type, which are located below and in which the heavy ions are diffused. A method of manufacturing a semiconductor device. 6. A step of forming a sidewall on a side surface of the gate electrode, ion-implanting a second impurity into the semiconductor region using the gate electrode and the sidewall as a mask, and activating the second impurity. Forming a first-conductivity-type high-concentration impurity diffusion layer located outside the extension high-concentration impurity diffusion layer and having a deep junction formed by diffusion of the second impurity. The method of manufacturing a semiconductor device according to claim 5, wherein 7. The implantation dose of the heavy ions is 5 × 10.
The method of manufacturing a semiconductor device according to claim 5, characterized in that ¹³ / cm ² or less. 8. The second heat treatment, wherein the temperature is raised to a temperature of 950 to 1050 ° C. at a rate of 100 ° C./sec or more,
6. The method for manufacturing a semiconductor device according to claim 5, wherein the rapid heat treatment is performed at the temperature for 1 to 10 seconds. 9. A step of forming a gate electrode on a semiconductor region via a gate insulating film; and implanting heavy ions having a large mass into the semiconductor region using the gate electrode as a mask to form an amorphous layer in the semiconductor region. Forming a first region of the semiconductor region using the gate electrode as a mask.
Ion-implanting an impurity of the group; and ion-implanting a group IV element into the semiconductor region using the gate electrode as a mask to depress the position of the amorphous layer in a substrate depth direction. By performing the second heat treatment, the first impurity is diffused, the first conductivity type extension high-concentration impurity diffusion layer having a shallow junction is formed under the first conductivity type, and is located under the extension high-concentration impurity diffusion layer. Forming a second conductivity type pocket impurity diffusion layer in which the heavy ions are diffused, respectively. 10. A step of forming a sidewall on a side surface of the gate electrode, ion-implanting a second impurity into the semiconductor region using the gate electrode and the sidewall as a mask, and activating the second impurity. Forming a first-conductivity-type high-concentration impurity diffusion layer located outside the extension high-concentration impurity diffusion layer and having a deep junction formed by diffusion of the second impurity. The method for manufacturing a semiconductor device according to claim 9, wherein: 11. The heavy ion implantation dose is 5 ×
The method for manufacturing a semiconductor device according to claim 9, wherein the concentration is 10 ¹³ / cm ² or more. 12. The second heat treatment is a rapid heat treatment in which the temperature is raised to a temperature of 950 to 1050 ° C. at a rate of 100 ° C./sec or more and held at the temperature for 1 to 10 seconds. The method of manufacturing a semiconductor device according to claim 9. 13. A step of forming a gate electrode on a semiconductor region via a gate insulating film, and ion-implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask at an implantation dose at which an amorphous layer is not formed. Forming a first conductivity type extension high concentration impurity diffusion layer in which the heavy ions are diffused by repeating a step of performing a heat treatment at a high temperature for a short time on the semiconductor region a plurality of times. After forming a sidewall on a side surface of the gate electrode,
A step of ion-implanting an impurity into the semiconductor region using the gate electrode and the sidewall as a mask; and activating the impurity, whereby the impurity is located outside the extension high-concentration impurity diffusion layer, and the impurity is diffused. Forming a first-conductivity-type high-concentration impurity diffusion layer having a relatively deep junction. 14. The implantation dose of the heavy ions is 5 ×
14. The density is 10 ¹³ / cm ² or less.
13. The method for manufacturing a semiconductor device according to item 5. 15. The heat treatment is a rapid heat treatment in which the temperature is raised to a temperature of 950 to 1050 ° C. at a rate of 100 ° C./second or more and held at the temperature for 1 to 10 seconds. Item 14. A method for manufacturing a semiconductor device according to item 13.