JPH025480A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress an overlapping capacity and to prevent the resistance of source and drain layers from increasing by reducing the lateral size of the end of a gate to the gate as compared with the depthwise size of the position of the end of the gate. CONSTITUTION:A gate oxide film 12 is grown on the surface of a silicon single crystalline substrate 14, a polysilicon film 13 to become a gate electrode is grown thereon, the film 13 and the film 12 are patterned by dry etching, and the surface of the substrate 14 is exposed. Then, it is cooled to the temperature of liquid helium, and with the gate electrode 13 as a mask boron ions are implanted perpendicularly to the surface of the substrate to form source, drain region 11. Thus, since the shape of the source, drain region is smaller in the lateral size from the end of the gate to the gate than the depthwise size of the position of the end of the gate, the resistance of the source, drain is small thereby to prevent an operating speed from deteriorating.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same.

(Prior Art) It is desirable that semiconductor devices used in large-scale integrated circuits be as fine as possible. In a conventional MIS structure transistor, the source and drain are formed by self-aligned ion implantation using the gate electrode as a mask. However, since the implantation depth and lateral spread are about the same, the source and drain ends are at the bottom of the gate F/T%.
Parasitic overlap capacitance is created where the drains overlap.

If the overlamp capacitance is not scaled down at the same time as the device becomes finer, the dynamic characteristics of the device will deteriorate. Conventionally, there are techniques for shallowly implanting impurities into the source and drain to relatively reduce the lateral spread, and techniques for suppressing wraparound by providing spacers on the side walls of the gate electrode.

(Problems to be Solved by the Invention) However, when shallow implantation is performed to suppress lateral wraparound, the resistance of the source and drain layers increases.

In addition, if spacers are provided on the side walls of the gate electrode, the manufacturing process will be complicated and the yield will be adversely affected if the effective mask length is increased, and the source and drain ends will be separated from the gate end due to manufacturing variations. Therefore, the purpose of the present invention is to suppress the overlap capacitance.
It is an object of the present invention to provide an MIS transistor which can also prevent an increase in the resistance of the source and drain layers, and a method for easily manufacturing this structure using a self-alignment line.

(Means for Solving the Problems) In the MIS structure semiconductor device of the present invention, the shape of the source and drain regions is such that the lateral dimension from the gate end to the bottom of the gate is very large compared to the depth direction dimension at the gate end position. It has a structure characterized by its small size.

Further, in the method for manufacturing a MIS structure semiconductor device of the present invention, ions are formed on a semiconductor single crystal substrate having a low index surface, using a portion that will become a gate electrode as a mask, and forming a source and a drain in an extremely low temperature state so that most of the ions are channeled. This manufacturing method is characterized in that it is formed in a reself line by injection.

(Function) Next, the present invention will be explained in detail. Figure 1 shows the MIS of the present invention.
) is a diagram schematically showing the structure of a transistor.

In the figure, 1 is a gate electrode, 2 is a gate insulating film, 3 is a source and drain region, and 4 is a semiconductor substrate. In this structure, the edge of the gate electrode 1 and the source/drain 3
Since the positions of the ends of the capacitors almost coincide and the overlap is very small, an increase in overlap capacitance and resistance can be prevented and high-speed operation can be expected.

Further, in the manufacturing method of the present invention, ion implantation is performed perpendicularly to the low index surface crystal substrate at an extremely low temperature.

In other words, by lowering the temperature to an extremely low temperature, crystal lattice vibrations are eliminated, and most of the implanted ions are channeled in the direction of the low index axis of the crystal. This allows for sufficient implantation in the depth direction while suppressing the spread in the lateral direction, making it possible to easily realize the structure of the present invention. Figure 2 (a)-(b)
This figure shows a computer simulation of the profile when boron ions are implanted into a silicon crystal when there is no crystal lattice vibration. The crystal plane is (ioo), the implantation energy is 5kev, and the dose is I x 11015
The case of a' is shown. FIG. 2(a) is a depth direction-dimensional profile, and FIG. 2(b) is a cross-sectional two-dimensional isoconcentration line representation under the mask. This proves that the shape of the injection layer is deep below the mask edge but has very little lateral extent.

(Example) Next, a typical example of the MIS l-transistor of the present invention will be described using a series of process diagrams shown in FIGS. 3(a) to 3(d).

In Figure 3(a), the low index surface, here (100
) A gate oxide film 12 was grown on the surface of a silicon single crystal substrate 14 having a surface, and a polysilicon film 13 to be a gate electrode was grown thereon to a thickness of 0.5 pm. Then the third
As shown in Figure (b), the polysilicon film 13 and gate oxide film 12 were patterned by dry etching. Here, the surface of the single crystal substrate 14 is exposed. Next, this is cooled to liquid helium temperature, and at the same time the gate electrode 1
3 as a mask, boron ions (1113+) are applied to the substrate (1
00) perpendicular to the surface, dose I x 11015a'
, the source/drain regions 11 were formed by implantation at an acceleration energy of 5 keV. The steps up to this point are shown in FIG. 3(c). Next, an interlayer insulating film 15 is grown on this, and then heated to 1000°C for both flow and activation of source/drain impurities.
Lamp annealing was performed for 10 seconds, contact holes were opened, and wiring 16 was provided. This is shown in FIG. 3(d).

In the above steps, the depth of the source/drain diffusion layer 11 is 0.
3pm, lateral spread from gate edge to bottom of gate is 0
．． 05pm was obtained, which is sufficiently small compared to the depth. FIG. 3(d) shows a typical M-type S transistor having the structure of the present invention.

(Effects of the Invention) According to the structure of the MIS transistor of the present invention, although there is almost no overlap capacitance between the gate and the sheath/drain as compared to the conventional one, the depth is 0.5 mm in the embodiment.
Deep at 3pm. Therefore, compared to the conventional shallow junction source/drain whose lateral spread is minimized, the resistance of the source/drain is small and deterioration in operating speed can be prevented.

According to the manufacturing method of the present invention, the shape of the source and drain regions, which is a structural feature of the present invention, is that the lateral dimension from the gate edge to the bottom of the gate is very large compared to the depth dimension at the gate edge position. It is possible to easily create a small source line with no gate end overlamp using the gate electrode and self-alignment line. That is, the effect of the present invention is manifested in that it does not require the conventional process of complicating the manufacturing process to the extent that it affects the yield, that is, the technique of providing a spacer on the gate electrode serving as a mask.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of the M/S transistor of the present invention, FIGS. 2(a)-(b) are diagrams showing the results of computer simulation to prove the effects of the manufacturing method of the present invention, and FIG. a)-(d) are cross-sectional views showing a typical embodiment of the present invention in the order of steps; 1.11...source/drain diffusion layer, 2,12...
・Gate insulating film, 3.13'...Gate electrode, 13・
...Polysilicon film, 4...Semiconductor substrate, 14...
Silicon single crystal substrate, 15... interlayer insulating film, 16...
·wiring.

Claims (2)

[Claims] (1) A MIS structure semiconductor device characterized in that the shape of the source and drain regions is such that the lateral dimension from the gate end to the bottom of the gate is extremely small compared to the depth dimension at the gate end position. . (2) The source and drain are formed by ion implantation into a semiconductor single crystal substrate having a low surface index surface using the portion that will become the gate electrode as a mask in an extremely low temperature state so that most of the ions are channeled. A method for manufacturing a semiconductor device.