JPH025455A - Semiconductor device for chip-on-chip - Google Patents

Abstract

PURPOSE:To easily realize an all-in-one device and to simplify a process by applying the other chip including an E<2>PROM element on one chip including a semiconductor element necessary for a wafer process different from the E<2> PROM element by a face-down bonding. CONSTITUTION:In order to manufacture an all-in-one device in which all functions are unified on the same wafer by an all-in-one process, an E<2>PROM element necessary for a different wafer process and other elements adhere by a protruding electrode 2 formed on chips including the element on a base chip 1 with the chip including the latter element as a base by a chip-on-chip by face-down bonding. Thus, satisfactory products can be selected as chips, and since the chip may be placed on the chip, a process is simplified, and the chip size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention requires different wafer processes when formed on the same wafer, resulting in longer steps, higher costs, and fewer defects. Regarding improved technology for so-called all-inch devices that combine all functions, we are particularly interested in all-in-one functional modules that combine E2PROM elements and other elements.
The present invention relates to a technique that can eliminate the above-mentioned drawbacks.

[Conventional technology]

The conventional mounting method for multichip modules is generally the on-substrate method, in which many chips are mounted on a single board. However, there are disadvantages such as increased parasitic capacitance and slower speed.

To this end, it has been proposed to create an all-in-one device that integrates all functions on the same wafer.

An example of a patent that describes an all-in-one device is Japanese Patent Laid-Open No. 136865/1983.

[Problem to be solved by the invention]

However, when trying to realize an all-in-one device with all functions on the same wafer, different wafer processes are required, such as the need to perform the ion implantation process multiple times, or The diffusion process may need to be performed several times, and in particular, the mask process may require a large number of masks, which lengthens the process, increases costs, and increases the chip size. Therefore, defects are more likely to occur and yields are inevitably lower. In particular, E2P 几UM (Elec-tric
ally Erasable Programma
bleRead Qnly Memory (electrically rewritable read-only memory element) element and other elements such as R, AM (Random Access
When realizing an all-in-one device such as a standard cell or one-chip microcomputer that includes a memory (memory) element, the well concentration separation process as a high-voltage process is necessary because E2PROM is a memory element that requires the use of high voltage during writing. and MNO8 structure and FLO
TOX structure creation process, Zener diode creation process, etc. are required, and therefore, even though the device area for EtPROM creation per wafer is only 1/4 to 1/1O, the mask process for this is required. This requires an additional masking process, approximately 5 to 10 times in total. This may lead to producing only defective products.

The present invention solves the drawbacks of the prior art.1.
In particular, if semiconductor devices such as E2PROM devices and other devices are to be formed on the same wafer, the process will be long, the cost will be high, the chip size will be large, and the yield rate will be low. The purpose is to provide technology that can realize an all-in-one device that eliminates the problems.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In the present invention, if all functions are to be manufactured in one KL, fc all-in-one device on the same wafer by an all-in-one process, a different wafer process is required. Regarding the FROM element and other elements, a chip containing the latter element is used as a base, and a chip containing the E"FROM element is formed on each chip on the base chip by chip-on-chip using 7-eight down bonding. 1. The electrodes were bonded using the protruding electrode (panda) part.

In addition, the all-in-one device using the chip-on-chip was mounted on a support and fixed by botting with a polyimide synthetic resin liquid, and after the fixation, the entire device was sealed using plastic sealing or the like.

[Effect]

In this way, according to the method of mounting chips including E"FROMi elements on pace chips, it is possible to select good products for each chip, and there is no need to change the mask on the same wafer, thereby eliminating defective products. (7) In addition, since it is only necessary to mount a chip on a chip, the process is simplified and the chip size Furthermore, since the chips are connected by bumps, there is no need for long wiring to connect between chips as in the conventional on-subplane method, which reduces wiring capacitance and resistance. can be reduced.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

As shown in FIG. 1, bumps 2 are provided around the inner surface of the pace chip 1.

On the other hand, bumps 4 are also provided around the surface of the chip 3 including the E2P11,0M element.

As indicated by the arrow in FIG. 1, E! The chip 3 containing the FROM element is turned over and bonded to the surface of the pace chip 1.

FIG. 2 shows a cross section of an example of a main part of a chip 3 including an E"P OM element.

In FIG. 2, 5 is a device region, 6 is an insulating film, 7 is a structural wiring, 8 is a passivation film, 9 is a Cr layer, 10 is a C
11 is an Al1 layer, and bumps 4 made of Al or solder, for example, are provided on the surface of the Au layer 11 in a protruding manner.

The pace chip 1 shown in FIG. 1 also has a similar configuration.

The pace chip 1 is made of, for example, a silicon crystal substrate, in which a number of circuit elements are formed by known techniques to provide a single circuit function. A specific example of the circuit element is, for example, a MOS transistor, and the circuit functions of, for example, a logic circuit and a memory are formed by the stiff circuit element.

The pace chip 1 is composed of, for example, a one-chip microcomputer, and includes a CPU (central processing unit), memory (RA-i, ROM), input/output circuit (110 ports), and the like.

The chip 3 containing the E2PROM element to be chip-on is also
For example, it is made of a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function.

A specific example of the circuit element is, for example, a MOS transistor.
OM) circuit functions are formed.

FIG. 5 shows a system block diagram in the present invention.

Pace chip (1 chip microcomputer) 1 has
CPU 12, RAMI 3, ROM14.

■10 boats 15. Built-in timer 16 1. Indicates the status quo.

This pace chip 1 and the chip 3 including the E"PlrOM element mounted on the pace chip 1 have bumps 2 and 4.
connected by. The chip-on-chip forms an all-in-one device.

FIG. 3 shows a sectional view of a main part showing an embodiment of the present invention. After the chip 3 is placed on the pace chip 1 and the bumps 2 and 4 formed on these chips are melted and bonded, the chip 3 is mounted on a support 17, and a fixing material 18 made of, for example, a polyimide synthetic resin liquid is botted. Then, these chips 1 and 3 are fixed.

FIG. 4 shows the entire semiconductor device according to the present invention with a portion thereof cut away.

The support body 17 is made of a lead frame, for example, and the chip-on-chip all-in-one device is mounted on the tab portion of the lead frame 17, and wire bonding pads (not shown) around the pace chip 1 are mounted.
and the inner leads of the lead frame 17 are made of, for example, Au.
A chip-on-chip semiconductor as shown in FIG. A device 20 can be obtained.

According to the invention, an E! By melting and bonding the bumps 2 and 4 formed on the chips 1 and 3 to the whip 3 containing the FROM element, an all-in-one device can be easily obtained, without relying on the chip-on-chip mounting method. , it would take too many steps to manufacture a device with all these functions in one wafer.
The cost is higher and the chip size is also larger.
Furthermore, defects are more likely to occur, but according to the present invention, these drawbacks can be eliminated.

Further, wiring capacitance and wiring resistance can also be reduced.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and it is possible to make various changes without departing from the gist of the invention. Not even.

In the above explanation, the invention made by the present inventor was mainly applied to a resin-sealed semiconductor device, which is the background field of application, but the invention is not limited thereto. It can also be applied to devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, an all-in-one device can be easily realized, the process is simplified, the cost is reduced, and the yield is improved (7) The wiring capacitance is reduced, and the chip area can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a perspective view showing an actual case of the present invention, Fig. 2 is a sectional view of a main part showing an embodiment of the invention, Fig. 3 is a sectional view of a main part showing an embodiment of the invention, and Fig. 4 is a sectional view of a main part showing an embodiment of the invention. FIG. 5 is a partially cutaway perspective view showing an embodiment of the present invention, and FIG. 5 is a system block diagram showing an embodiment of the present invention. 1... Base chip, 2... Bump (protruding electrode part), 3... Chip including E2PH, 0M element, 4...
・Bump, 5... Device area, 6... Insulating film, 7
... Electrode wiring, 8... Passivation film, 9...
・Cry, 10...Cu layer, 1l-AU layer, 12・C
PU113・RAM. 14...ROM115...I10 boat, 16...
- Timer, 17... Lead frame, 18... Bonding wire, 19... Resin sealing part, 20... Semiconductor device. Figure 1 Figure 2, 3 Figure 4 Figure 3 Figure 7 Creed 7 to Leh/

Claims (1)

[Claims] 1. When forming a semiconductor element, an all-in-one device in which another chip is mounted on one chip using a chip-on-chip method that requires different wafer processes is mounted on a support and fixed. , in a sealed semiconductor device, in which the all-in-one device includes one chip containing a semiconductor element that requires a different wafer process than the E^2PROM element, and another chip containing the E^2PROM element;
A chip-on-chip semiconductor device characterized in that it is mounted by face-down bonding and by joining protruding electrode portions formed on these chips. 2. The chip-on-chip semiconductor device according to claim 1, wherein the chip-on-chip all-in-one device is fixed by potting a polyimide synthetic resin liquid.