JPH0253947B2 - - Google Patents
Info
- Publication number
- JPH0253947B2 JPH0253947B2 JP56208633A JP20863381A JPH0253947B2 JP H0253947 B2 JPH0253947 B2 JP H0253947B2 JP 56208633 A JP56208633 A JP 56208633A JP 20863381 A JP20863381 A JP 20863381A JP H0253947 B2 JPH0253947 B2 JP H0253947B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- transistor
- opposite
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は同一半導体基板にダーリントントラン
ジスタとスビードアツプダイオードを組み込んだ
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device incorporating a Darlington transistor and a speed-up diode on the same semiconductor substrate.
第１図の等価回路で示されるこのような半導体
装置は、既に本出願人が特願昭52−159933（特開
昭54−91184）において出願しており、例えば第
２図およびその−線断面図の第３図に示すよ
うにＮ形シリコン基板１にＰ領域２を設け、この
Ｐ領域内に一方の表面から延びる三つのＮ領域
３，４，５が形成されている。Ｎ形基板１とＰ領
域２およびＮ領域３により第１図における前段ト
ランジスタTr1を構成し、Ｎ形基板１とＰ領域２
およびＮ領域５により後段トランジスタTr2を構
成する。トランジスタTr1のエミツタとTr2のベ
ースは領域３に設けられた電極３１とＰ領域２に
設けられた電極２２にまたがる接続導体６によつ
て接続されている。各電極３１，２２および接続
導体６は第１図に同じ符号で示された部分に対応
する。さらにＮ領域４とＰ領域との間において第
１図のスピードアツプダイオードＤを構成し、Ｎ
領域４に設けられた電極４１をＰ領域２に設けら
れた電極２１とを接続導体７で接続し、接続導体
７ならびに基板１およびＮ領域５に設けた電極１
１および５１よりそれぞれ端子Ｂ，Ｃ，Ｅを引き
出すことにより第１図の回路に相当する半導体装
置が完成する。しかしこのような半導体装置にお
いてＮ領域４とＰ領域５の間に形成されるダイオ
ードＤでは、Ｎ領域４の下側のＰ領域５の厚さが
薄いため、ダイオード電流はほとんど太線で示し
たＮ領域４を基板面方向でとり囲むPN接合８を
通じて流れる。従つてＮ領域４の面積が小さいと
きにはダイオードＤの順電圧が大きくなり、スピ
ードアツプダイオードとしての効果が減少する。
順電圧を下げるためにＮ領域４の面積を大きくす
れば、トランジスタTr1またはTr2の有効面積が
減らさなれいためには基板を大きくする必要が生
ずる。 Such a semiconductor device shown by the equivalent circuit in FIG. 1 has already been filed by the present applicant in Japanese Patent Application No. 52-159933 (Japanese Patent Application Laid-Open No. 54-91184), and for example, the semiconductor device shown in FIG. As shown in FIG. 3, an N-type silicon substrate 1 is provided with a P region 2, and within this P region, three N regions 3, 4, and 5 are formed extending from one surface. The N-type substrate 1, the P region 2, and the N region 3 constitute the front-stage transistor Tr1 in FIG.
and N region 5 constitute a subsequent transistor Tr 2 . The emitter of the transistor Tr 1 and the base of the transistor Tr 2 are connected by a connecting conductor 6 spanning an electrode 31 provided in the region 3 and an electrode 22 provided in the P region 2. Each electrode 31, 22 and connecting conductor 6 correspond to the parts indicated by the same reference numerals in FIG. Furthermore, a speed-up diode D shown in FIG. 1 is configured between the N region 4 and the P region, and the N
The electrode 41 provided in the region 4 is connected to the electrode 21 provided in the P region 2 by a connecting conductor 7, and the electrode 1 provided in the connecting conductor 7, the substrate 1, and the N region 5.
By drawing out terminals B, C, and E from terminals 1 and 51, respectively, a semiconductor device corresponding to the circuit shown in FIG. 1 is completed. However, in the diode D formed between the N region 4 and the P region 5 in such a semiconductor device, since the thickness of the P region 5 below the N region 4 is thin, the diode current is almost the same as the N region indicated by the thick line. It flows through the PN junction 8 surrounding the region 4 in the direction of the substrate surface. Therefore, when the area of N region 4 is small, the forward voltage of diode D increases, reducing its effectiveness as a speed-up diode.
If the area of N region 4 is increased in order to lower the forward voltage, it becomes necessary to increase the size of the substrate in order to avoid reducing the effective area of transistor Tr 1 or Tr 2 .
本発明は、上述の欠点を除去してより小さな面
積でも十分小さな順電圧を示す組込みダイオード
を有する半導体装置を提供することを目的とす
る。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device having a built-in diode that exhibits a sufficiently small forward voltage even in a smaller area.
この目的は組込みダイオードを形成するために
設けられた領域が基板面に平行に且つ櫛歯状に屈
曲した輪郭を有するPN接合面で囲まれた形状を
有することによつて達成される。 This object is achieved in that the region provided for forming the built-in diode has a shape parallel to the substrate surface and surrounded by a PN junction surface having a comb-like curved contour.
以下図を引用して本発明の実施例について説明
する。第２、第３図と共通の部分に同一の符号を
付した第４図およびその−線断面図である第
５図において、断面では第３図と全く同様の構造
であるが、第４図から明らかなようにダイオード
を形成するＮ領域４の平面形状は櫛形を呈し屈曲
した輪廓を有している。従つてＰ領域２との間の
PN接合８の面積は第２、第３図の場合に比して
大きくなり、順電圧が増大しない。しかもＮ領域
４の基板面に平行な縦および横寸法は第２、第３
図の場合とほぼ同じにできるので、基板面積が大
きくなることもない。 Embodiments of the present invention will be described below with reference to the drawings. In FIG. 4, in which the same parts as in FIGS. 2 and 3 are given the same reference numerals, and in FIG. As is clear from the figure, the planar shape of the N region 4 forming the diode is comb-shaped and has a curved circumference. Therefore, between P area 2
The area of the PN junction 8 is larger than in the cases shown in FIGS. 2 and 3, and the forward voltage does not increase. Moreover, the vertical and horizontal dimensions parallel to the substrate surface of the N region 4 are the second and third dimensions.
Since it can be made almost the same as the case shown in the figure, the board area does not increase.
第６図ａ，ｂはダイオード領域の別の形状で、
第６図ａでは丸味を持つてジグザグ状、第６図ｂ
では片側のみに歯を有する櫛形である。 Figures 6a and 6b show another shape of the diode region,
Figure 6a shows a rounded zigzag shape, Figure 6b
It is comb-shaped with teeth on only one side.
上記の従来例、実施例においては、NPNトラ
ンジスタからなるダーリントントランジスタにつ
いて述べたが、もちろんPNPトランジスタの場
合にも同様に実施できる。 In the above conventional examples and embodiments, a Darlington transistor made of an NPN transistor was described, but of course the same can be applied to a PNP transistor.
以上述べたように本発明はダーリントントラン
ジスタと同一半導体基板に組込まれるスピードア
ツプダイオードの平面形状に櫛歯状に屈曲した
PN接合を持たせることによりダイオードの占有
面積を増大させることなく有効接合面積を増大さ
せて順電圧の低いダイオードとするもので、ター
ンオフ時間の短い高速ダーリントントランジスタ
として動作する半導体装置が従来と同一面積の基
板を用いて同一工程により作成することが可能で
あるため、得られる効果は極めて大きい。 As described above, the present invention has a speed-up diode that is bent in a comb-like shape in a planar shape to be incorporated into the same semiconductor substrate as a Darlington transistor.
By providing a PN junction, the effective junction area is increased without increasing the occupied area of the diode, resulting in a diode with low forward voltage.The semiconductor device, which operates as a high-speed Darlington transistor with a short turn-off time, has the same area as a conventional one. The effect obtained is extremely large because it can be manufactured using the same substrate using the same process.
第１図は本発明による半導体装置の等価回路
図、第２図は第１図の半導体装置を１枚の半導体
基板内に構成した従来例の部分平面図、第３図は
その−線矢視断面図、第４図は本発明の一実
施例の部分平面図、第５図はその−線矢視断
面図、第６図ａ，ｂはそれぞれ異なる実施例の部
分平面図である。
１……シリコン板、２……Ｐ領域、４……ダイ
オードを形成するＮ領域。
FIG. 1 is an equivalent circuit diagram of a semiconductor device according to the present invention, FIG. 2 is a partial plan view of a conventional example in which the semiconductor device of FIG. 4 is a partial plan view of one embodiment of the present invention, FIG. 5 is a cross-sectional view taken along the - line, and FIGS. 6a and 6b are partial plan views of different embodiments. 1...Silicon plate, 2...P region, 4...N region forming a diode.
Claims (1)
の領域を設け、この逆導電形の領域内の一部に一
導電形の第一の部分領域を設けて、一導電形の基
板と逆導電形の領域および一導電形の第一の部分
領域によりダーリントントランジスタの前段トラ
ンジスタを形成し、逆導電形の領域内の一部に一
導電形の第二の部分領域を設けて、一導電形の基
板と逆導電形の領域および一導電形の第二の部分
領域よりダーリントントランジスタの後段トラン
ジスタを形成し、前段トランジスタの一導電形の
第一の部分領域と後段トランジスタの逆導電形の
領域とにまたがつて導電接触部を設けることによ
り前段トランジスタのエミツタ領域と後段トラン
ジスタのベース領域とを導電接続し、さらに逆導
電形の領域内に一導電形の第三の部分領域を設け
て逆導電形の領域との間にダイオードを形成し、
このダイオードの一導電形の第三の部分領域と前
段トランジスタの逆導電形の領域とにまたがつて
導電接触部を設けることによりダイオードの一極
を前段トランジスタのベース領域に導電接続し、
この導電接続部、後段トランジスタの一導電形の
第二の部分領域、基板の一導電形の部分よりそれ
ぞれ端子を引き出したものにおいて、ダイオード
を形成する一導電形の第三の部分領域が基板面に
平行に且つ櫛歯状に屈曲した輪郭を有するPN接
合面で囲まれた形状を有することを特徴とする半
導体装置。1. A region of an opposite conductivity type is provided on the surface portion of a semiconductor substrate of one conductivity type, and a first partial region of one conductivity type is provided in a part of this region of opposite conductivity type, so that a region opposite to the substrate of one conductivity type is provided. A region of conductivity type and a first partial region of one conductivity type form a front-stage transistor of a Darlington transistor, and a second partial region of one conductivity type is provided in a part of the region of opposite conductivity type, and a second partial region of one conductivity type is formed in a part of the region of opposite conductivity type. A rear-stage transistor of the Darlington transistor is formed from a region of conductivity type opposite to the substrate and a second partial region of one conductivity type, and a first partial region of one conductivity type of the front-stage transistor and a region of opposite conductivity type of the rear-stage transistor are formed. The emitter region of the former transistor is conductively connected to the base region of the latter transistor by providing a conductive contact portion across the region, and a third partial region of one conductivity type is provided within the region of the opposite conductivity type to provide reverse conductivity. form a diode between the shaped region,
A conductive contact is provided across a third partial region of one conductivity type of the diode and a region of the opposite conductivity type of the preceding transistor, thereby conductively connecting one pole of the diode to the base region of the preceding transistor;
In this conductive connection part, a second partial region of one conductivity type of the subsequent transistor, and a terminal drawn out from a part of one conductivity type of the substrate, the third partial region of one conductivity type forming a diode is connected to the substrate surface. 1. A semiconductor device characterized by having a shape surrounded by a PN junction surface having a comb-teeth-shaped curved contour parallel to the .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56208633A JPS58110071A (en) | 1981-12-23 | 1981-12-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56208633A JPS58110071A (en) | 1981-12-23 | 1981-12-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58110071A JPS58110071A (en) | 1983-06-30 |
| JPH0253947B2 true JPH0253947B2 (en) | 1990-11-20 |
Family
ID=16559456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56208633A Granted JPS58110071A (en) | 1981-12-23 | 1981-12-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58110071A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0426535U (en) * | 1990-06-27 | 1992-03-03 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669860A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Semiconductor device |
-
1981
- 1981-12-23 JP JP56208633A patent/JPS58110071A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669860A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58110071A (en) | 1983-06-30 |
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