JPH0253142A - Diagnosing system for vector register - Google Patents

Abstract

PURPOSE:To diagnose a vector register VR at a high speed without stopping a system clock by writing and reading the prescribed data into and out of the VR with use of the system clock. CONSTITUTION:At diagnosis a VR write control circuit 20 selects 0 via a selector 16. Then a write address generating circuit 40 0-clears a write address latch 51 and adds 1 successively to give a write address to a VR10 via a selector 60. Then 0 is written into all elements of the VR10. At reading a VR read control circuit 30 0-clears a read address latch 52 via a read address generating circuit 41 and adds 1 successively. Then a read address is given to the VR10 via the selector 60 and all elements of the VR10 are read out. These writing and reading actions are carried out synchronously with a system clock.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a diagnostic method for vector registers (hereinafter referred to as VR), and in particular, to updating the write address and read address of VR using a system clock. The present invention relates to a VR diagnostic method that allows diagnosis to be performed by writing and reading VR at high speed.

[Prior Art] A scan-in/scan-out control method has been widely adopted as an effective maintenance/diagnosis method for data processing devices. As a conventional technique for diagnosing registers that use RAM for registers such as VR, for example, Japanese Patent Application Laid-Open No. 59-1240
A technique described in Publication No. 75 and the like is known.

Hereinafter, a diagnosis method according to this kind of conventional technology will be explained with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of an example of a conventional technique for diagnosing a RAM by scan-in/scan-out. In FIG. 4, 1 is a RAM, 2 is an address latch, 3 is a data-in latch, 4 is a write latch, 5 is a data-out latch, 6 is a clock amplifier, and 8 is a scan control circuit.

In the prior art shown in FIG. 4, latches 2 to 4 control writing and reading of data to and from RAM 1 during normal operation or scan operation, and latch 5 controls data reading from and writing to RAM 1 during normal operation or scan operation.
These latches 2 to 5 can be scanned in and scanned out from the scan control circuit 8, respectively.

Under normal operating conditions, the address signal (Address
s), the data-in signal (DATAiN), and the write signal (Write) are input to the data output of the corresponding latches 2 to 4, respectively, and the system clock (
CLOCK) is applied to the clock input CK of each latch 2-4 via the clock amplifier 6. As a result, target data is written into the RAM 1 in synchronization with the system clock. Further, the RAMI can be read out in synchronization with the system clock using the address signal input to the address latch 2, and the read data from the RAMI can be read out from the system clock via the data out latch 5. Read out in synchronization with timing.

On the other hand, in the diagnostic state for RAM1.

The system clock is stopped, and the scan clocks 9-1 to 9-4 from the scan control circuit 8 become valid instead. These scanning clocks 9-1 to 9-4 are
The scan control circuit 8 generates a scan address signal (SC
A N Address), scan timing signal (
This is a clock generated based on a scan-out mode signal (SCAN OUT MODE), a scan-in mode signal (SCAN iN MODE), and a scan control circuit 8 based on a scan address signal.

Scan clocks 9-1 to 9-4 can be generated for each of the latches 2 to 5 described above. In addition, in the diagnostic state, each data input of latches 2 to 4 is
Diagnostic addresses, diagnostic data, and write control signals are provided.

When writing data to the RAMI in a diagnostic state, the scan control circuit 8 first generates a scan clock 9-1, and sets a diagnostic address in the address latch 2 using this clock 9-1 and the scan-in data input. . Similarly, the scan control circuit 8 writes diagnostic data into the data latch 3 using the scan clock 9-2.Next, the scan control circuit 8 generates the scan clock 9-3 and at the first scan clock timing. , set the write latch 4 to “H” state, and set the write latch 4 to u L at the next scan clock timing.
The scan control circuit 8 writes the diagnostic data set in the data latch 3 into the RAM 1 according to the diagnostic address set in the address latch 2 by controlling the latches 2 to 4 as described above. Can be done.

Also, when reading data from RAM1 in the diagnostic state,
The scan control circuit 8 sets a diagnostic read address in the address latch 2 based on the scan-in data input and the scan clock 9-1. When the diagnostic read address is set in address latch 2, RAM1
The output of (D.

Since the data corresponding to the above-mentioned diagnostic read address is output to the UT), the scan control circuit 8 outputs the scan clock 9-4 to the data out latch 5.
By generating , read data can be set in the latch 5, and the data can be read from the RAM 1.

[Problems to be Solved by the Invention] The above-mentioned conventional technology specifies RAM addresses in units of 13 through scan-in/scan-out operations and writes and reads data to and from the RAM.
Since we are diagnosing the AM, if the RAM is large capacity like a VR, diagnosing it will take a lot of time, and diagnosing the VR of the entire vector processing device may take several minutes in some cases. There was a problem in that it required

The purpose of the present invention is to solve the problems of the prior art described above,
To provide a VR diagnostic method that enables VR diagnostics to be executed at high speed without stopping the system clock by using normal logic without relying on the scan-in/scan-out method.

[Means to solve the problem] According to the invention, the purpose is a VR clear signal.

In addition to providing a VR read signal and a VR read ink signal, a function to guarantee 0" or 11171 for VR write data and a function to decode the maximum element number of the VR write address is provided, and predetermined data can be written to VR using the system clock. This is achieved by performing readout.

[Function] When the VR clear signal is set to "1", the VR write data guarantee function guarantees "0" or "1" for the VR write data, for example, it Opp, and clears the VR write address to ``0''. be done. After that, the VR write address is not incremented by +1 by the system clock, but is
This operation of generating an R write pulse and writing "0" to VR is performed by the maximum element number decoding function of the VR write counter.

This continues until writing to all elements of VR is completed.

Next, when the VR read signal is set to 1, the VR read address is cleared to "'O", and thereafter, by setting the VR read ink signal to "1", the VR read address is incremented by 1 according to the system clock, and the VR You can read any element of .

The present invention, as described above, writes to VR.

Since reading can be performed at high speed using the system clock, VR diagnosis can be performed at high speed.

Further, the present invention can also be used for high-speed VR clearing by using only the write operation described above.

[Implementation g%] Hereinafter, one embodiment of the VR diagnostic method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing details of the VR write control circuit,
Fig. 3 is a block diagram showing details of the VR read control circuit.6 In Figs. Control path, 23 is a write pulse control circuit, 24.32 is a +1 control circuit, 30 is a VR read control circuit, 40 is a write address generation circuit, 4
1 is a read address generation circuit.

FIG. 1 shows an embodiment of the present invention showing the overall configuration including a VR control system, and this embodiment includes a VRIO, a VR write control circuit 20. VR read control circuit 30, write address generation circuit 40. Read address generation circuit 4
1 and a plurality of latches 50 to 54.

The latches 50 to 54 are a write launch 50, a write address latch 51, a read address latch 52, and
They are a data-in latch 53 and a data-out latch 54. In an embodiment of such a configuration, the VRIO has n
The write address generation circuit 40 clears the write address to "0", +1. The read address generation circuit 41 has a maximum value detection function.
It has a read address 11071 clear and +1 function. Further, pipe A and pipe B are pipes to which write data to the VR 10 is sent from the main storage section and the arithmetic unit, respectively.

Writing data to VRIO in the normal state of the embodiment of the present invention configured as described above will be described.

Writing to VRIO in a normal state is writing data sent from the main storage unit or arithmetic unit via pipe A or pipe B. In this case, the VR write control circuit 20 first provides the pipe select signal 20-1 to the selector 61.

Selects pipe A or pipe B, and at the same time generates write address II O19 clear signal 20-3.

9. The write address generation circuit 40 clears the write address latch 51 to "0".Next, the VR write control circuit 20 generates write pulse signals 20-2, 20-2, and 20-2 in synchronization with the data from pipe A or pipe B. A write address +1 signal 20-4 is generated. As a result, the write latch 50 is set, and the write address generation circuit 40 sequentially increments the write address latch 51 by +1, and this write address is given to VRIO via the selector 60. Data set in the in-latch 53 from pipe A or pipe B is sequentially written to each element of VRIO.

When reading VRIO, the VR read control circuit 30 first generates a read address "0" clear signal 30-1, sets the read address latch 52 to "0" via the read address generation circuit 41, and then VR
The read control circuit 30 receives the read address +1 signal 30
-2 is generated.

Accordingly, the read address generation circuit 41.

The value of the read address latch 52 is sequentially incremented by 1, this read address is given to the VRIO via the selector 60, and the target data can be read from the VRIO to the data out latch 54.

Next, write and read operations for VRIO in the diagnostic state will be described.

During a write operation, first, the VR write control circuit 20:
Upon receiving VR clear signal 100, pipe select signal 2
This causes the selector 61 to output ``0-1''.
Select the input signal to ensure that the write data is 0'', and at the same time write 7 dress 110 n clear signal 20
-3 and causes the write address generation circuit 40 to clear the write address latch 51 to 0". Next, the VR
The write control circuit 20 generates a write pulse signal 20-2°ride address+1 signal 204. As a result, the write latch 5o is set, and the write address generation circuit 40 sequentially sets the write address latch 51 to +.
1 and this write address is given to VRIO via the selector 6o, so the write data “0” set in the data-in latch 53 is
71 is sequentially written to each element of VRIO. VR
When the writing of data "'0" to all elements of LO is completed, the write address generation circuit 4o detects that the write address for VRIO has become the maximum element address of VRIO, and generates a maximum value signal 20-5. do.

The VR write control circuit 2o receives this maximum value signal 20-5.
In response, the write operation to VRIO is stopped.

When reading the “0” data written above, VR
The read control circuit 30 receives the VR read signal 200, generates a read address "0" clear signal 30-1, and sets the read address latch 52 to "OII" via the read address generation circuit 41. The VR read control circuit 30 receives the VR read ink signal 201 and generates a read address +1 signal 30-2.Thereby, the read address generation circuit 41 sequentially increments the read address latches 52 by +1 and selects this address. 60 to VRIO, the data in VRlo is read out sequentially via data out latch 54.

Writing and reading from VRlo in the above-described diagnostic state is performed using the system clock as in the normal operation, so diagnosis can be performed at extremely high speed. Further, since data "0" is used as write data, it is possible to clear VRIO at high speed only by a write operation.

Next, details of the v8 write control circuit 20 and the VR read control circuit in the embodiment of the present invention that operate as described above will be described.

As shown in FIG. 2, the VR write control circuit 20 includes a pipe select control circuit 21, a tt Ou clear control circuit 2.2, a write pulse control circuit 23, and a +1 control circuit 24.
．． Latches 70, 71, OR gates 80-83 and AND
It is constituted by a gate 84.

The various control circuits 21 to 24 described above are control logics necessary for normal operation, and include the latch 70, 71 and gate 8.
0 to 84 are logics for diagnosis.

During the write operation in the diagnostic state, the VR clear signal 100 is sent to the VR write control circuit 20 as described with reference to FIG.
is given. This clear signal, after being set in the latch 7o, acts on the pipe select control circuit 21 to generate a pipe select signal 20-1 that causes the selector 61 in FIG. 1 to select data "0". , O
Via the R gate 80, it is output as a write address "0" clear signal 20-3. Next, the VR clear signal held in the latch 70 is set in the latch 71 via the OR gate 83 in synchronization with the system clock, and is then set in the latch 71 via the AND gate 84 to the OR gates 81 and 82.
These gates 81 and 82 output a write pulse signal 20-2 and a write address +1 signal 20-4.

As a result, “0” element of VRIO shown in Fig.
Then, in synchronization with the system clock, the data in the latch 71 is written to the AND gate 84,
It is set again to the latch 71 via the R gate 83,
Light pulse signal 20-2. Write address +1 signal 2
o-4 is generated again. As a result, VRIO “1”
It OIT is written to the ``th element.'' After that, the same operation is repeated until the largest element of VRIO, in this example (n
-1) Write address generation circuit 4 in synchronization with lock
A write address maximum value signal 20-5 is sent from 0 to 0. This write address maximum value signal 2o-5 is AND
Since it acts on the gate 84 and suppresses the output data of the latch 71, the VR write control circuit 20 ends the "0" write process to VRIO.

As shown in FIG.
0″ clear control circuit 31. +1 control circuit 32, latch 9
0,91 and OR gates 92,93.

The control circuits 31 and 32 are as follows.

This is the control logic necessary for normal operation, and the latch 90
．． 91 and OR gates 92 and 93 are logic for diagnosis.

During the read operation in the diagnostic state, the VR read signal 200 and the VR read ink signal 201 are applied to the VR read control circuit 30, as already described in the explanation of FIG. First, when the VR read signal is applied, this signal is set to the launch 9o and then output as the read address "Ol) clear signal 30-1 via the OR gate 90. As a result, the first As explained in the figure,
The read address latch 52 is cleared to “0” by the read address generation circuit 41, and the VRIO becomes “0”.
The number element is read out via the data out latch 54. Next, when the VR lead ink signal 201 is given,
This signal is set in latch 91 and then outputted as read address +1 signal 30-2 via OR gate 93.

As a result, the read address latch 52 is increased by +1.
Element 11111 of VRIO is read out.
By repeating the above-described operation based on the R read ink signal 201, all elements of VRIO can be read out.

As described above, according to an embodiment of the present invention, VR diagnosis can be performed without stopping the system clock, using the system clock and the logic used during normal operation, to write and read data to and from all elements of the VR using the system clock. It can be executed by synchronizing with
This can be done extremely quickly.

Further, in the embodiment of the present invention, the write data for diagnosis is set to '0', so by using this write, the present invention can clear the VR, that is, initialize it at high speed.

Further, according to the present invention, it is also possible to perform diagnosis by writing "1" into all elements of the VR, and to perform initialization by writing "1" into all elements of the VR. In this case, "02" of the selector 61 in FIG.
The input may be “1” input, or selector 6
Both "0" and "1" may be input to 1 so that they can be selected.

[Effects of the Invention] As described above, according to the present invention, data writing and reading during diagnostic operation of vector registers can be performed in synchronization with the system clock without using the scan-in/scan-out method. This makes it possible to diagnose vector registers at extremely high speed. In addition, initialization of the vector register can be performed extremely quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing details of the VR write control circuit,
FIG. 3 is a block diagram showing details of the VR readout control circuit, and FIG. 4 is a block diagram showing the configuration of an example of the prior art. 1...RAM, 8...Scan control circuit, 10...Vector register (VR), 20
...VR writing control circuit, 22, 31...
...rt OIF clear control circuit, 23...
Write pulse control circuit, 24°32...+1 control circuit, 3o...VR readout control circuit, 40
...Write address generation circuit, 41...
...Read address generation circuit.

Claims (1)

[Claims] 1. In a vector processing device comprising a vector register, a logic unit that writes to an element of the vector register, and a logic unit that reads from the elements of the vector register, the logic unit that performs writing is configured to:
After ensuring that the write data to the vector register is either "0" or "1" and clearing the vector register write address to "0", a vector register write pulse is generated while increasing the address by +1, and all elements of the vector register are filled with the above information. The logic unit that has the function of writing write data and performs the reading sets the vector register read address to “0” by the vector register read signal.
After clearing, the data in the elements of the vector register is sequentially incremented by the vector register read ink signal and has a function of reading out the data in the element. A diagnostic method for a vector register, characterized in that the function is executed in synchronization with the vector register.