JPH0252808B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a direction discrimination circuit, and more specifically, it discriminates whether a position control object (table, tool, etc.) of a machine tool, etc. moves in the forward or reverse direction from the two-phase output of a pulse encoder, and counts each movement amount by counting pulses. This invention relates to a direction discrimination circuit that outputs as follows. For example, in position detection in machine tools, the two-phase output of an incremental type pulse encoder related to the movement of the position controlled object is applied to a direction discrimination circuit, which determines whether the position controlled object moves in the forward or reverse direction. Generates count-up and count-down pulses corresponding to the amount of movement,
This is generally done by driving a reversible counter. Figure 1 shows a conventional example of a direction discrimination circuit, in which the A-phase output of a pulse encoder (not shown) is input to the input terminal IN.
-1 through the first flip-flop 10
, a second flip-flop 12 that receives the B-phase output through the input terminal IN-2, a third flip-flop 14 that receives the _Q1 output of the first flip-flop 10, and a _Q1 output of the first flip-flop 10 and the third flip-flop 14. a first AND gate 16a that receives _three outputs from the first flip-flop 10, _one output from the first flip-flop 10, and one output from the third flip-flop 14;
a second AND gate 16b receiving the _Q3 output of
A first output gate 1 receives the output of the first AND gate 16a and _{the two} outputs of the second flip-flop 12.
8a, and a second output gate 18b receiving the output of the second AND gate 16b and _{the two} outputs of the second flip-flop 12. In addition, input terminal IN-3
A clock is sent to each flip-flop from OUT-1 to OUT-2, and output terminals OUT-1 and OUT-2 are connected to a reversible counter (not shown). 2A and 2B are operation time charts of the circuit shown in FIG. 1, in which FIG. 2A shows the time when a count-up pulse is output, and FIG. 2B shows the time when a count-down pulse is output. Each signal waveform in FIGS. 2A and 2B corresponds to the signal shown with the same reference numeral in the circuit of FIG. The operation of the circuit shown in FIG. 1 will be described below with reference to FIGS. 2A and 2B. A-phase and B-phase output signals b of the pulse encoder,
i has a phase difference of π/2 as shown in FIGS. 2A and 2B. First, the A-phase output b of the pulse encoder is applied as the data input of the first flip-flop 10, and its _Q1 output c drives the third flip-flop 14.
The _Q1 output and the _three outputs of the third flip-flop 14 drive the first AND gate 16a, and _{the one} output of the first flip-flop 10 and the _Q3 output of the third flip-flop 14 drive the second AND gate 16a.
6b, a short-time pulse train g corresponding to the rising edge of the A-phase output and a pulse train h of the same width corresponding to the falling edge of the pulse train g are generated. That is, the pulse train g corresponding to the rising edge is an AND1 of the _Q1 output c of the first flip-flop 10 and _{the third} output f of the third flip-flop 14.
6a, and the pulse train h corresponding to the falling edge is an AND16 of _{the 1} output d of the first flip-flop 10 and the _Q3 output of the third flip-flop 14.
given by b. Next, each pulse train g, h
is connected to the B-phase output i of the encoder and _{the two} outputs k of the second flip-flop 12, which are input as data, via an AND by output gates 18a and 18b.
Output terminal as shown in Figure 2A or Figure 2B
Count up pulse l to OUT-1 and OUT-2
Alternatively, it is supplied as a countdown pulse m. The direction discrimination circuit with the above configuration is widely used today for direction discrimination of pulse encoder output.
A flip-flop with both positive and negative logic outputs is required, and a large number of gates are required to decode the count information, which not only increases the number of ICs required but also complicates the circuit configuration, which increases the number of encoders. The disadvantage is that it increases as the number increases. Therefore, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its purpose is to provide a direction discrimination circuit that simplifies the circuit configuration and can also be used with a plurality of encoders with the same circuit configuration. It is in. To achieve the above object, the present invention generally comprises a first flip-flop that uses one of the two-phase outputs of a pulse encoder as a data input, a second flip-flop that uses the other as a data input, and a Q output of the first flip-flop. It consists of a pulse encoder output direction discrimination circuit having a third flip-flop as a data input, and an IC memory that outputs count-up or count-down pulses according to a predetermined combination of Q output levels of each flip-flop. Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows an embodiment of the direction discrimination circuit according to the present invention, which includes three flip-flops 20, 22, 24 having only Q outputs and a ROM 26. The first flip-flop 20 has an input terminal IN-1.
The A-phase output of a pulse encoder (not shown) is input data through the second flip-flop 2.
2 uses the B-phase output of the pulse encoder as data input through the input terminal IN-2, and the third flip-flop 24 inputs the Qa of the first flip-flop 20.
Take the output as input data. Input terminal IN-3 is for a clock and supplies a clock to each flip-flop. ROM26 has address inputs A ₀ , A ₁ , A ₂ ,
The Qa output of the first flip-flop 20, the Qb output of the second flip-flop 22, and the Qc output of the third flip-flop 24 are received as output terminals OUT-1, OUT-1, corresponding to the data outputs _D0 , _D1 .
A count up pulse and a count down pulse are respectively supplied to OUT-2. The chip enable CE of the ROM26 is always in the operating state in this embodiment, and the output enable OE is connected to the input terminal IN.
A clock is applied through -3, and it is controlled to output a count pulse after a certain period of time when the output data is established after the address changes.
The storage pattern of the ROM 26 is determined to output count up pulses or count down pulses according to a predetermined combination of Q output levels of each flip-flop. Specifically, the details are as follows. In the circuit shown in FIG. 1 described above, the count-up pulse l and count-down pulse m are generated by the outputs c, _Q1 , _Q2, and _Q3 of each flip-flop.
Corresponds to the combination of j and e. Note that the respective inverted outputs Q ₁ , ₂ and ₃ are represented by outputs Q ₁ , Q ₂ and Q ₃ . Therefore, the following truth table can be obtained from FIGS. 2A and 2B.

[Table] As is clear from the table above, the count-up pulse is given when Q ₁ = “1”, Q ₂ = “0”, and Q ₃
= “0”, and the countdown pulse is given when Q ₁ = “0”, Q ₂ = “0”, Q ₃ = “1”
This is the case. In FIG. 3, it is clear that Qa of the first flip-flop 20 corresponds to the above _Q1 , Qb of the second flip-flop 22 corresponds to the above _Q2 , and Qc of the third flip-flop 24 corresponds to the above _Q3 . Therefore, based on the truth table above, ROM2
By creating 6 memory patterns, it is possible to obtain count-up or count-down pulses in response to movement of the pulse encoder in the forward or reverse direction. In the above embodiment, decoding is performed using a ROM, but it is of course possible to use a PROM, and with this, it is possible to easily switch between count-up and count-down by changing the program. Furthermore, since highly integrated ROMs can be easily obtained, a single ROM is sufficient even when decoding multiple encoder outputs. For example, if a 32 Kbit ROM is used, there are 12 address inputs, so each output of four pulse encoders can be decoded. As can be understood from the above description of the embodiments, the gist of the present invention is as stated in the claims, and therefore, according to the present invention, the device consists of three flip-flops and one ROM. Moreover, the flip-flop only needs to have a Q output, and the configuration is extremely simple compared to the conventional flip-flop that outputs both positive and negative logic polarities. Also, the decoder part is one
Since it is a ROM, the circuit configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a conventional example of a direction discrimination circuit, FIGS. 2A and 2B are operation time charts of the circuit in FIG.
FIG. 3 is an embodiment of a direction discrimination circuit according to the present invention. 20: first flip-flop, 22: second flip-flop, 24: third flip-flop, 2
6:ROM.

Claims (1)

[Claims] 1. A first flip-flop 20 that uses one of the two-phase outputs of the pulse encoder as a data input, a second flip-flop 22 that uses the other as a data input, and the Q output of the first flip-flop 20 as a data input. a third flip-flop 24; and the first, second and third flip-flops 2
Each output Qa, Qb, Qc of 0, 22, 24 is received at each address A ₀ , A ₂ , A ₁ , and each address A ₀ , A ₁ ,
A ROM 26 that generates a count-up pulse only when the acceptance level of _A2 is in a pattern of 1, 0, 0, and generates a count-down pulse only when the pattern is 0, 1, 0. Direction discrimination circuit for pulse encoder output.