JPS58109812A - Output circuit of pulse encoder - Google Patents

Abstract

PURPOSE:To deliver plural pieces of forward and backward revolution information in a cycle of an output pulse with a simple constitution, by latching with two steps the output of a pulse encoder to form an address and then reading out the forward and backward revolution information from a storage means. CONSTITUTION:The waveform is shaped for output pulses PA and PB of a pulse encoder which have a shift of phases and the phase relation reversed between the forward and backward revolutions of a wheel. These output pulses are processed by a double-stage latch circuits 13 and 16 as well as 14 and 17. The addresses are formed with the outputs of these latch circuits, and an access is given to an ROM15. Therefore, for instance, the forward revolution information D1 of a high level is delivered in the case of an address excepting 1000 and synchronizes with a clock PC in response to 2-bit signals AD4, AD5, etc. which control the ROM15. Then plural pieces of forward revolution information are delivered up to 4 units, etc. in a cycle of the pulse PA. The same applies to the backward revolution information. In such a way, plural pieces of forward/backward revolution information are produced in a cycle of an output pulse of an encoder with a simple constitution of a reduced number of component parts. This improves the detecting resolution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit for a /4 pulse empuder that generates two types of pulse signals with the same phase shift in response to rotation of a shaft.

In general, a Δ Luz encoder used for position detection and positioning in a positioning control system has two types of Δ Δ pulses with the same waveform that correspond to the rotation of its axis and are out of phase by 90', as shown in Figure 1. The pulse signals P and PB are generated, and the phase relationship of these pulse signals is reversed when the axis of the pulse encoder rotates forward and backward. In other words, when the axis of the Δ pulse encoder I rotates forward, , as shown in the figure, the signal PA
When the phase of the signal Pa is 90 degrees ahead of the phase of the signal Pa and the axis is reversed, the phase of the signal P1 is 90 degrees ahead of the phase of the signal P.
Go forward 0'.

FIG. 2 shows a conventional example of an output circuit attached to this /4 pulse encoder. In this circuit, the above-mentioned pulse signals Pm and Pm are waveform-shaped by a waveform shaping circuit 1゜2, and the shaped pulse signal P-*PS (see Fig. 3), (e)) will be described later. A NAND circuit N41, N(HK) provided with a direction discrimination circuit KK is added.The non-linear signal P'A, P% is set to a predetermined amount by a differentiating circuit 3°4 and a set trigger circuit 5, 6. Width Noyalus signal pl, i'2 (tlK ''see figure (d)) K-converted %tJiArus signal P 1 #
P2 is applied to the gate input CK of a defroster f7.8 provided in the direction determining circuit section.

The direction determination circuit includes the /ll susu No. P 1a P
z.

Based on P'A and P%, when the Δ pulse encoder is rotating in the forward direction, A pulse encoder is rotating in the forward direction. Next, the operation of this direction discrimination circuit will be explained below.

When the pulse signals P and Pl are not output, and when the encoder is in the stop state IIK, the reset signal R8 for initial setting is added to the reset input R of the differential port, the differential port, and f7.8 via the NOR circuit NrleNr2. At the same time, the above-mentioned reset signal is inputted to the reset manual power R of the D flip-flop 7"9.10 via the inno-otor connection Ivl jv2. As a result, the reset signal is inputted to the reset manual R of the D flip-flop 7"9.10.
Since the D-flip, differential opening, and f9.10 are reset, their outputs Q all become "O". When this initial setting is completed, the reset signal &- disappears.

In such a state, when the /4 encoder rotates forward, the above-mentioned ! The pulse signal P2 triggers the T7 filter f8 to make its output signal s1 [“l”,
As a result, D7 sy 7' 7 Hy f 10 (
The D input becomes '1', therefore, after this D flip 7E!, fl 0t) enter'jJCKKIIE3
When the black signal Pc shown with the diagonal at in FIG.

Since the signal s2 of B is applied to the AND circuit Ad2, the scissors AND circuit d2 becomes operational, and the IF
Then, when the clock signal Pc falls, the output terminal Q of the NOR circuit Nrffi is placed at @o# via the ineater circuit Iv2 and the AND circuit d2.

For this reason, 〒7su, f70. fg is reset and its output signal s1 becomes ``1o'', so when the next clock signal PcO rises, D7 lip flop 7'IO is inverted, and its output signal s2 is shown in FIG. 3(f). ``0''
It becomes 1. At this time, the normal pulse signal R continues to be in the state of ``@1'', and therefore, the above NAND circuit Nd2 outputs the above a check signal PcK as shown in FIG. 3(g).
A synchronized signal Pf is output.

It should be noted that each element shown in the direction discriminating circuit K includes the T7 differential, the D7 differential, the D7 differential flop 9, the NAND circuit Nd1, and the NOR circuit Nr1, and the output signal PIK of the shunt trigger circuit 5. Fuo, full, D
It has the same effect as the NAND circuit N42 and the NOR circuit N,1. That is,
When the pulse embossing axis is reversed, the circuit made up of these elements outputs multiple outputs from the above-mentioned G I2v signal PC, nine pulse cancel signal P, and the NAND circuit Ndl.

The output signals p1 and pr of the direction determining circuit X are used as up and down input signals of a position confirmation circuit of a positioning control system (not shown). Therefore, in the above example, as the nine-crotch signal pc, the position iii is
The synchronous clock signal of the iag counter is used.

The above-mentioned conventional output circuit has a problem that its configuration is complicated and the number of parts is large.In addition, a plurality of output pulse signals are generated during one cycle of the output pulse signal Psol of the pulse encoder. It has the disadvantage that it cannot be applied at all when Pr (Pr) is required.

The present invention is a complete solution to the problems mentioned above.

According to the present invention, the first 2.2. a first latch means, a second latch means for latching the output of the first latch means in accordance with the synchronous clock signal, and receiving the outputs of the first and second latch means as address data; The above object is achieved by providing storage means for outputting forward/reverse data stored in advance in accordance with the address data.

Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings.

FIG. 4 shows an embodiment of the output circuit of the /digital encoder according to the present invention.

In this circuit, the output /f lune signal PAePI at the time of normal rotation of the falsification encoder shown in 5th open can) and (e) is sent to a latch circuit 13.14 via a waveform shaping circuit 11.12, respectively. Added latch circuit 13,
14a, the synchronous tarot signal Pc (
5(a)), the above-mentioned arm pulse signals P and P are turned on at the rising edge of FIG. 5(a)).
) K and their output signals D6. AD1 is the address person cam 0 of 10111 (read-only memory) 15, which will be described later. 16.17. The latch circuits 16 and 17 output the signals AD, # when the synchronous clock signal pc rises, which is added to the latch force.
It latches AD1, and its output signal D,
, ADi (see FIG. 4. Address datum D4 for setting the number of pulse signals Pf and PyO to be described later.

ADs are added.

In the above ROM 15, the data D1w shown in Table 1 below
D2 is stored at each address input terminal. The storage data JpD2 selected by the above-mentioned address data AD and S mountain 5 to be added to MSK are outputted from the data output terminal 01,
Output from 02.

The circuit shown in FIG.
During one period of the pulse compensation signal Pm, P1, a maximum of four normal rotation pulse signals Pfi9 synchronized with the clock/mother pulse signal PcK can be obtained as a reverse rotation pulse signal P. Hereinafter, its operation will be explained with reference to FIG. 5, which shows a tie ζ star chart when the pulse encoder rotates in the normal direction.

Now, in order to obtain one forward rotation/f pulse Pf in the period T, address data IJ)4 #AX)5 are each @0''
, 101, the above four addresses D,
~16 shown in area M of the table above in response to changes in Di.
One of the data D1#D2 is the clock signal P.
It is selected based on the frequency of occurrence of c.

Since the address data D, -Ds during normal rotation of the pulse encoder have the phase relationship shown in FIGS. 5(d) to (g), the address data D0°ADI*
AD2 *ADjka@1 ” # ” 0 ' e
@O' e ” O' K na-)Only at 9 o'clock, tsut)
The normal rotation data D1 changes to @01 only at time 1 (indicated by @positive in the area M of the table), and this state occurs when the next clock signal Pc is generated and the address data ADi Continues until the number reaches 1”K. ζO
As a result, one negative polarity Δlus Pf synchronized with the clock signal Pc is output from the normal rotation side output terminal 01 of the ROM 15 during the period T, as shown in FIG.

In the area M of the table, the address data AD6
e AD1* AD2 a ADB i)E G'
, 'O'', '1''.

@O'', the stored data D2 of the ROM 1B changes to 101, but due to the phase relationship of the output Δ pulse signal PmJl of the encoder shown in FIG. ADl am D2 x ADB @
o, o.

1.0", but the current value is ROM 15.
The output data D2 of the reverse side output terminal 02 of is shown in FIG. 5 (1).
As shown in K, 11" IIK is placed without any change.

When the above-mentioned rotor is reversed, the circuit performs the inverter operation shown in FIG. 6, so that the address data D0. Mu D1. M D2 *ADB @0',
"0', @l', @O'Kf12ft and @ (f
The output data D2 of the reverse output terminal 02 of the ROM 15 becomes 10'' only in the region M of In synchronization with PcK, 91 negative polarity pulse signals P1 are outputted from the ROM 15). Of course, in this case, the above address datums D@IAD1 and AD2.

Since ADi will never be 11" @ 0 #, @ 0", @ 0", as shown in the above R
Output data D1 of normal rotation output terminal 01 of OM 15 is "1"
maintain the state of

Thus, the address data AD4, AD, are @
When the above encoder rotates forward or reverse, one forward rotation/4 pulse signal Pf-1 is output during the output pulse signal PA#PIO period T. is the reverse pulse signal P, and the above ROM
1! ! ] will be output.

The device of the present invention can obtain 2 to 4 output pulses during one period TO of the /4 pulse encoder output Pm eel by changing the address data AD4 and mn5, for example, As shown in area BK of the table, address data AD4*Ds are each set to "0".

In the case of Il#, two Δlunu signals Pf and P are generated within the above period T when the encoder rotates forward and backward, as shown by 'forward' and '1 reverse'. As shown in areas C and D, address data A
D4. AD5 are @l#, @l□# and @l” respectively.
#@1", 3 and 4 forward/reverse/four pulse signals Pf IP during the above period TO
r is synchronized with the clock signal pc, the ROM 1
-5 more output.

In the above embodiment, the phase difference between the Δlume correction signals P and PI is explained as a quarter cycle of the arm pulse signals P and Pl. However, as shown in FIGS. 7(a) and 7(b), when the phase difference φ1 between the pulse signal P and the pulse signal is as small as 1/4 period, and FIG. 7(@) , (d), the same application can be made even when the phase difference φ'1 with the /f pulse signal color 6 is larger than one-fourth period.

Since it is 9, the phase difference φ1 between the nollus signal and 6 is 1/4
If the period is also small, it is necessary to use a clock signal Pc with a period less than the cough phase difference φ1 as the clock signal pc, and the phase difference between the pulse signals Dom and fl is φ'1.
If is larger than 1/4 period, the above blackout signal p
As c, the period from the rising edge of the pulse signal P"s to the falling edge of the pulse signal 60 is less than or equal to φ2 (see FIG. 7(d)).

It is necessary to use a signal PC.

As explained above, according to the present invention, a plurality of pulse encoders (maximum 4) are output during one period of the pulse encoder output/mother pulse signal.
It is possible to obtain forward and reverse rotation data, improving the resolution of the Nords encoder. 9. Forward and reverse rotation data is stored in advance in the ROM K, and is selectively outputted using address data indicating the phase relationship between the output pulses of the lanotator KA4 pulse encoder I, thereby simplifying the circuit.

[Brief explanation of drawings]

Fig. 1←), (bl, waveform diagram showing an example of the output pulse signal of the Noyals encoder, Fig. 2 is)! Rusuenko! Figure 3 shows a conventional example of an output circuit.
~(g) t;j, a tie-building chart showing the operation of the circuit shown in FIG. 2, tIN4 FIG. 4 shows an embodiment of the output circuit of the pulse encoder according to the present invention! The lock diagram, FIGS. 5(a) to (1), and FIGS. 6(a) to (1) are waveform diagrams showing other examples of the force/ff pulse signal. 11.12--Liquid shape shaping circuit, 13.14, 16.1
7...Latch circuit, 15...ROM (read-only memory).

Claims (2)

[Claims] (1) A pulse encoder/pulse encoder that outputs two types of sO pulse signals with the same waveform, which are greatly out of phase and whose phase relationship is reversed when the shaft rotates forward and backward, in response to the rotation of the shaft.
When the shaft rotates in the normal direction, only the normal rotation pulse signal is sent.
In the output circuit of a pulse encoder that outputs only a reverse/false pulse when the axis is reversed, the time corresponding to the phase difference between the two types of medium pulse signals and the pulse whose phase is delayed among the two types of pulse signals. The above two types of pulse signals are each controlled by a synchronized clock signal with a period less than the shorter of the time from which the rising edge of the pulse signal leads in phase from the A edge to the Y edge. Not really. The first latch means that outputs the output from the first latch means #11 and the output from the first latch means O to the synchronized taro,! I'm going to stop by the signal @! 6 latch means and forward/reverse data are stored in advance, and the output signals of the first and second latch means are accepted as address data to form the address data. When the relationship is such that the normal rotation of the final signal is established, the normal rotation data is outputted as the positive@/false sign, and the phase relationship of the four signals is the same as the /l.
9. An output circuit for a pulse encoder, comprising: storage means for outputting reversal data as the reversal pulse signal when the relationship indicates reversal of the pulse encoder. (2) Two types of /4 of the same waveform that are out of phase with each other and whose phase relationship is reversed when the shaft rotates forward and reverse.
It is connected to the a4 Lusenfu/ which outputs a Luss signal corresponding to the rotation of the shaft, and the ΔLusen In the output circuit, the time corresponding to the phase difference between the two types of pulse signals and the rising edge of the pulse signal whose phase is shifted among the two types of pulse signals are the same as the rising edge of the pulse signal whose phase is leading from the edge. A tenth latch means for latching each of the two types of pulse signals separately by a synchronization clock signal having a period less than the shorter of the time to the lower IIXD end and the time O, and the output of the first latch means is synchronized with the output of the first latch means. a second latch means that latches in response to a clock signal; and four signals that store forward/reverse data in advance and receive output signals from the four stages of the first and second latches as address data to form the address data. When the phase relationship of the pulse encoder O indicates normal rotation, positive @ data is output as the normal rotation pulse signal, and the phase relationship of the four signals suggests a reversal of the ∆ pulse encoder. storage means for outputting reversal data as the reversal/reversal signal when the relationship is expressed,
A pulse encoder output circuit characterized in that rounded address data is added to the address data to select and output specific data from among the forward rotation data and reverse rotation data stored in the storage means.