JPH0245804B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an output circuit for a pulse encoder that generates two types of pulse signals having the same waveform but out of phase in response to rotation of a shaft. In general, pulse encoders used in position detection devices of positioning control systems, etc., correspond to the rotation of their shafts and are out of phase with each other, as shown in Figure 1.
Two types of pulse signals P _A and P _B with the same waveform shifted by 90 degrees are generated, and the phase relationship of these pulse signals is reversed when the shaft of the pulse encoder rotates forward and backward.
In other words, when the axis of the pulse encoder is rotating in the normal direction, the phase of the signal P _A as shown in the figure leads the phase of the signal P B by 90 degrees, and when the axis is rotating in the reverse direction, the phase of the signal P _A is 90 degrees ahead of the phase of the signal P B. The phase of _B is less than the phase of signal P _A.
Go 90 degrees. FIG. 2 shows a conventional example of an output circuit attached to this pulse encoder. In this circuit, the pulse signals P _A and P _B are waveform-shaped by waveform shaping circuits 1 and 2, and the shaped pulse signals P' _A and P' _B (see Fig. 3 b and c) are described later. A NAND circuit N _d1 provided in the direction discriminating circuit K,
Added to N _d2 . In addition, the pulse signals P′ _A , P′ _B
is a pulse signal P ₁ of a predetermined pulse width by the differentiating circuits 3 and 4 and the Schmitt trigger circuits 5 and 6.
P ₂ (see Figure 3d), and the pulse signal
P ₁ and P ₂ are applied to clock inputs CK of T flip-flops 7 and 8 provided in the direction determining circuit K. The direction discrimination circuit K receives the pulse signal P ₁ ,
Based on P ₂ , P′ _A , and P′ _B , a pulse signal P _f is formed when the pulse encoder is rotating in the forward direction, and a pulse signal P _r is formed when the pulse encoder is rotating in the reverse direction. The operation of this direction determining circuit K will be explained below. When the pulse signals P _A and P _B are not output, that is, when the encoder is in a stopped state, the reset signal RS for initial setting is added to the reset input R of the T flip-flops 7 and 8 via the NOR circuits N _r1 and N _r2 . At the same time, the reset signal is input to the reset inputs R of the D flip-flops 9 and 10 via the inverter circuits _IV1 and _IV2 . By this,
Since the T flip-flops 7 and 8 and the D flip-flops 9 and 10 are reset, their outputs Q become "0". Note that when this initial setting is completed, the reset signal RS disappears. If the pulse encoder rotates forward in this condition,
The pulse signal P ₂ shown in FIG. 3d triggers the T flip-flop 8 to cause its output signal S ₁ to go to "1", which causes the input D of the D flip-flop 10 to go to "1". Therefore, after that, the input CK of this D flip-flop 10 is
When the clock signal P _C shown shaded in FIG. 3A is input, the D flip-flop 10 is inverted and its output signal S ₂ becomes "1" as shown in FIG. 3F. Since this signal S ₂ is applied to the AND circuit A _d2 , the AND circuit A _d2 becomes operational. Therefore, when the clock signal P _C falls, the inverter circuit I _V4 and the AND circuit A _d2 The output terminal Q of the NOR circuit _{Nr2 is set to "0" via the NOR circuit Nr2} . Therefore, the T flip-flop 8 is reset and its output signal _S1 becomes "0", so that the D flip-flop 10 is inverted at the next rising edge of the clock signal _PC , and its output signal _S2 is shown in FIG. 3f. It becomes “0” as shown in the figure. At this time, the pulse signal
P′ _A continues to be in the “1” state, therefore,
The NAND circuit _Nd2 outputs a signal _Pf synchronized with the clock signal _PC as shown in FIG. 3g. In addition, each element shown in the direction discrimination circuit K is a T flip-flop 7, a D flip-flop 9, and a NAND circuit.
The _Nd1 , NOR circuit _Nr1 , etc. have the same effect on the output signal _P1 of the Schmitt trigger circuit 5 as the above-described elements T flip-flop 8, D flip-flop 10, NAND circuit _Nd2 , NOR circuit _Nr2 , etc. be. That is, the circuit made up of these elements causes the NAND circuit _Nd1 to output a pulse signal _Pr synchronized with the clock signal _PC when the axis of the pulse encoder is reversed. The output signals P _f and P _r of the direction determining circuit K are used as up and down input signals for a position confirmation counter of a positioning control system (not shown). Therefore, in the above example, the clock signal P _C
The synchronous clock signal of the position confirmation counter is used as the position confirmation counter. The conventional output circuit described above has a problem that _its configuration is complicated and the number of parts is large. Also, a plurality of output pulse signals P _{f (} P _r ), it has the disadvantage that it cannot be applied at all. The present invention has been made to solve the above-mentioned problem. According to the present invention, the shaft of the pulse encoder outputs two pulse signals having the same waveform, which are out of phase with each other and whose phase relationship is reversed when the shaft rotates forward and backward, in response to the rotation of the shaft. The time corresponding to the phase difference between the two pulse signals at the time of maximum rotation, and the time from the rising edge of the pulse signal whose phase is delayed to the falling edge of the pulse signal whose phase is leading among the two pulse signals. a first latch means for separately latching two pulse signals outputted from the pulse encoder using a synchronized clock signal having a cycle shorter than the shortest time; a second latch means for latching each latch individually according to a signal; and a phase relation between the address signals which receives the output signals of the first and second latch means as an address signal and indicates normal rotation of the pulse encoder. When it is, normal rotation data is output to output a normal rotation pulse indicating normal rotation of the axis, and when the phase relationship of the signal is such that the pulse encoder is in a reverse rotation, the rotation data of the axis is output. A storage means that stores forward and reverse rotation data in advance at each address so as to output reverse rotation data for outputting a reverse pulse indicating reverse rotation, and outputs the stored forward and reverse rotation data in response to an input address signal. In the output circuit of the pulse encoder comprising: generating a selection signal for selectively setting the number of the forward rotation and reverse rotation pulses in one cycle of the pulse signal output from the pulse encoder, and storing the selection signal in the storage means; The storage means includes a selection signal generation means inputted as an upper address signal of an address signal, and the storage means divides a storage area into a number corresponding to the number of selections set by the selection signal generation means by the upper address signal, The above object is achieved by storing forward and reverse data that generates different numbers of forward and reverse rotation pulses in each of these divided storage areas. Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. FIG. 4 shows an embodiment of an output circuit of a pulse encoder according to the present invention. In this circuit, the output pulse signals P _A and P _B during normal rotation of the pulse encoder shown in FIGS. 13,
Added to 14. The latch circuits 13 and 14 are connected to a synchronous clock signal P _C (see Fig. 5a) applied to the latch input L.
The above pulse signals P _A , P _B are generated at the rising edge of
_The output signals AD ₀ and _{AD 1} shown in FIGS. The latch circuits 16 and 17 are added as latch means. The latch circuits 16 and 17 latch the signals AD ₀ and AD ₁ at the rising edge of the synchronous clock signal _PC applied to the latch input L, and their output signals AD ₂ and AD ₃
(See FIGS. 5f and 5g) are applied to the address input terminals A ₂ and A ₃ of the ROM 15. In addition, ROM15
The above pulse signal is applied to address input terminals A ₄ and A ₅ of
Pulse signal (described later) output during period T of P _A and P _B
Address data AD ₄ and AD ₅ are applied from a selection signal generating means (not shown) that selects and sets the numbers of P _f and P _r . Further, the period τ of the synchronous clock signal is set to be shorter than 1/4 period of the pulse signals P _A and _PB when the shaft to which the pulse encoder is attached rotates at its maximum. The above ROM15 contains the data shown in Table 1 below.
D ₁ and D ₂ are stored, and each of the above address data AD 0 to A ₅ is added to each address input terminal A ₀ to _A 5.
The stored data D ₁ , D ₂ selected by AD ₅ are outputted from its data output terminals O ₁ , O ₂ .

【table】

[Table] The circuit shown in FIG. 4 uses the output data D ₁ or D ₂ of the ROM 15 to generate up to 4 pulses synchronized with the clock pulse signal P _C during the period T of the output pulse signals P _A and P _B of the pulse encoder. It is possible to obtain forward rotation pulse signals P _f or reverse rotation pulse signals P _r . The operation will be described below with reference to FIG. 5, which shows a timing chart when the pulse encoder rotates in the normal direction. Now, in order to obtain one forward rotation pulse P _f during the above period T, address data AD ₄ and AD ₅ are set to "0", respectively.
When set to “0”, the above four address data
Corresponding to the changes in AD ₀ to AD ₃ , one of the 16 pieces of data D ₁ and D ₂ shown in area A of the table is selected at the generation cycle of the clock signal _PC . The address data AD ₀ to AD ₃ during normal rotation of the pulse encoder have the phase relationships shown in FIG. 5 d to g, so that the address data AD ₀ ,
Normal rotation occurs only when AD ₁ , AD ₂ , AD ₃ become "1", "0", "0", "0", that is, only at time t ₁ , t' ₁ , t'' ₁ shown in the same figure. Data _D1 changes to "0" (indicated by "positive" in area A of the table above), and this state continues until the next clock signal P _C is generated and address data _AD2 becomes "1". As a result, the above
A negative polarity pulse P _f synchronized with the clock signal P _C is output from the normal rotation side output terminal O ₁ of the ROM 15 as shown in h in the figure.
is output once during the period T. In area A of the table, the above address data
AD ₀ , AD ₁ , AD ₂ , AD ₃ are “0”, “0”, “1”,
When the data becomes "0", the data _D2 stored in the ROM 15 changes to "0", but in the phase relationship of the output pulse signals P _A and P _B of the encoder shown in FIG. 5, the data _AD0 , AD ₁ , AD ₂ , AD ₃ will never become “0, 0, 1, 0”, therefore, the output data _{D 2} of the reverse side output terminal O 2 of the ROM 15
is kept in the "1" state without changing at all, as shown in FIG. 5i. Next, when the above encoder reverses,
Since the above circuit performs the timing operation shown in FIG. 6, the above address data AD ₀ , AD ₁ , AD ₂ , AD ₃
The above ROM 15 is activated only when the value becomes “0”, “0”, “1”, or “0” (indicated by “reverse” in area A of the table above).
The output data _D2 of the reverse rotation output terminal _O2 becomes "0".
Therefore, as shown in FIG. 1, one negative pulse signal P _r synchronized with the clock signal P _C is outputted from the ROM 15 during the period T. Of course, in this case, the above address data AD ₀ ,
Since AD ₁ , AD ₂ , and AD ₃ never become "1", "0", "0", or "0", as shown in Figure h, the normal output terminal O ₁ of the ROM 15 is Output data _D1 maintains the state of "1". Thus, when the address data AD ₄ and AD ₅ are set to "0" and "0", when the encoder rotates forward or reverse, the period T of the output pulse signals P _A and P _B is One forward rotation pulse signal P _f or one reverse rotation pulse signal P _r is outputted from the ROM 15, respectively. The device of the present invention can obtain 2 to 4 output pulses during one period T of the pulse encoder outputs P _A and _PB by changing the address data AD ₄ and AD ₅ , for example, Area B of the table above
As shown in the figure, when address data AD ₄ and AD ₅ are set to “0” and “1” respectively, “forward” and “reverse”
As shown in , two pulse signals P _f and P _r are generated within the period T when the encoder rotates forward and backward, respectively. Then, as shown in areas C and D of the table, address data AD ₄ and AD ₅ are "1" and "1", respectively.
When set to "0", "1", and "1", the three and four forward/reverse pulse signals P _f and P _r are synchronized with the clock signal P _C during the period T. The data is output from the ROM 15. In the above embodiment, the phase difference between the pulse signals P _A and P _B was explained as being one-quarter period of the pulse signals P _A and P _B , but this phase difference is not limited to one-fourth period. In the case where the phase difference φ ₁ between the pulse signals P′ _A and P′ _B is smaller than one-quarter period as shown in Fig. 7 a and b, and when the phase difference φ 1 between the pulse signals P′ A and P′ B is smaller than one-quarter period, As such, the phase difference φ′ ₁ between pulse signals P″ _A and P″ _B is 4
The same can be applied to cases where the period is larger than one-quarter period. However, even if the phase difference φ ₁ between the pulse signals P' _A and P' _B is smaller than 1/4 period, the phase difference φ ₁ when the shaft to which the pulse encoder is attached rotates to its maximum is used as the above clock signal.
It is necessary to use a clock signal P _C with the following period, and if the phase difference φ' ₁ between the pulse signals _P''A and _P''B is larger than 1/4 period, the pulse encoder is used as the clock signal. Period from the rising edge of pulse signal P″ _B to the falling edge of pulse signal P″ _A when the attached shaft rotates at maximum speed _φ2
(See Figure 7d) It is necessary to use a clock signal P _C with the following period. This is because when the phase difference between the pulse signals P _A and P _B is 90° as shown in FIGS. 5 and 6, and when the phase difference φ ₁ as shown in FIG.
In any case when φ ₁ ', if the period τ of the clock signal P _C is larger than these phase differences, the address data AD ₀ to AD ₃ output from the latch circuits 13, 14, 16, and 17 This is because the periodicity is disrupted and the ROM 15 cannot accurately output the forward rotation pulse signal P _{f and} the reverse rotation pulse signal P _r corresponding to the rotation of the shaft. As explained above, according to the present invention, it is possible to obtain a plurality of pieces (up to 4 pieces) of forward/reverse data during one period of the output pulse signal of the pulse encoder.
The resolution of the pulse encoder can be improved. Also,
Forward/reverse data is stored in the ROM in advance, and these data are selectively output using address data indicating the phase relationship of the output pulses of the pulse encoder, thereby simplifying the circuit.

[Brief explanation of drawings]

1A and 1B are waveform diagrams showing an example of an output pulse signal of a pulse encoder, and FIG. 2 is a block diagram showing a conventional example of an output circuit of a pulse encoder.
3a to 3g are timing charts showing the operation of the circuit shown in FIG. 2, FIG. 4 is a block diagram showing an embodiment of the output circuit of the pulse encoder according to the present invention, and FIG. 5a -i and Figure 6 a-i
7 is a timing chart showing an example of the operation of the embodiment shown in FIG. 4, and FIGS. 7a to 7d are waveform charts showing other examples of output pulse signals of the pulse encoder. 11, 12... Waveform shaping circuit, 13, 14, 1
6, 17...Latch circuit, 15...ROM (read-only memory).

Claims (1)

[Scope of Claims] 1. The shaft of a pulse encoder that outputs two pulse signals of the same waveform that are out of phase with each other and whose phase relationship is reversed when the shaft rotates forward and backward, in response to rotation of the shaft. 2 above at the maximum rotation of
The time corresponding to the phase difference between the two pulse signals and the time corresponding to the phase difference between the two pulse signals.
The clock signal is transmitted from the pulse encoder by a synchronous clock signal having a period shorter than the time from the rising edge of the pulse signal whose phase is delayed to the falling edge of the pulse signal whose phase is leading among the two pulse signals. a first latch means for individually latching the two output pulse signals; a second latch means for separately latching the output of the first latch means by the synchronous clock signal; The output signal of the second latch means is received as an address signal, and when the phase relationship of the address signal indicates normal rotation of the pulse encoder, a normal rotation pulse indicating normal rotation of the shaft is outputted. When the phase relationship of the signals is such that the pulse encoder indicates a reverse rotation, outputs reverse rotation data for outputting a reverse pulse indicating a reverse rotation of the shaft. In an output circuit of a pulse encoder, the output circuit includes a memory means for storing reverse data in each address in advance and outputting forward and reverse data stored in correspondence with an input address signal, further comprising a selection signal generating means for generating a selection signal for selectively setting the number of the forward rotation and reverse rotation pulses in one cycle, and inputting the selection signal to the storage means as an upper address signal of the address signal; The storage means divides the storage area into a number corresponding to the selection setting number of the selection signal generation means according to the upper address signal, and each of these divided storage areas receives a different number of forward and reverse rotation pulses. An output circuit for a pulse encoder, characterized in that forward/reverse data generated is stored.