JPH03113611A - Reference voltage generation circuit - Google Patents

Abstract

PURPOSE:To reduce the number of terminals by using a binary counter for a trimming circuit connected to a decoder circuit and sharing the clock input terminal of the binary counter and the power terminal of PROM. CONSTITUTION:A DELTAVT-type reference voltage source 1, the decoder circuit 2 making a reference voltage VOUT to be optimum, a serial resistance network consisting of resistors R1 and R2 and a resistor (r) and the trimming circuit 3 which trims the input of the decoder circuit 2 are provided. The trimming circuit 3 is provided with the n-bit binary counter which is connected in serial by n-bits and programmable ROM which sets the output to be an input, and the clock input of an initial stage is shared with the power source of programmable ROM. Thus, the number of the terminals is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit using a resistor network, a decoder circuit, and a trimming circuit.

[Conventional technology]

Conventionally, this type of reference voltage generation circuit uses a programmable ROM (hereinafter referred to as FROM) of a trimming circuit to set the reference voltage to a desired value. In this case, FRO
The trimming code to be written to M is transferred using a number of terminals. Furthermore, the initial value of the reference voltage source output voltage is measured only once.

FIG. 5 is a block diagram of a conventional reference voltage generation circuit.

As shown in FIG. 5, the conventional reference voltage generation circuit has ΔV
It is composed of a T-type reference voltage source l (another voltage source may be used), a decoder circuit 2, a trimming circuit 3, and a series resistance network consisting of resistors R1, R2, and r. In this resistor network, the resistor r is repeatedly used as a unit resistance cell, the connecting point between the resistors R1 and r is jl, the connecting point between the resistor r and the next r is j2, the subsequent connecting points are j6, and so on. There is even. The decoder circuit 2 selects one of the connection points j1 to j64 according to the values of n-bit (hereinafter, 6 bits are taken as an example) data D0 to D from the trimming circuit 3, and selects the output from the n-bit data D0 to D. It is input to the ΔVT type standard reference voltage source single-inverting input terminal.

FIG. 6 is a diagram of the trimming circuit shown in FIG.

As shown in FIG. 6, the conventional trimming circuit 3A is composed of PROM cells 10-15 with test functions and shift registers 26-31 with reset input. These shift registers 26 to 31 with reset input have a test function.
Its purpose is to supply write data to each FROM cell 16 of ROM cells IO to 15. On the other hand, the terminals of PROM cells 10 to 15 with test function. ~D is the output terminal to the decoder circuit 2, TEST is the input terminal and PR
Output the data of OM cell 16 or shift/
This is a terminal for selecting whether to output the data of registers 26 to 31. Also, ■.

is a power supply terminal for writing into the PROM cell 16, and writes by applying a high voltage. Furthermore, RESET is a reset input terminal for initializing the shift registers 26 to 31, SD is a serial data input terminal for the shift registers 26 to 31, and CLK is a transfer lock terminal for transferring serial data. It is. Note that VOUT is the output terminal of the reference voltage source 1, and the terminal voltage of VOUT is assumed to be ΔV.

Next, the operation of such a conventional reference voltage generation circuit will be explained.

FIG. 7 is a timing diagram for explaining the circuit operation centered on the trimming circuit in FIGS. 5 and 6. FIG.

As shown in FIG. 7, Vpp is 0, 1, Vpp
The three values are O, Ov21 and VD.
DvPP is a high voltage exceeding the level of 1. Note that the term "timing" refers to the operating state at each time.

First, timing (2) is in an undefined state, and it is unknown what values the shift registers 26 to 31 will have.

Next, at timing (2), the reset terminal RESET is set to O to initialize the data in the shift registers 26-31.

That is, the output Q of shift registers 26-31. -Q
Let 5 be 0.

Next, at timing (2), the reference voltage source output voltage V is measured. The condition at this time is that the TEST signal is 0. In this case, D.

=Q, =O,D, =Q, =O,..., D s =
Q s = O, and the value of the reference voltage source output voltage V is the value when the decoder circuit 2 selects the connection point j1.

Therefore, in order to obtain the desired reference voltage source output voltage V, based on the initial value of the reference voltage source output voltage V, trimming and
Calculate food. In this Figure 7, D, ~D0 = 1
It is assumed that a trimming code of 00101 is calculated.

Next, at timing (2), the above data is sent to the serial data input terminal SD, a transfer lock is supplied to the transfer lock terminal CLK, and a trimming code is set. Next, at timing (2), the TEST signal is set to 0, the trimming code set to the decoder circuit 2 is applied, and the reference voltage source output voltage V according to the trimming code is measured. Once the desired reference voltage source output voltage v1 is obtained, proceed to FROM writing at timing ①.
If not, a correction trimming code that fills the difference with the desired reference voltage source output voltage V is added or subtracted, and the timing (2) is repeated again. At the above timing ■, the set trimming code is transferred to PROM cell 1.
6, and the power supply terminal Vpp maintains a high voltage only for the time required to write the trimming code to FROM. Next, at timing 2, writing of the trimming code is completed.

[Problem to be solved by the invention]

The conventional reference voltage generation circuit described above requires a large number of terminals to transfer the trimming code to be written to the FROM, and has the disadvantage that the number of pin terminals in the package increases. Furthermore, in the conventional reference voltage generation circuit described above, the initial value of the reference voltage source output voltage can only be measured at one point in order to calculate the trimming code.
The drawback is that it lacks precision.

An object of the present invention is to provide a reference voltage generation circuit that reduces the number of terminals and improves accuracy.

[Means to solve the problem]

The reference voltage generating circuit of the present invention includes a resistor network and n (
n is a natural number) the input decoder circuit and the decoder circuit
a reference voltage source connected to the resistor network and one end of the resistor network;
A trimming circuit having an n-bit binary counter to be connected in series with n-bits and a programmable ROM that inputs the output of the n-bit binary counter, and a trimming circuit that sets the output of the final stage of the n-bit binary counter to 1 and 1. Q output from the first stage to before the final stage is 0.
n bits of the trimming circuit;
The first stage clock input of the binary counter is configured to be shared with the power supply of the programmable ROM.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a reference voltage generation circuit showing a first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a ΔvT type reference reference voltage source 1 has a reference voltage V. It has a decoder circuit 2 for optimizing 1T, a series resistance network consisting of resistors R+, R2 and 63 resistors r, and a trimming circuit 3 for trimming the input of the decoder circuit 2. Among the resistors, r is repeatedly used as a unit resistance cell, and the connecting point between resistors R1 and r is J1, the connecting point between r and the next r is J2, and the subsequent connecting points are formed up to J64. The decoder circuit 2 determines the connection points j1 to j based on the values of n-bit (hereinafter, 6 bits will be taken as an example) data D0 to D from the trimming circuit 3.
$4 is selected, and the potential at that point is input to the inverting input terminal of 1 (which may be a ΔvT type reference reference voltage source).

FIG. 2 is a configuration diagram of the trimming circuit shown in FIG. 1.

As shown in FIG. 2, the trimming circuit 3 includes binary counters 4 to 8 with reset inputs and reset inputs.
A that takes the AND of the binary counter 9 with preset input, the FROM cells 10 to 15 with test function, the RESET signal, and the PRESET signal, and uses the output as the reset (π) input of the binary counters 4 to 9.
It is composed of an ND gate 17. Terminal. ~D5 is an output terminal to the decoder circuit 2, and the above-mentioned RESET signal terminal is a reset input terminal for initializing the binary counters 4 to 8 with reset input and the binary counter 9 with reset/preset input. be. Also,
The PRESET signal terminal is a preset input terminal for setting the binary counter 9 with reset/preset input to 1.

Furthermore, the CLK terminal, which is the center of this embodiment, is a binary terminal.
A clock input terminal for counting up counters 4 to 9, and a FROM cell 1 with test function.
This is a test terminal for selecting whether to output 0 to 150FROM data to output terminals D0 to D5 or output the values of binary counters 4 to 9.
It also serves as a power supply terminal for writing to the M cell 16.

Next, the operation of the reference voltage generation circuit described above will be explained.

FIG. 3 is a timing diagram for explaining the circuit operation centered on the trimming circuit in FIGS. 1 and 2. FIG.

As shown in FIG. 3, CLK is 0, 1 . There are three values: V, P, 0 OV, 1 VH), Vpp
This is a high voltage that exceeds the level of C1. Moreover, the term "timing" means the operating state at each time.

First, the timing ■ is in an undefined state, and the binary
It is unknown what kind of data exists in counters 4 to 9.

At timing (2), the reset terminal RESET is set to 0 to initialize the data in the binary counters 4-9. That is, the binary counter output Q. - Let Q5 be O.

At timing (2), the reference voltage source output voltage v1 is measured. The conditions at this time are that the CLK input terminal must be set to CLKO during or before resetting. In this case. −Q,=0, D+=Q+=0,・
..., D s = Q s = O, and the value of the output voltage v1 of the reference voltage source 1 is the value of the output voltage v1 of the decoder circuit 2 at the connection point j1.
This is the value when .

At timing ■, the preset terminal PRESET is set to O, and the output of the n-th stage binary counter 9 is set to 1.
The outputs of the first to (n-1)th stage binary counters 4 to 8 are set to 0.

At timing (2), the reference voltage source output voltage V33 is measured. In this case, Do”Qo=O,I)+=Q+=0,・
..., ])4=Q4=Q, D5=Q, =0, and the value of the reference voltage source output voltage V33 is determined by the decoder circuit 2 at the connection point j.
, x is the value of the selected state. Here, the reference voltage source output voltages V, , V3. A trimming code is calculated to obtain the desired reference voltage source output voltage , based on the value of . In FIG. 3, it is assumed that the trimming codes D5 to D o "101011 have been calculated, and the number of input clocks of the binary counter is set to 43.

At timing (2), the number of input clocks (43) set at the above-mentioned timing (2) is input to CLK and counted up. The process stops after counting up 43 CLKs.

At timing (2), CLK is set to 0, a trimming code is given to the decoder circuit 2, and the reference voltage source output voltage V according to the trimming code is measured. Once the desired reference voltage source output voltage (2) is obtained, the process proceeds to the FROM writing at the timing (2) described above. If not, a correction trimming code to fill in the difference with the desired reference voltage source output voltage V is added or subtracted, and the operations at timings 1 to 2 are repeated again.

In Timing■, set the trimming code to F.
Leave the input in ROM cell 16, and set CLK to P.
The high voltage is held for only the time necessary to write data to the ROM.

At timing ■, the writing of the trimming code is completed. Note that CLK must be pulled up to the "1" level after writing is completed.

Next, a method for calculating the above-mentioned trimming code will be described.

First, the following relationship exists between the reference voltage source output voltage {circle around (2)}, the resistors R1, R2°, and the connection point j.

・・・・・・(1) Here, ■1° is an offset voltage.

Next, the value of the reference voltage source output voltage ■1 when j=1 is vl
, the value of the reference voltage source output voltage v1 when j=33 is VS2
Then, ■ and VS2 are as follows from equation (1) above.

here, From equation (3), equation (2) can be expressed as Then, ・・・・・・(4) becomes.

The following equation is obtained from equations (3) and (4) above.

Next, by substituting and rearranging equations (4) and (5) into equation (1), the following equation is obtained.

2 j=-+65 (6) Therefore, from this equation (6), the reference voltage source output voltages v1 and V3
By measuring 3, the connection point j can be found. In other words, the trimming code has been calculated.

FIG. 4 is a configuration diagram of a trimming circuit for explaining a second embodiment of the present invention.

As shown in FIG. 4, this embodiment differs from the trimming circuit in the first embodiment described above in determining whether or not to use a binary counter with reset input, a binary counter with reset/preset input, and the like. Output Q. -Q,
a NOR gate 24 that detects whether all are "0";
The trimming circuit 3 uses a NOR gate 25 that detects whether the output Q is "1" and Q0 to Q4 are "0".
O~15, binary counters 18~23, and outputs Q0~Q5 of binary counters 18~23 are all 0.
” to detect that N.

It consists of an R gate 24 and a NOR gate 25 which detects that the outputs Q of the binary counters 18 to 23 are "1°" and the output Q.-Q4 is 0".

Here, in the first embodiment described above, the outputs Q0 to Q of the binary counters 4 to 9 were initialized by turning on the reset input RESET, but in this second embodiment, Monitor the outputs V and Q of the NOR gate 24, and if they are "0°", the binary counters 4 to 9
Since at least one of the outputs Q0 to Q of is '1'', a clock is inputted by CLK and continues to be inputted until the output V + Q of the NOR gate 24 becomes 1.The output V + Q of this NOR gate 24 When detects 1, the clock input is stopped and the reference voltage source output voltage v1 is measured.Next, the output V33 of the NOR gate 25 is
Monitor Q, and if it is OI+, output of binary counter 23 and binary counters 18 to 2 are output.
2 output Q. Since at least one of the outputs of -Q4 is "1", a clock is input using CLK, and the clock continues to be input until the output V33Q of the NOR gate 25 becomes 1. The output V 3s Q of this NOR gate 25 is 1
Upon detection of V33, the clock input is stopped and the reference voltage source output voltage V33 is measured. At the same time, trimming is performed based on the reference voltage source output voltages V1 and V33.
The code is calculated and the number of input clocks for the binary counters 18-23 is set. Here, since there is no reset input to binary counters 18 to 23, binary counters 18 to 23 have no reset input, so
- Since it is not known whether the values of the counters 18 to 23 are "0" or "1" at first, the reference voltage source output voltage v1 is not necessarily measured first. Therefore, the Q outputs of the binary counters 18 to 23 immediately before counting up are Q, ~Q o ”
ooooooo or Qs ~QO= 100000
I don't know which one. Therefore, which of the output V, Q=1 of the NOR gate 24 and the output v33Q=1 of the NOR gate 25 is detected first is known outside the trimming circuit 3, and the number of input clocks is controlled accordingly.

The following operation is similar to the operation of the first embodiment described above, from counting up at timing (2) to completion at timing (2) in FIG.

[Effects of the Invention] As explained above, the reference voltage generation circuit of the present invention uses a binary counter instead of a shift register in the trimming circuit connected to the decoder circuit, and the clock of this binary counter By sharing the input terminal and the power supply terminal of the FROM, there is an effect that the number of terminals can be reduced. Furthermore, the present invention has the advantage that accuracy can be improved because the initial value of the reference voltage source output voltage can be measured twice in order to calculate the trimming code.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a reference voltage generation circuit showing a first embodiment of the present invention, FIG. 2 is a configuration diagram of a trimming circuit shown in FIG. 1, and FIG. 3 is a trimming diagram in FIGS. 1 and 2. A timing diagram for explaining the circuit operation centered on the circuit, FIG. 4 is a configuration diagram of a trimming circuit for explaining the second embodiment of the present invention, and FIG. 5 is a reference voltage generation diagram showing a conventional example. FIG. 6 is a block diagram of the circuit, FIG. 6 is a configuration diagram of the trimming circuit shown in FIG. 5, and FIG. 7 is a timing diagram for explaining the circuit operation centered on the trimming circuit in FIGS. 5 and 6. 1...ΔvT type reference reference voltage source...Tecoder circuit, 3...Trimming circuit, 4-8...
...Binary counter with reset input, 9.
...Binary counter with reset/preset input, lO~15...FROM with test function
Cell, 16...PROM cell, 17...
・AND gate, 18-23...Binary counter, 24.25...NOR gate, R+
+ R, 2r r...Resistance, J1~jet...
...Net connection point between resistors.

Claims (1)

[Claims] a resistor network, a decoder circuit with n inputs (n is a natural number) connected to each point of the resistor network to optimize the reference voltage, and a reference voltage connected to one end of the decoder circuit and the resistor network. n bits connected in series with the source and n bits in series.
A trimming circuit having a binary counter and a programmable ROM which inputs the output of the n-bit binary counter, and a trimming circuit that sets the output of the final stage of the n-bit binary counter to 1 and sets the Q from the first stage to before the final stage. 1. A reference voltage generating circuit comprising means for setting an output to 0, and sharing a first stage clock input of an n-bit binary counter of the trimming circuit with a power source of the programmable ROM.