JPH0252470U

JPH0252470U -

Info

Publication number: JPH0252470U
Application number: JP13197088U
Authority: JP
Priority date: 1988-10-08
Filing date: 1988-10-08
Publication date: 1990-04-16
Anticipated expiration: 2003-10-08
Also published as: JPH0644127Y2

Description

[Brief explanation of drawings]

第１図から第１１図までは本考案の実施例を示
し、第１図は混成集積回路装置の斜視図、第２図
は第１図の―視側面図、第３図は組み込み状
態を示す斜視図、第４図は第１図の―視拡大
断面図、第５図は第１図の―視拡大断面図、
第６図は第２実施例の断面図、第７図は第３実施
例の平面図、第８図は正面図、第９図は第４実施
例の平面図、第１０図は第５実施例の一部切欠き
側面図、第１１図は第１０図の―視拡大
断面図、第１２図は従来技術の断面図である。１，１１……混成集積回路装置、２，１２，１
３，３７，３８，５３，５４，５８，５９，６０
，６１，６２，６３，６７，６９……基板、４ａ
，４ｂ……配線、５……スルーホール、６……導
体、７，１６，７５……外部接続用端子、８，１
４……母基板、２０，２１，３９，６７……細長
溝、２２……足部、２３，２４ａ，２４ｂ，２５
ａ，２５ｂ，２６，２７ａ，２７ｂ，２８ａ，２
８ｂ，４０ａ，４０ｂ，４１ａ，４１ｂ，４２，
５５，５６，６４，６５，７０ａ，７０ｂ，７１
ａ，７１ｂ，７２ｄ……固定パツド、１０，１９
，２９，３２，３５，３６，４４，４７，５０，
５７，６６，７３……半田、３０，３１，３３，
３４，４３，４８，５２……配線部。 1 to 11 show embodiments of the present invention, FIG. 1 is a perspective view of a hybrid integrated circuit device, FIG. 2 is a side view of FIG. 1, and FIG. 3 is an assembled state. A perspective view, FIG. 4 is an enlarged sectional view of FIG. 1, and FIG. 5 is an enlarged sectional view of FIG.
6 is a sectional view of the second embodiment, FIG. 7 is a plan view of the third embodiment, FIG. 8 is a front view, FIG. 9 is a plan view of the fourth embodiment, and FIG. 10 is a plan view of the fifth embodiment. FIG. 11 is an enlarged cross-sectional view of FIG. 10, and FIG. 12 is a cross-sectional view of the prior art. 1, 11...hybrid integrated circuit device, 2, 12, 1
3, 37, 38, 53, 54, 58, 59, 60
, 61, 62, 63, 67, 69...Substrate, 4a
, 4b... Wiring, 5... Through hole, 6... Conductor, 7, 16, 75... External connection terminal, 8, 1
4... Mother board, 20, 21, 39, 67... Elongated groove, 22... Foot portion, 23, 24a, 24b, 25
a, 25b, 26, 27a, 27b, 28a, 2
8b, 40a, 40b, 41a, 41b, 42,
55, 56, 64, 65, 70a, 70b, 71
a, 71b, 72d...Fixed pad, 10, 19
,29,32,35,36,44,47,50,
57, 66, 73... solder, 30, 31, 33,
34, 43, 48, 52... Wiring section.

Claims

[Scope of utility model registration request]

In a hybrid integrated circuit device consisting of a plurality of substrates, at least one of the substrates is cut out with a long and narrow groove into which the other substrate intersects, and the front and back surfaces of both substrates, or one side thereof, are provided with the grooves of the two substrates. A hybrid integrated circuit device, characterized in that conductive fixing pads are provided in proximity to each intersection, and the fixing pads on one of the substrates facing each other at the intersection are fixed by soldering to the other fixing pad.