JPH0251462U - - Google Patents

Info

Publication number
JPH0251462U
JPH0251462U JP13054788U JP13054788U JPH0251462U JP H0251462 U JPH0251462 U JP H0251462U JP 13054788 U JP13054788 U JP 13054788U JP 13054788 U JP13054788 U JP 13054788U JP H0251462 U JPH0251462 U JP H0251462U
Authority
JP
Japan
Prior art keywords
image
line
signal
electrical signal
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13054788U
Other languages
Japanese (ja)
Other versions
JPH0722927Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988130547U priority Critical patent/JPH0722927Y2/en
Publication of JPH0251462U publication Critical patent/JPH0251462U/ja
Application granted granted Critical
Publication of JPH0722927Y2 publication Critical patent/JPH0722927Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Facsimile Scanning Arrangements (AREA)
  • Editing Of Facsimile Originals (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第13図はこの考案の一実施例を示し
たもので、各図は次のものを表している。第1図
はデジタル式電子複写装置の側面構造図、第2図
は第1図に於ける〜断面図、第3図は原稿台
の構造説明図、第4図は信号処理部の構成ブロツ
ク図、第5図は拡大画像用のサンプリングタイミ
ング生成回路と、スレツシヨルドレベル生成部の
ブロツク図、第6図は正・鏡像の書込・読出し回
路図、第7図は縮小時のサンプリングクロツク生
成回路図、第8図は中央印字制御のための回路図
(正像の場合)、第9図はストローブ発生回路図
、第10図はストローブ巾監視部のブロツク図、
第11図はサーマルヘツドの斜視図、第12図は
サーマルヘツドの構成図、第13図Aはストロー
ブ巾制御なしに、副走査方向縮小時の記録画素の
重なりを示す作用説明図、第13図Bは副走査送
りに対応してストローブ巾制御をした時の、記録
画素を示す作用説明図。
1 to 13 show one embodiment of this invention, and each figure represents the following. Fig. 1 is a side structural diagram of the digital electronic copying device, Fig. 2 is a sectional view of Fig. 1, Fig. 3 is an explanatory diagram of the structure of the document table, and Fig. 4 is a block diagram of the configuration of the signal processing section. , Fig. 5 is a block diagram of the sampling timing generation circuit for enlarged images and the threshold level generation section, Fig. 6 is a write/read circuit diagram for normal and mirror images, and Fig. 7 is a sampling clock for reduction. Figure 8 is a circuit diagram for central printing control (in the case of normal image), Figure 9 is a strobe generation circuit diagram, Figure 10 is a block diagram of the strobe width monitoring section,
Fig. 11 is a perspective view of the thermal head, Fig. 12 is a configuration diagram of the thermal head, Fig. 13A is an explanatory diagram of the operation showing the overlap of recording pixels when reducing in the sub-scanning direction without strobe width control, Fig. 13 B is an explanatory diagram showing the operation of recording pixels when strobe width is controlled in response to sub-scanning feed.

Claims (1)

【実用新案登録請求の範囲】 原稿の画像情報を電気信号にして出力するイメ
ージセンサユニツトと、この電気信号を符号化し
てライン毎に記憶する記憶手段、および、この記
憶された画像信号をライン毎にシリアルに読み出
す読出し手段から成る信号処理部と、読み出され
た前記画像信号を受けて記録紙に印字する記録部
とから成る画像形成装置において、 記録時に正像とするか鏡像とするかを選択する
選択手段と、読み出し手段における正像用ならび
に鏡像用のそれぞれ、もしくは共用のアドレス信
号回路と、記憶手段が1バイト1ビツト構成で無
い場合、読み出し手段における正像用ならびに鏡
像用のそれぞれ、もしくは共用の記憶手段の構成
ビツト数に応じたパラレル/シリアル変換回路と
を設けたことを特徴とする画像形成装置。
[Claims for Utility Model Registration] An image sensor unit that converts image information of a document into an electrical signal and outputs it, a storage unit that encodes this electrical signal and stores it line by line, and a storage unit that encodes the electrical signal and stores it line by line. In an image forming apparatus consisting of a signal processing section consisting of a reading means that serially reads out the image signal, and a recording section that receives the read image signal and prints it on recording paper, it is possible to decide whether to make a normal image or a mirror image at the time of recording. Selection means for selection, respective or shared address signal circuits for the normal image and mirror image in the readout means, and address signal circuits for the normal image and mirror image in the readout means if the storage means is not configured with 1 byte and 1 bit; Alternatively, an image forming apparatus characterized in that it is provided with a parallel/serial conversion circuit according to the number of bits constituting the shared storage means.
JP1988130547U 1988-10-05 1988-10-05 Image forming device Expired - Lifetime JPH0722927Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988130547U JPH0722927Y2 (en) 1988-10-05 1988-10-05 Image forming device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988130547U JPH0722927Y2 (en) 1988-10-05 1988-10-05 Image forming device

Publications (2)

Publication Number Publication Date
JPH0251462U true JPH0251462U (en) 1990-04-11
JPH0722927Y2 JPH0722927Y2 (en) 1995-05-24

Family

ID=31385814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988130547U Expired - Lifetime JPH0722927Y2 (en) 1988-10-05 1988-10-05 Image forming device

Country Status (1)

Country Link
JP (1) JPH0722927Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114080A (en) * 1983-11-25 1985-06-20 Canon Inc Picture processing system
JPS6335163U (en) * 1986-08-25 1988-03-07

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114080A (en) * 1983-11-25 1985-06-20 Canon Inc Picture processing system
JPS6335163U (en) * 1986-08-25 1988-03-07

Also Published As

Publication number Publication date
JPH0722927Y2 (en) 1995-05-24

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