JPH0251463U - - Google Patents

Description

[Brief explanation of drawings]

1 to 13 show one embodiment of this invention, and each figure represents the following. Fig. 1 is a side structural diagram of the digital electronic copying device, Fig. 2 is a sectional view of Fig. 1, Fig. 3 is an explanatory diagram of the structure of the document table, and Fig. 4 is a block diagram of the configuration of the signal processing unit. , Fig. 5 is a block diagram of the sampling timing generation circuit for enlarged images and the threshold level generation section, Fig. 6 is a write/read circuit diagram for normal and mirror images, and Fig. 7 is a sampling clock for reduction. Figure 8 is a circuit diagram for central printing control (in the case of normal image), Figure 9 is a strobe generation circuit diagram, Figure 10 is a block diagram of the strobe width monitoring section,
Fig. 11 is a perspective view of the thermal head, Fig. 12 is a configuration diagram of the thermal head, Fig. 13A is an explanatory diagram of the operation showing the overlap of recording pixels when reducing in the sub-scanning direction without strobe width control, Fig. 13 B is an explanatory diagram showing the operation of recording pixels when strobe width is controlled in response to sub-scanning feed.

Claims (1)

[Claims for Utility Model Registration] An image sensor unit that converts image information of a document into an electrical signal and outputs it, a storage unit that encodes this electrical signal and stores it line by line, and encodes and stores the stored image signal line by byte. In an image forming apparatus consisting of a signal processing section consisting of a reading means for serially reading out the image signals, and a recording section for receiving the read image signals and printing them on recording paper, in order to obtain a record that is smaller than the original, A reduction mode sampling clock generation circuit that generates a thinned-out sampling clock, and a half of the margin generated by the reduction are created at the beginning of the line by using the address counter of the reading means. a circuit that prohibits clock input during one period; and a gate circuit that transmits the serial output signal of the reading means only after the prohibited address signal is subtracted from all address signals for reading. An image forming apparatus characterized by having a central printing control circuit.