JPH0251463U - - Google Patents
Info
- Publication number
- JPH0251463U JPH0251463U JP13054988U JP13054988U JPH0251463U JP H0251463 U JPH0251463 U JP H0251463U JP 13054988 U JP13054988 U JP 13054988U JP 13054988 U JP13054988 U JP 13054988U JP H0251463 U JPH0251463 U JP H0251463U
- Authority
- JP
- Japan
- Prior art keywords
- line
- signal
- image
- reading means
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 11
- 238000012544 monitoring process Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Landscapes
- Facsimile Scanning Arrangements (AREA)
- Editing Of Facsimile Originals (AREA)
Description
第1図〜第13図はこの考案の一実施例を示し
たもので、各図は次のものを表している。第1図
はデジタル式電子複写装置の側面構造図、第2図
は第1図に於ける〜断面図、第3図は原稿台
の構造説明図、第4図は信号処理部の構成ブロツ
ク図、第5図は拡大画像用のサンプリングタイミ
ング生成回路と、スレツシヨルドレベル生成部の
ブロツク図、第6図は正・鏡像の書込・読出し回
路図、第7図は縮小時のサンプリングクロツク生
成回路図、第8図は中央印字制御のための回路図
(正像の場合)、第9図はストローブ発生回路図
、第10図はストローブ巾監視部のブロツク図、
第11図はサーマルヘツドの斜視図、第12図は
サーマルヘツドの構成図、第13図Aはストロー
ブ巾制御なしに、副走査方向縮小時の記録画素の
重なりを示す作用説明図、第13図Bは副走査送
りに対応してストローブ巾制御をした時の、記録
画素を示す作用説明図。
1 to 13 show one embodiment of this invention, and each figure represents the following. Fig. 1 is a side structural diagram of the digital electronic copying device, Fig. 2 is a sectional view of Fig. 1, Fig. 3 is an explanatory diagram of the structure of the document table, and Fig. 4 is a block diagram of the configuration of the signal processing unit. , Fig. 5 is a block diagram of the sampling timing generation circuit for enlarged images and the threshold level generation section, Fig. 6 is a write/read circuit diagram for normal and mirror images, and Fig. 7 is a sampling clock for reduction. Figure 8 is a circuit diagram for central printing control (in the case of normal image), Figure 9 is a strobe generation circuit diagram, Figure 10 is a block diagram of the strobe width monitoring section,
Fig. 11 is a perspective view of the thermal head, Fig. 12 is a configuration diagram of the thermal head, Fig. 13A is an explanatory diagram of the operation showing the overlap of recording pixels when reducing in the sub-scanning direction without strobe width control, Fig. 13 B is an explanatory diagram showing the operation of recording pixels when strobe width is controlled in response to sub-scanning feed.
Claims (1)
ージセンサユニツトと、この電気信号を符号化し
てライン毎に記憶する記憶手段、および、この記
憶された画像信号をバイト毎にシリアルに読み出
す読み出し手段から成る信号処理部と、読み出さ
れた前記画像信号を受けて記録紙に印字する記録
部とから成る画像形成装置において、 原稿よりも縮小された記録を得るために、間引
きされたサンプリングクロツクを生成する縮小モ
ードサンプリングクロツク生成回路と、縮小され
て生じる余白部分の二分の一を、ライン先頭部分
に作成するため、読み出し手段のアドレスカウン
タに、前記余白部分の二分の一の期間中、クロツ
ク入力を禁止する回路と、読み出しの全アドレス
信号分から、前記禁止されたアドレス信号分を差
引いた以降にのみ、前記読み出し手段のシリアル
出力信号を発信するゲート回路とから成る、中央
印字制御回路を設けたことを特徴とする画像形成
装置。[Claims for Utility Model Registration] An image sensor unit that converts image information of a document into an electrical signal and outputs it, a storage unit that encodes this electrical signal and stores it line by line, and encodes and stores the stored image signal line by byte. In an image forming apparatus consisting of a signal processing section consisting of a reading means for serially reading out the image signals, and a recording section for receiving the read image signals and printing them on recording paper, in order to obtain a record that is smaller than the original, A reduction mode sampling clock generation circuit that generates a thinned-out sampling clock, and a half of the margin generated by the reduction are created at the beginning of the line by using the address counter of the reading means. a circuit that prohibits clock input during one period; and a gate circuit that transmits the serial output signal of the reading means only after the prohibited address signal is subtracted from all address signals for reading. An image forming apparatus characterized by having a central printing control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13054988U JPH0251463U (en) | 1988-10-05 | 1988-10-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13054988U JPH0251463U (en) | 1988-10-05 | 1988-10-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0251463U true JPH0251463U (en) | 1990-04-11 |
Family
ID=31385818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13054988U Pending JPH0251463U (en) | 1988-10-05 | 1988-10-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0251463U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128671A (en) * | 1984-11-28 | 1986-06-16 | Canon Inc | Image recording device |
JPS63167567A (en) * | 1986-12-27 | 1988-07-11 | Konica Corp | Image processor having editing function |
-
1988
- 1988-10-05 JP JP13054988U patent/JPH0251463U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128671A (en) * | 1984-11-28 | 1986-06-16 | Canon Inc | Image recording device |
JPS63167567A (en) * | 1986-12-27 | 1988-07-11 | Konica Corp | Image processor having editing function |
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